ARM: dts: enable framebuffer in hi4511

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Conflicts:
	arch/arm/boot/dts/hi3620.dtsi

2 files changed, 149 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index 20cc4def98fd..570eaef9d275 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -1484,5 +1484,101 @@
 
 			pinctrl-single,register-width = <32>;
 		};
+
+		/* unremovable emmc as mmcblk0 */
+		dwmmc_1: dwmmc1@fcd04000 {
+			compatible = "hisilicon,hi4511-dw-mshc";
+			reg = <0xfcd04000 0x1000>;
+			interrupts = <0 17 4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&mmcclk1>, <&ddrcperclk>;
+			clock-names = "ciu", "biu";
+		};
+
+		/* sd as mmcblk1 */
+		dwmmc_0: dwmmc0@fcd03000 {
+			compatible = "hisilicon,hi4511-dw-mshc";
+			reg = <0xfcd03000 0x1000>;
+			interrupts = <0 16 4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&sdclk>, <&ddrcperclk>;
+			clock-names = "ciu", "biu";
+		};
+
+		dwmmc_2: dwmmc2@fcd05000 {
+			compatible = "hisilicon,hi4511-dw-mshc";
+			reg = <0xfcd05000 0x1000>;
+			interrupts = <0 18 4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&mmcclk2>;
+		};
+
+		dwmmc_3: dwmmc3@fcd06000 {
+			compatible = "hisilicon,hi4511-dw-mshc";
+			reg = <0xfcd06000 0x1000>;
+			interrupts = <0 19 4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&mmcclk3>;
+		};
+
+		dma0: dma@fcd02000 {
+			compatible = "hisilicon,k3-dma-1.0";
+			reg = <0xfcd02000 0x1000>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+			dma-requests = <27>;
+			interrupts = <0 12 4>;
+			clocks = <&dmaclk>;
+			status = "disable";
+		};
+
+		edc0: edc@fa202000 {
+			compatible = "hisilicon,hi3620-fb";
+			reg = <0xfa202000 0x1000>;
+			clocks = <&ldiclk0 &edcclk0 &dsiclk0 &lanebyteclk0>;
+			clock-names = "ldi", "edc", "dsi", "lane";
+			interrupts = <0 38 0x4>, <0 39 0x4>, <0 40 0x4>;
+			interrupt-names = "edc", "ldi", "dsi";
+			status = "disabled";
+
+			dsi2xclk0: clkdsi@0 {
+				compatible = "hisilicon,hi3620-phy";
+				#clock-cells = <0>;
+				clocks = <&osc26m>;
+				clock-output-names = "clk_dsi2x0";
+			};
+			dsiclk0: clkdsi@1 {
+				compatible = "hisilicon,clk-fixed-factor";
+				#clock-cells = <0>;
+				clocks = <&dsi2xclk0>;
+				clock-output-names = "clk_dsi0";
+				/*mult, div*/
+				hisilicon,fixed-factor = <1 2>;
+			};
+			lanebyteclk0: clkdsi@2 {
+				compatible = "hisilicon,clk-fixed-factor";
+				#clock-cells = <0>;
+				clocks = <&dsi2xclk0>;
+				clock-output-names = "clk_lanebyte0";
+				/*mult, div*/
+				hisilicon,fixed-factor = <1 8>;
+			};
+			escclk0: clkdsi@3 {
+				compatible = "hisilicon,hi3620-phy-esc";
+				#clock-cells = <0>;
+				clocks = <&lanebyteclk0>;
+				clock-output-names = "clk_dsi_phy_esc0";
+			};
+		};
+		edc1: edc@fa206900 {
+			compatible = "hisilicon,hi3620-fb";
+			clocks = <&ldiclk1 &edcclk1>;
+			clock-names = "ldi", "edc";
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/hi4511.dts b/arch/arm/boot/dts/hi4511.dts
index bdf2c12280a3..5eaaaf81c2db 100644
--- a/arch/arm/boot/dts/hi4511.dts
+++ b/arch/arm/boot/dts/hi4511.dts
@@ -828,6 +828,34 @@
 			pmu-power-hold-gpios = <&gpio19 6 0>;
 		};
 
+		edc0: edc@fa202000 {
+			hisilicon,pixel-format = "RGB565";
+			hisilicon,color-mode = <5>;
+			hisilicon,dsi-clock-frequency = <270000000>;    /* 241MHz, not 300MHz */
+			hisilicon,mipi-mode = "video";
+			hisilicon,mipi-lanes = <4>;
+			status = "ok";
+
+			display-timings {
+				native-mode = <&timing0>;
+				timing0: timing0 {
+					clock-frequency = <68000000>;      /* 13.158MHz pixel clock */
+					hactive = <720>;
+					vactive = <1280>;
+					hsync-active = <0>;
+					vsync-active = <0>;
+					de-active = <1>;
+					pixelclk-active = <1>;
+					hfront-porch = <96>;
+					hback-porch = <16>;
+					hsync-len = <16>;
+					vfront-porch = <12>;
+					vback-porch = <12>;
+					vsync-len = <16>;
+				};
+			};
+		};
+
 		pmic: pmic@fcc00000 {
 			compatible = "hisilicon,hi6421-pmic";
 			reg = <0xfcc00000 0x0180>; /* 0x60 << 2 */
@@ -1339,4 +1367,29 @@
 			};
 		}; /* end of pmic */
 	};
+
+	r63306_osc_clk: clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <14000000>;
+		clock-output-names = "14mhz";
+	};
+
+	panel {
+		compatible = "renesas,r63306";
+
+		renesas_pwm: pwm {
+			compatible = "renesas,r63306-pwm";
+			#pwm-cells = <2>;
+			clocks = <&r63306_osc_clk>;
+		};
+	};
+	backlight2 {
+		compatible = "pwm-backlight";
+		/* reference is 14MHz, set output clock to 1MHz */
+		pwms = <&renesas_pwm 0 1000>;
+		pwm-names = "backlight2";
+		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+		default-brightness-level = <16>;
+	};
 };