diff options
Diffstat (limited to 'product/sgm775/include')
21 files changed, 1316 insertions, 0 deletions
diff --git a/product/sgm775/include/fmw_cmsis.h b/product/sgm775/include/fmw_cmsis.h new file mode 100644 index 00000000..8cf22ddd --- /dev/null +++ b/product/sgm775/include/fmw_cmsis.h @@ -0,0 +1,30 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FMW_CMSIS_H +#define FMW_CMSIS_H + +#define __CHECK_DEVICE_DEFINES +#define __CM3_REV 0x0201 +#define __MPU_PRESENT 1 +#define __NVIC_PRIO_BITS 3 +#define __Vendor_SysTickConfig 0 + +typedef enum IRQn { + NonMaskableInt_IRQn = -14, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, +} IRQn_Type; + +#include <core_cm3.h> + +#endif /* FMW_CMSIS_H */ diff --git a/product/sgm775/include/sgm775_core.h b/product/sgm775/include/sgm775_core.h new file mode 100644 index 00000000..afa59509 --- /dev/null +++ b/product/sgm775/include/sgm775_core.h @@ -0,0 +1,15 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_CORE_H +#define SGM775_CORE_H + +#define SGM775_CORE_PER_CLUSTER_MAX 8 + +unsigned int sgm775_core_get_count(void); + +#endif /* SGM775_CORE_H */ diff --git a/product/sgm775/include/sgm775_irq.h b/product/sgm775/include/sgm775_irq.h new file mode 100644 index 00000000..fbbe92e7 --- /dev/null +++ b/product/sgm775/include/sgm775_irq.h @@ -0,0 +1,178 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_IRQ_H +#define SGM775_IRQ_H + +#include <fwk_interrupt.h> + +#define WDOG_IRQ FWK_INTERRUPT_NMI /* SCP Watchdog (SP805) */ + +enum sgm775_irq { + TIM32KHZ_IRQ = 0, /* 32KHz Physical Timer */ + CDBG_PWR_UP_REQ_IRQ = 1, /* Coresight Debug Power Request */ + CSYS_PWR_UP_REQ_IRQ = 2, /* Coresight System Power Request */ + CDBG_RST_REQ_IRQ = 3, /* Coresight Debug Reset Request */ + GIC_EXT_WAKEUP_IRQ = 4, /* External GIC Wakeup Request */ + RESERVED5_IRQ = 5, /* Reserved */ + RESERVED6_IRQ = 6, /* Reserved */ + RESERVED7_IRQ = 7, /* Reserved */ + RESERVED8_IRQ = 8, /* Reserved */ + RESERVED9_IRQ = 9, /* Reserved */ + RESERVED10_IRQ = 10, /* Reserved */ + RESERVED11_IRQ = 11, /* Reserved */ + RESERVED12_IRQ = 12, /* Reserved */ + RESERVED13_IRQ = 13, /* Reserved */ + RESERVED14_IRQ = 14, /* Reserved */ + RESERVED15_IRQ = 15, /* Reserved */ + SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */ + SOC_WAKEUP1_IRQ = 17, /* SoC Expansion Wakeup */ + SOC_WAKEUP2_IRQ = 18, /* SoC Expansion Wakeup */ + SOC_WAKEUP3_IRQ = 19, /* SoC Expansion Wakeup */ + SOC_WAKEUP4_IRQ = 20, /* SoC Expansion Wakeup */ + SOC_WAKEUP5_IRQ = 21, /* SoC Expansion Wakeup */ + SOC_WAKEUP6_IRQ = 22, /* SoC Expansion Wakeup */ + SOC_WAKEUP7_IRQ = 23, /* SoC Expansion Wakeup */ + SOC_WAKEUP8_IRQ = 24, /* SoC Expansion Wakeup */ + SOC_WAKEUP9_IRQ = 25, /* SoC Expansion Wakeup */ + SOC_WAKEUP10_IRQ = 26, /* SoC Expansion Wakeup */ + SOC_WAKEUP11_IRQ = 27, /* SoC Expansion Wakeup */ + SOC_WAKEUP12_IRQ = 28, /* SoC Expansion Wakeup */ + SOC_WAKEUP13_IRQ = 29, /* SoC Expansion Wakeup */ + SOC_WAKEUP14_IRQ = 30, /* SoC Expansion Wakeup */ + SOC_WAKEUP15_IRQ = 31, /* SoC Expansion Wakeup */ + PPU_SCP_IRQ = 32, /* SCP Power Policy Unit */ + TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ + MHU_HIGH_PRIO_IRQ = 34, /* MHU High Priority */ + MHU_LOW_PRIO_IRQ = 35, /* MHU Low Priority */ + MHU_SECURE_IRQ = 36, /* MHU Secure */ + CTI_TRIGGER0_IRQ = 37, /* SCP CTI Trigger */ + CTI_TRIGGER1_IRQ = 38, /* SCP CTI Trigger */ + GIC_ERROR_ECC_IRQ = 39, /* GIC Error (ECC Fatal) */ + GIC_ERROR_AXIM_IRQ = 40, /* GIC Error (AXIM) */ + DMC_RESERVED0_IRQ = 41, /* DMC, Reserved */ + DMC_0_ERROR_ECC_IRQ = 42, /* DMC0 Combined ECC Error */ + DMC_0_ERROR_ACCESS_IRQ = 43, /* DMC0 Combined Misc Access Error */ + DMC_RESERVED1_IRQ = 44, /* DMC, Reserved */ + DMC_RESERVED2_IRQ = 45, /* DMC, Reserved */ + DMC_1_ERROR_ECC_IRQ = 46, /* DMC1 Combined ECC Error */ + DMC_1_ERROR_ACCESS_IRQ = 47, /* DMC1 Combined Misc Access Error */ + DMC_RESERVED3_IRQ = 48, /* DMC, Reserved */ + DMC_RESERVED4_IRQ = 49, /* DMC, Reserved */ + DMC_2_ERROR_ECC_IRQ = 50, /* DMC2 Combined ECC Error */ + DMC_2_ERROR_ACCESS_IRQ = 51, /* DMC2 Combined Misc Access Error */ + DMC_RESERVED5_IRQ = 52, /* DMC, Reserved */ + DMC_RESERVED6_IRQ = 53, /* DMC, Reserved */ + DMC_3_ERROR_ECC_IRQ = 54, /* DMC3 Combined ECC Error */ + DMC_3_ERROR_ACCESS_IRQ = 55, /* DMC3 Combined Misc Access Error */ + DMC_RESERVED7_IRQ = 56, /* DMC, Reserved */ + RESERVED57_IRQ = 57, /* Reserved */ + RESERVED58_IRQ = 58, /* Reserved */ + RESERVED59_IRQ = 59, /* Reserved */ + RESERVED60_IRQ = 60, /* Reserved */ + RESERVED61_IRQ = 61, /* Reserved */ + RESERVED62_IRQ = 62, /* Reserved */ + RESERVED63_IRQ = 63, /* Reserved */ + PPU_CLUS0CORE0_IRQ = 64, /* Cluster 0 Core 0 Power Policy Unit */ + PPU_CLUS0CORE1_IRQ = 65, /* Cluster 0 Core 1 Power Policy Unit */ + PPU_CLUS0CORE2_IRQ = 66, /* Cluster 0 Core 2 Power Policy Unit */ + PPU_CLUS0CORE3_IRQ = 67, /* Cluster 0 Core 3 Power Policy Unit */ + PPU_CLUS0_IRQ = 68, /* Cluster 0 Power Policy Unit */ + PPU_CLUS1CORE0_IRQ = 69, /* Cluster 1 Core 0 Power Policy Unit */ + PPU_CLUS1CORE1_IRQ = 70, /* Cluster 1 Core 1 Power Policy Unit */ + PPU_CLUS1CORE2_IRQ = 71, /* Cluster 1 Core 2 Power Policy Unit */ + PPU_CLUS1CORE3_IRQ = 72, /* Cluster 1 Core 3 Power Policy Unit */ + PPU_CLUS1_IRQ = 73, /* Cluster 1 Power Policy Unit */ + PPU_SYS0_IRQ = 74, /* System Power Policy Unit 0 */ + PPU_SYS1_IRQ = 75, /* System Power Policy Unit 1 */ + PPU_GPU_IRQ = 76, /* GPU Power Policy Unit */ + PPU_VPU_IRQ = 77, /* Video Power Policy Unit */ + RESERVED78_IRQ = 78, /* Reserved */ + PPU_DPU0_IRQ = 79, /* Display Power Policy Unit 0 */ + PPU_DPU1_IRQ = 80, /* Display Power Policy Unit 1 */ + PPU_DEBUG_IRQ = 81, /* DBGSYS Power Policy Unit */ + RESERVED82_IRQ = 82, /* Reserved */ + RESERVED83_IRQ = 83, /* Reserved */ + RESERVED84_IRQ = 84, /* Reserved */ + RESERVED85_IRQ = 85, /* Reserved */ + RESERVED86_IRQ = 86, /* Reserved */ + RESERVED87_IRQ = 87, /* Reserved */ + RESERVED88_IRQ = 88, /* Reserved */ + RESERVED89_IRQ = 89, /* Reserved */ + PPU_CLUS0CORE4_IRQ = 90, /* Cluster 0 Core 4 Power Policy Unit */ + PPU_CLUS0CORE5_IRQ = 91, /* Cluster 0 Core 5 Power Policy Unit */ + PPU_CLUS0CORE6_IRQ = 92, /* Cluster 0 Core 6 Power Policy Unit */ + PPU_CLUS0CORE7_IRQ = 93, /* Cluster 0 Core 7 Power Policy Unit */ + PPU_CLUS1CORE4_IRQ = 94, /* Cluster 1 Core 4 Power Policy Unit */ + PPU_CLUS1CORE5_IRQ = 95, /* Cluster 1 Core 5 Power Policy Unit */ + PPU_CLUS1CORE6_IRQ = 96, /* Cluster 1 Core 6 Power Policy Unit */ + PPU_CLUS1CORE7_IRQ = 97, /* Cluster 1 Core 7 Power Policy Unit */ + PLL_CLUS0_LOCK_IRQ = 98, /* Cluster 0 CPU PLL Lock */ + PLL_CLUS1_LOCK_IRQ = 99, /* Cluster 1 CPU PLL Lock */ + PLL_GPU_LOCK_IRQ = 100, /* GPU PLL Lock */ + PLL_VPU_LOCK_IRQ = 101, /* Video PLL Lock */ + PLL_SYS_LOCK_IRQ = 102, /* System PLL Lock */ + PLL_DPU_LOCK_IRQ = 103, /* Display PLL Lock */ + PLL_CLUS0CORE0_IRQ = 104, /* Cluster 0 PLL0 Lock */ + PLL_CLUS0CORE1_IRQ = 105, /* Cluster 0 PLL1 Lock */ + PLL_CLUS0CORE2_IRQ = 106, /* Cluster 0 PLL2 Lock */ + PLL_CLUS0CORE3_IRQ = 107, /* Cluster 0 PLL3 Lock */ + PLL_CLUS0CORE4_IRQ = 108, /* Cluster 0 PLL4 Lock */ + PLL_CLUS0CORE5_IRQ = 109, /* Cluster 0 PLL5 Lock */ + PLL_CLUS0CORE6_IRQ = 110, /* Cluster 0 PLL6 Lock */ + PLL_CLUS0CORE7_IRQ = 111, /* Cluster 0 PLL7 Lock */ + PLL_CLUS1CORE0_IRQ = 112, /* Cluster 1 PLL0 Lock */ + PLL_CLUS1CORE1_IRQ = 113, /* Cluster 1 PLL1 Lock */ + PLL_CLUS1CORE2_IRQ = 114, /* Cluster 1 PLL2 Lock */ + PLL_CLUS1CORE3_IRQ = 115, /* Cluster 1 PLL3 Lock */ + PLL_CLUS1CORE4_IRQ = 116, /* Cluster 1 PLL4 Lock */ + PLL_CLUS1CORE5_IRQ = 117, /* Cluster 1 PLL5 Lock */ + PLL_CLUS1CORE6_IRQ = 118, /* Cluster 1 PLL6 Lock */ + PLL_CLUS1CORE7_IRQ = 119, /* Cluster 1 PLL7 Lock */ + RESERVED120_IRQ = 120, /* Reserved */ + RESERVED121_IRQ = 121, /* Reserved */ + RESERVED122_IRQ = 122, /* Reserved */ + RESERVED123_IRQ = 123, /* Reserved */ + RESERVED124_IRQ = 124, /* Reserved */ + RESERVED125_IRQ = 125, /* Reserved */ + RESERVED126_IRQ = 126, /* Reserved */ + RESERVED127_IRQ = 127, /* Reserved */ + SCP_EXT_INTR0_IRQ = 128, /* SCP Customer Extension */ + SCP_EXT_INTR1_IRQ = 129, /* SCP Customer Extension */ + SCP_EXT_INTR2_IRQ = 130, /* SCP Customer Extension */ + SCP_EXT_INTR3_IRQ = 131, /* SCP Customer Extension */ + SCP_EXT_INTR4_IRQ = 132, /* SCP Customer Extension */ + SCP_EXT_INTR5_IRQ = 133, /* SCP Customer Extension */ + SCP_EXT_INTR6_IRQ = 134, /* SCP Customer Extension */ + SCP_EXT_INTR7_IRQ = 135, /* SCP Customer Extension */ + SCP_EXT_INTR8_IRQ = 136, /* SCP Customer Extension */ + SCP_EXT_INTR9_IRQ = 137, /* SCP Customer Extension */ + SCP_EXT_INTR10_IRQ = 138, /* SCP Customer Extension */ + SCP_EXT_INTR11_IRQ = 139, /* SCP Customer Extension */ + SCP_EXT_INTR12_IRQ = 140, /* SCP Customer Extension */ + SCP_EXT_INTR13_IRQ = 141, /* SCP Customer Extension */ + SCP_EXT_INTR14_IRQ = 142, /* SCP Customer Extension */ + SCP_EXT_INTR15_IRQ = 143, /* SCP Customer Extension */ + SCP_EXT_INTR16_IRQ = 144, /* SCP Customer Extension */ + SCP_EXT_INTR17_IRQ = 145, /* SCP Customer Extension */ + SCP_EXT_INTR18_IRQ = 146, /* SCP Customer Extension */ + SCP_EXT_INTR19_IRQ = 147, /* SCP Customer Extension */ + SCP_EXT_INTR20_IRQ = 148, /* SCP Customer Extension */ + SCP_EXT_INTR21_IRQ = 149, /* SCP Customer Extension */ + SCP_EXT_INTR22_IRQ = 150, /* SCP Customer Extension */ + SCP_EXT_INTR23_IRQ = 151, /* SCP Customer Extension */ + SCP_EXT_INTR24_IRQ = 152, /* SCP Customer Extension */ + SCP_EXT_INTR25_IRQ = 153, /* SCP Customer Extension */ + SCP_EXT_INTR26_IRQ = 154, /* SCP Customer Extension */ + SCP_EXT_INTR27_IRQ = 155, /* SCP Customer Extension */ + SCP_EXT_INTR28_IRQ = 156, /* SCP Customer Extension */ + SCP_EXT_INTR29_IRQ = 157, /* SCP Customer Extension */ + SCP_EXT_INTR30_IRQ = 158, /* SCP Customer Extension */ + SCP_EXT_INTR31_IRQ = 159, /* SCP Customer Extension */ +}; + +#endif /* SGM775_IRQ_H */ diff --git a/product/sgm775/include/sgm775_mhu.h b/product/sgm775/include/sgm775_mhu.h new file mode 100644 index 00000000..8cdc4dd0 --- /dev/null +++ b/product/sgm775/include/sgm775_mhu.h @@ -0,0 +1,21 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * MHU module device indexes. + */ + +#ifndef SGM775_MHU_H +#define SGM775_MHU_H + +enum sgm775_mhu_device_idx { + SGM775_MHU_DEVICE_IDX_S, + SGM775_MHU_DEVICE_IDX_NS_H, + SGM775_MHU_DEVICE_IDX_NS_L, + SGM775_MHU_DEVICE_IDX_COUNT +}; + +#endif /* SGM775_MHU_H */ diff --git a/product/sgm775/include/sgm775_mmap.h b/product/sgm775/include/sgm775_mmap.h new file mode 100644 index 00000000..16626760 --- /dev/null +++ b/product/sgm775/include/sgm775_mmap.h @@ -0,0 +1,101 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_MMAP_H +#define SGM775_MMAP_H + +#include <stdint.h> + +/* + * Top-level base addresses + */ +#define EXPANSION0_BASE UINT32_C(0x40000000) +#define PERIPHERAL_BASE UINT32_C(0x44000000) +#define POWER_PERIPHERAL_BASE UINT32_C(0x50000000) +#define SYS0_BASE UINT32_C(0x60000000) +#define SYS1_BASE UINT32_C(0xA0000000) +#define PPB_INTERNAL_BASE UINT32_C(0xE0000000) +#define PPB_EXTERNAL_BASE UINT32_C(0xE0040000) +#define EXPANSION1_BASE UINT32_C(0xE0100000) + +/* + * Peripherals + */ +#define REFCLK_CNTCTL_BASE (PERIPHERAL_BASE + 0x0000) +#define REFCLK_CNTBASE0_BASE (PERIPHERAL_BASE + 0x1000) +#define WDOG_BASE (PERIPHERAL_BASE + 0x6000) +#define S32K_CNTCONTROL_BASE (PERIPHERAL_BASE + 0x7000) +#define S32K_CNTCTL_BASE (PERIPHERAL_BASE + 0x8000) +#define S32K_CNTBASE0_BASE (PERIPHERAL_BASE + 0x9000) +#define CS_CNTCONTROL_BASE (PERIPHERAL_BASE + 0xA000) + +/* + * Power control peripherals + */ +#define PIK_SCP_BASE (POWER_PERIPHERAL_BASE + 0x00000) +#define PIK_DEBUG_BASE (POWER_PERIPHERAL_BASE + 0x20000) +#define SENSOR_DEBUG_BASE (POWER_PERIPHERAL_BASE + 0x30000) +#define PIK_SYSTEM_BASE (POWER_PERIPHERAL_BASE + 0x40000) +#define SENSOR_SYSTEM_BASE (POWER_PERIPHERAL_BASE + 0x50000) +#define PIK_CLUS0_BASE (POWER_PERIPHERAL_BASE + 0x60000) +#define SENSOR_CLUS0_BASE (POWER_PERIPHERAL_BASE + 0x70000) +#define PIK_CLUS1_BASE (POWER_PERIPHERAL_BASE + 0x80000) +#define SENSOR_CLUS1_BASE (POWER_PERIPHERAL_BASE + 0x90000) +#define PIK_GPU_BASE (POWER_PERIPHERAL_BASE + 0xA0000) +#define SENSOR_GPU_BASE (POWER_PERIPHERAL_BASE + 0xB0000) +#define PIK_VPU_BASE (POWER_PERIPHERAL_BASE + 0xC0000) +#define SENSOR_VPU_BASE (POWER_PERIPHERAL_BASE + 0xD0000) +#define PIK_DPU_BASE (POWER_PERIPHERAL_BASE + 0xE0000) +#define SENSOR_DPU_BASE (POWER_PERIPHERAL_BASE + 0xF0000) + +/* + * PPU base address + */ +#define PPU_SCP_BASE (PIK_SCP_BASE + 0x1000) +#define PPU_SYS0_BASE (PIK_SYSTEM_BASE + 0x1000) +#define PPU_SYS1_BASE (PIK_SYSTEM_BASE + 0x2000) +#define PPU_DEBUG_BASE (PIK_DEBUG_BASE + 0x1000) +#define PPU_CLUS0CORE0_BASE (PIK_CLUS0_BASE + 0x2000) +#define PPU_CLUS0CORE1_BASE (PIK_CLUS0_BASE + 0x3000) +#define PPU_CLUS0CORE2_BASE (PIK_CLUS0_BASE + 0x4000) +#define PPU_CLUS0CORE3_BASE (PIK_CLUS0_BASE + 0x5000) +#define PPU_CLUS0CORE4_BASE (PIK_CLUS0_BASE + 0x6000) +#define PPU_CLUS0CORE5_BASE (PIK_CLUS0_BASE + 0x7000) +#define PPU_CLUS0CORE6_BASE (PIK_CLUS0_BASE + 0x8000) +#define PPU_CLUS0CORE7_BASE (PIK_CLUS0_BASE + 0x9000) +#define PPU_CLUS0_BASE (PIK_CLUS0_BASE + 0x1000) +#define PPU_CLUS1CORE0_BASE (PIK_CLUS1_BASE + 0x2000) +#define PPU_CLUS1CORE1_BASE (PIK_CLUS1_BASE + 0x3000) +#define PPU_CLUS1CORE2_BASE (PIK_CLUS1_BASE + 0x4000) +#define PPU_CLUS1CORE3_BASE (PIK_CLUS1_BASE + 0x5000) +#define PPU_CLUS1_BASE (PIK_CLUS1_BASE + 0x1000) +#define PPU_GPU_BASE (PIK_GPU_BASE + 0x1000) +#define PPU_VPU_BASE (PIK_VPU_BASE + 0x1000) +#define PPU_DPU0_BASE (PIK_DPU_BASE + 0x2000) +#define PPU_DPU1_BASE (PIK_DPU_BASE + 0x3000) + +/* + * System access port 1 + */ +#define TRUSTED_RAM_BASE (SYS1_BASE + 0x04000000) +#define NONTRUSTED_RAM_BASE (SYS1_BASE + 0x06000000) +#define SSC_BASE (SYS1_BASE + 0x2A420000) +#define REFCLK_CNTCONTROL_BASE (SYS1_BASE + 0x2A430000) +#define MHU_BASE (SYS1_BASE + 0x2B1F0000) + +/* + * Base addresses of MHU devices + */ + +#define MHU_SCP_INTR_L_BASE (MHU_BASE) +#define MHU_SCP_INTR_H_BASE (MHU_BASE + 0x0020) +#define MHU_CPU_INTR_L_BASE (MHU_BASE + 0x0100) +#define MHU_CPU_INTR_H_BASE (MHU_BASE + 0x0120) +#define MHU_SCP_INTR_S_BASE (MHU_BASE + 0x0200) +#define MHU_CPU_INTR_S_BASE (MHU_BASE + 0x0300) + +#endif /* SGM775_MMAP_H */ diff --git a/product/sgm775/include/sgm775_mmap_scp.h b/product/sgm775/include/sgm775_mmap_scp.h new file mode 100644 index 00000000..a4ceb5b9 --- /dev/null +++ b/product/sgm775/include/sgm775_mmap_scp.h @@ -0,0 +1,19 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP ROM and RAM memory bases. These definitions are kept isolated without + * the UINT32_C() or UL decorators allowing them to be used in the linker + * script. + */ + +#ifndef SGM775_MMAP_SCP_H +#define SGM775_MMAP_SCP_H + +#define SCP_ROM_BASE 0x00000000 +#define SCP_RAM_BASE 0x10000000 + +#endif /* SGM775_MMAP_SCP_H */ diff --git a/product/sgm775/include/sgm775_pik.h b/product/sgm775/include/sgm775_pik.h new file mode 100644 index 00000000..7d0ac12b --- /dev/null +++ b/product/sgm775/include/sgm775_pik.h @@ -0,0 +1,29 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_PIK_H +#define SGM775_PIK_H + +#include <sgm775_mmap.h> +#include <sgm775_pik_cpu.h> +#include <sgm775_pik_debug.h> +#include <sgm775_pik_dpu.h> +#include <sgm775_pik_gpu.h> +#include <sgm775_pik_scp.h> +#include <sgm775_pik_system.h> +#include <sgm775_pik_vpu.h> + +#define PIK_CLUS0 ((struct pik_cpu_reg_v8_2 *) PIK_CLUS0_BASE) +#define PIK_CLUS1 ((struct pik_cpu_reg_v8_2 *) PIK_CLUS1_BASE) +#define PIK_DEBUG ((struct pik_debug_reg *) PIK_DEBUG_BASE) +#define PIK_DPU ((struct pik_dpu_reg *) PIK_DPU_BASE) +#define PIK_GPU ((struct pik_gpu_reg *) PIK_GPU_BASE) +#define PIK_SCP ((struct pik_scp_reg *) PIK_SCP_BASE) +#define PIK_SYSTEM ((struct pik_system_reg *) PIK_SYSTEM_BASE) +#define PIK_VPU ((struct pik_vpu_reg *) PIK_VPU_BASE) + +#endif /* SGM775_PIK_H */ diff --git a/product/sgm775/include/sgm775_pik_cpu.h b/product/sgm775/include/sgm775_pik_cpu.h new file mode 100644 index 00000000..5c7cc646 --- /dev/null +++ b/product/sgm775/include/sgm775_pik_cpu.h @@ -0,0 +1,145 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_PIK_CPU_H +#define SGM775_PIK_CPU_H + +#include <stdint.h> +#include <fwk_macros.h> + +#define PE_COUNT_MAX 16 + +/*! + * \brief CPU PIK V8 register definitions + */ +struct pik_cpu_reg_v8 { + FWK_RW uint32_t STATIC_CONFIG; + uint8_t RESERVED0[0x10 - 0x4]; + FWK_RW uint32_t RVBARADDR0_LW; + FWK_RW uint32_t RVBARADDR0_UP; + FWK_RW uint32_t RVBARADDR1_LW; + FWK_RW uint32_t RVBARADDR1_UP; + FWK_RW uint32_t RVBARADDR2_LW; + FWK_RW uint32_t RVBARADDR2_UP; + FWK_RW uint32_t RVBARADDR3_LW; + FWK_RW uint32_t RVBARADDR3_UP; + FWK_RW uint32_t CLUSTER_CONFIG; + uint8_t RESERVED1[0x200 - 0x34]; + FWK_R uint32_t DBG_RST_STATU; + FWK_RW uint32_t DBG_RST_SET; + FWK_RW uint32_t DBG_RST_CLR; + uint8_t RESERVED2[0x400 - 0x20C]; + FWK_RW uint32_t CPUACTIVE_CTRL; + uint8_t RESERVED3[0x800 - 0x404]; + FWK_RW uint32_t PPUCLK_CTRL; + FWK_RW uint32_t PPUCLK_DIV1; + FWK_RW uint32_t PPUCLK_DIV2; + FWK_R uint32_t RESERVED4; + FWK_RW uint32_t CPUCLK_CTRL; + FWK_RW uint32_t CPUCLK_DIV1; + FWK_RW uint32_t CPUCLK_DIV2; + FWK_R uint32_t RESERVED5; + FWK_RW uint32_t PCLKDBG_CTRL; + uint8_t RESERVED6[0x830 - 0x824]; + FWK_RW uint32_t ATCLKDBG_CTRL; + uint8_t RESERVED7[0x840 - 0x834]; + FWK_RW uint32_t ACLKCPU_CTRL; + uint8_t RESERVED8[0xA00 - 0x844]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_RW uint32_t CLKFORCE_SET; + FWK_RW uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xFC0 - 0xA0C]; + FWK_R uint32_t PIK_CONFIG; + uint8_t RESERVED10[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +/*! + * \brief PE Static Configuration register definitions + */ +struct static_config { + FWK_RW uint32_t STATIC_CONFIG; + FWK_RW uint32_t RVBARADDR_LW; + FWK_RW uint32_t RVBARADDR_UP; + uint32_t RESERVED; +}; + +/*! + * \brief AP cores clock control register definitions + */ +struct ap_clk_ctrl { + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV; + uint32_t RESERVED; + FWK_RW uint32_t CORECLK_MOD; +}; + +/*! + * \brief CPU PIK V8.2 register definitions + */ +struct pik_cpu_reg_v8_2 { + FWK_RW uint32_t CLUSTER_CONFIG; + uint8_t RESERVED0[0x10 - 0x4]; + struct static_config STATIC_CONFIG[PE_COUNT_MAX]; + uint8_t RESERVED1[0x800 - 0x110]; + FWK_RW uint32_t PPUCLK_CTRL; + FWK_RW uint32_t PPUCLK_DIV1; + uint8_t RESERVED2[0x810 - 0x808]; + FWK_RW uint32_t PCLK_CTRL; + uint8_t RESERVED3[0x820 - 0x814]; + FWK_RW uint32_t ATCLK_CTRL; + uint8_t RESERVED4[0x830 - 0x824]; + FWK_RW uint32_t GICCLK_CTRL; + uint8_t RESERVED5[0x840 - 0x834]; + FWK_RW uint32_t AMBACLK_CTRL; + uint8_t RESERVED6[0x850 - 0x844]; + FWK_RW uint32_t CLUSCLK_CTRL; + FWK_RW uint32_t CLUSCLK_DIV1; + uint8_t RESERVED7[0x860 - 0x858]; + struct ap_clk_ctrl AP_CLK_CTRL[8]; + uint8_t RESERVED8[0xA00 - 0x8E0]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_RW uint32_t CLKFORCE_SET; + FWK_RW uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xFB8 - 0xA0C]; + FWK_R uint32_t CAP2; + FWK_R uint32_t CAP; + FWK_R uint32_t PIK_CONFIG; + uint8_t RESERVED10[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#define PIK_CPU_V8_2_CAP_CLUSSYNC UINT32_C(0x00000001) +#define PIK_CPU_V8_2_CAP_CORESYNC(CORE) ((uint32_t)(1 << ((CORE) + 1))) +#define PIK_CPU_V8_2_CAP_PE_MASK UINT32_C(0xF0000000) +#define PIK_CPU_V8_2_CAP_PE_POS 28 + +#define PIK_CPU_V8_2_PIK_CONFIG_NO_OF_PPU UINT32_C(0x0000000F) + +#endif /* SGM775_PIK_CPU_H */ diff --git a/product/sgm775/include/sgm775_pik_debug.h b/product/sgm775/include/sgm775_pik_debug.h new file mode 100644 index 00000000..3a7f5fee --- /dev/null +++ b/product/sgm775/include/sgm775_pik_debug.h @@ -0,0 +1,49 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_PIK_DEBUG_H +#define SGM775_PIK_DEBUG_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief Debug register definitions + */ +struct pik_debug_reg { + FWK_RW uint32_t DEBUG_CONTROL; + FWK_R uint32_t DEBUG_STATUS; + uint32_t RESERVED0[2]; + FWK_R uint32_t APP_DAP_TARGET_ID; + FWK_R uint32_t SCP_DAP_TARGET_ID; + FWK_R uint32_t DAP_INSTANCE_ID; + uint8_t RESERVED1[0x810 - 0x1C]; + FWK_RW uint32_t TRACECLK_CTRL; + FWK_RW uint32_t TRACECLK_DIV1; + uint32_t RESERVED2[2]; + FWK_RW uint32_t PCLKDBG_CTRL; + uint32_t RESERVED3[3]; + FWK_RW uint32_t ATCLK_CTRL; + FWK_RW uint32_t ATCLK_DIV1; + FWK_R uint8_t RESERVED4[0xFC0 - 0x838]; + FWK_R uint32_t PIK_CONFIG; + uint32_t RESERVED5[3]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#endif /* SGM775_PIK_DEBUG_H */ diff --git a/product/sgm775/include/sgm775_pik_dpu.h b/product/sgm775/include/sgm775_pik_dpu.h new file mode 100644 index 00000000..e9c5292f --- /dev/null +++ b/product/sgm775/include/sgm775_pik_dpu.h @@ -0,0 +1,51 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_PIK_DPU_H +#define SGM775_PIK_DPU_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief DPU PIK register definitions + */ +struct pik_dpu_reg { + FWK_R uint8_t RESERVED0[0x810]; + FWK_RW uint32_t M0CLK_CTRL; + FWK_RW uint32_t M0CLK_DIV1; + FWK_RW uint32_t M0CLK_DIV2; + uint32_t RESERVED1; + FWK_RW uint32_t M1CLK_CTRL; + FWK_RW uint32_t M1CLK_DIV1; + FWK_RW uint32_t M1CLK_DIV2; + uint32_t RESERVED2; + FWK_RW uint32_t ACLKDP_CTRL; + FWK_RW uint32_t ACLKDP_DIV1; + FWK_RW uint32_t ACLKDP_DIV2; + uint8_t RESERVED3[0xA00 - 0x83C]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED4[0xFC0 - 0xA0C]; + FWK_RW uint32_t PWR_CTRL_CONFIG; + uint8_t RESERVED5[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#endif /* SGM775_PIK_DPU_H */ diff --git a/product/sgm775/include/sgm775_pik_gpu.h b/product/sgm775/include/sgm775_pik_gpu.h new file mode 100644 index 00000000..c92a3e94 --- /dev/null +++ b/product/sgm775/include/sgm775_pik_gpu.h @@ -0,0 +1,45 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_PIK_GPU_H +#define SGM775_PIK_GPU_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief GPU PIK register definitions + */ +struct pik_gpu_reg { + uint8_t RESERVED0[0x810]; + FWK_RW uint32_t GPUCLK_CTRL; + FWK_RW uint32_t GPUCLK_DIV1; + FWK_RW uint32_t GPUCLK_DIV2; + FWK_R uint32_t RESERVED1; + FWK_RW uint32_t ACLKGPU_CTRL; + uint8_t RESERVED2[0xA00 - 0x824]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED3[0xFC0 - 0xA0C]; + FWK_RW uint32_t PWR_CTRL_CONFIG; + uint8_t RESERVED4[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#endif /* SGM775_PIK_GPU_H */ diff --git a/product/sgm775/include/sgm775_pik_scp.h b/product/sgm775/include/sgm775_pik_scp.h new file mode 100644 index 00000000..dce3a371 --- /dev/null +++ b/product/sgm775/include/sgm775_pik_scp.h @@ -0,0 +1,63 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_PIK_SCP_H +#define SGM775_PIK_SCP_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief SCP PIK register definitions + */ +struct pik_scp_reg { + uint32_t RESERVED0[4]; + FWK_RW uint32_t RESET_SYNDROME; + FWK_RW uint32_t WIC_CTRL; + FWK_R uint32_t WIC_STATUS; + uint8_t RESERVED1[0xA00 - 0x1C]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_RW uint32_t CLKFORCE_SET; + FWK_RW uint32_t CLKFORCE_CLR; + uint32_t RESERVED2; + FWK_R uint32_t PLL_STATUS0; + FWK_R uint32_t PLL_STATUS1; + uint8_t RESERVED3[0xFC0 - 0xA18]; + FWK_R uint32_t PIK_CONFIG; + uint32_t RESERVED4[3]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#define PLL_STATUS0_REFCLK UINT32_C(0x00000001) +#define PLL_STATUS0_BCPUPLLLOCK UINT32_C(0x00000002) +#define PLL_STATUS0_LCPUPLLLOCK UINT32_C(0x00000004) +#define PLL_STATUS0_GPUPLLLOCK UINT32_C(0x00000008) +#define PLL_STATUS0_VIDEOPLLLOCK UINT32_C(0x00000010) +#define PLL_STATUS0_SYSPLLLOCK UINT32_C(0x00000020) +#define PLL_STATUS0_DISPLAYPLLLOCK UINT32_C(0x00000040) + +#define PLL_STATUS1_CPUPLLLOCK(CPU, PLL) \ + ((uint32_t)((1 << (PLL)) << ((CPU) * 8))) + +#define RESET_SYNDROME_PORESET UINT32_C(0x01) +#define RESET_SYNDROME_WDOGRESET_SCP UINT32_C(0x02) +#define RESET_SYNDROME_WDOGRESET_SYS UINT32_C(0x04) +#define RESET_SYNDROME_SYSRESETREQ UINT32_C(0x08) +#define RESET_SYNDROME_SCPM3LOCKUP UINT32_C(0x10) + +#endif /* SGM775_PIK_SCP_H */ diff --git a/product/sgm775/include/sgm775_pik_system.h b/product/sgm775/include/sgm775_pik_system.h new file mode 100644 index 00000000..3e3dccdb --- /dev/null +++ b/product/sgm775/include/sgm775_pik_system.h @@ -0,0 +1,69 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_PIK_SYSTEM_H +#define SGM775_PIK_SYSTEM_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief System PIK register definitions + */ +struct pik_system_reg { + uint8_t RESERVED0[0x800]; + FWK_RW uint32_t PPUCLK_CTRL; + FWK_RW uint32_t PPUCLK_DIV1; + uint32_t RESERVED1[2]; + FWK_RW uint32_t ACLKNCI_CTRL; + FWK_RW uint32_t ACLKNCI_DIV1; + uint32_t RESERVED2[2]; + FWK_RW uint32_t ACLKCCI_CTRL; + FWK_RW uint32_t ACLKCCI_DIV1; + uint32_t RESERVED3[6]; + FWK_RW uint32_t TCUCLK_CTRL; + FWK_RW uint32_t TCUCLK_DIV1; + uint32_t RESERVED4[2]; + FWK_RW uint32_t GICCLK_CTRL; + FWK_RW uint32_t GICCLK_DIV1; + uint32_t RESERVED5[2]; + FWK_RW uint32_t PCLKSCP_CTRL; + FWK_RW uint32_t PCLKSCP_DIV1; + uint32_t RESERVED6[2]; + FWK_RW uint32_t SYSPERCLK_CTRL; + FWK_RW uint32_t SYSPERCLK_DIV1; + uint32_t RESERVED7[6]; + FWK_RW uint32_t FCMCLK_CTRL; + FWK_RW uint32_t FCMCLK_DIV1; + uint8_t RESERVED8[0xA00 - 0x898]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_RW uint32_t CLKFORCE_SET; + FWK_RW uint32_t CLKFORCE_CLR; + uint8_t RESERVED9[0xFBC - 0xA0C]; + FWK_R uint32_t CAP; + FWK_R uint32_t PIK_CONFIG; + uint32_t RESERVED10[3]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#define CAP_GICCLK_GATING_SUPPORT UINT32_C(0x00000001) +#define CAP_TCUCLK_SUPPORT UINT32_C(0x00000002) +#define CAP_ELA_SUPPORT UINT32_C(0x00000004) +#define CAP_FCMCLK_SUPPORT UINT32_C(0x00000008) + +#endif /* SGM775_PIK_SYSTEM_H */ diff --git a/product/sgm775/include/sgm775_pik_vpu.h b/product/sgm775/include/sgm775_pik_vpu.h new file mode 100644 index 00000000..a2742bb9 --- /dev/null +++ b/product/sgm775/include/sgm775_pik_vpu.h @@ -0,0 +1,43 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_PIK_VPU_H +#define SGM775_PIK_VPU_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief VPU PIK register definitions + */ +struct pik_vpu_reg { + uint8_t RESERVED0[0x810]; + FWK_RW uint32_t VIDEOCLK_CTRL; + FWK_RW uint32_t VIDEOCLK_DIV1; + FWK_RW uint32_t VIDEOCLK_DIV2; + uint8_t RESERVED1[0xA00 - 0x81C]; + FWK_R uint32_t CLKFORCE_STATUS; + FWK_W uint32_t CLKFORCE_SET; + FWK_W uint32_t CLKFORCE_CLR; + uint8_t RESERVED2[0xFC0 - 0xA0C]; + FWK_RW uint32_t PWR_CTRL_CONFIG; + uint8_t RESERVED3[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#endif /* SGM775_PIK_VPU_H */ diff --git a/product/sgm775/include/sgm775_scmi.h b/product/sgm775/include/sgm775_scmi.h new file mode 100644 index 00000000..a920c09f --- /dev/null +++ b/product/sgm775/include/sgm775_scmi.h @@ -0,0 +1,29 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Definitions for SCMI and SMT module configurations. + */ + +#ifndef SGM775_SCMI_H +#define SGM775_SCMI_H + +/* SCMI agent identifiers */ +enum sgm775_scmi_agent_id { + /* 0 is reserved for the platform */ + SCMI_AGENT_ID_OSPM = 1, + SCMI_AGENT_ID_PSCI, + SCMI_AGENT_ID_COUNT, +}; + +/* SCMI service indexes */ +enum sgm775_scmi_service_idx { + SGM775_SCMI_SERVICE_IDX_PSCI, + SGM775_SCMI_SERVICE_IDX_OSPM_0, + SGM775_SCMI_SERVICE_IDX_OSPM_1, + SGM775_SCMI_SERVICE_IDX_COUNT, +}; +#endif /* SGM775_SCMI_H */ diff --git a/product/sgm775/include/sgm775_sds.h b/product/sgm775/include/sgm775_sds.h new file mode 100644 index 00000000..943cfa7f --- /dev/null +++ b/product/sgm775/include/sgm775_sds.h @@ -0,0 +1,149 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_SDS_H +#define SGM775_SDS_H + +#include <mod_sds.h> + +/* + * Structure identifiers. + */ +enum sgm775_sds_struct_id { + SGM775_SDS_CPU_INFO = 1 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + SGM775_SDS_ROM_VERSION = 2 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + SGM775_SDS_RAM_VERSION = 3 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + SGM775_SDS_PLATFORM_ID = 4 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + SGM775_SDS_RESET_SYNDROME = 5 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + SGM775_SDS_FEATURE_AVAILABILITY = 6 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + SGM775_SDS_CPU_BOOTCTR = 7 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + SGM775_SDS_CPU_FLAGS = 8 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), + SGM775_SDS_BOOTLOADER = 9 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), +}; + +/* + * Structure sizes. + */ +#define SGM775_SDS_CPU_INFO_SIZE 4 +#define SGM775_SDS_ROM_VERSION_SIZE 4 +#define SGM775_SDS_RAM_VERSION_SIZE 4 +#define SGM775_SDS_PLATFORM_ID_SIZE 8 +#define SGM775_SDS_RESET_SYNDROME_SIZE 4 +#define SGM775_SDS_FEATURE_AVAILABILITY_SIZE 4 +#define SGM775_SDS_CPU_BOOTCTR_SIZE 8 +#define SGM775_SDS_CPU_FLAGS_SIZE 8 +#define SGM775_SDS_BOOTLOADER_SIZE 12 + +/* + * Field masks and offsets for the SGM775_SDS_AP_CPU_INFO structure. + */ +#define SGM775_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF +#define SGM775_SDS_CPU_INFO_PRIMARY_POS 0 + +/* + * Structure, field masks and offsets for the SGM775_SDS_PLATFORM_ID structure. + */ + +struct sgm775_sds_platid { + uint32_t platform_identifier; + uint32_t platform_type_identifier; +}; + +#define SGM775_SDS_PLATID_PARTNO_MASK 0xFFF +#define SGM775_SDS_PLATID_DESIGNER_MASK 0xFF000 +#define SGM775_SDS_PLATID_REV_MINOR_MASK 0xF00000 +#define SGM775_SDS_PLATID_REV_MAJOR_MASK 0xF000000 +#define SGM775_SDS_PLATID_CONFIG_MASK 0xF0000000 +#define SGM775_SDS_PLATID_TYPE_MASK 0xF + +#define SGM775_SDS_PLATID_PARTNO_POS 0 +#define SGM775_SDS_PLATID_DESIGNER_POS 12 +#define SGM775_SDS_PLATID_REV_MINOR_POS 20 +#define SGM775_SDS_PLATID_REV_MAJOR_POS 24 +#define SGM775_SDS_PLATID_CONFIG_POS 28 + +#define SGM775_SDS_PLATID_TYPE_POS 0 +/* + * Field masks and offsets for the SGM775_SDS_RESET_SYNDROME structure. + */ +#define SGM775_SDS_RESET_SYNDROME_POR_MASK 0x1 +#define SGM775_SDS_RESET_SYNDROME_WDOGSCP_MASK 0x2 +#define SGM775_SDS_RESET_SYNDROME_WDOGAP_MASK 0x4 +#define SGM775_SDS_RESET_SYNDROME_SYSRESET_MASK 0x8 +#define SGM775_SDS_RESET_SYNDROME_M3LOCKUP_MASK 0x10 + +#define SGM775_SDS_RESET_SYNDROME_POR_POS 0 +#define SGM775_SDS_RESET_SYNDROME_WDOGSCP_POS 1 +#define SGM775_SDS_RESET_SYNDROME_WDOGAP_POS 2 +#define SGM775_SDS_RESET_SYNDROME_SYSRESET_POS 3 +#define SGM775_SDS_RESET_SYNDROME_M3LOCKUP_POS 4 + +/* + * Field masks and offsets for the SGM775_SDS_FEATURE_AVAILABILITY structure. + */ +#define SGM775_SDS_FEATURE_FIRMWARE_MASK 0x1 +#define SGM775_SDS_FEATURE_DMC_MASK 0x2 +#define SGM775_SDS_FEATURE_MESSAGING_MASK 0x4 + +#define SGM775_SDS_FEATURE_FIRMWARE_POS 0 +#define SGM775_SDS_FEATURE_DMC_POS 1 +#define SGM775_SDS_FEATURE_MESSAGING_POS 2 + +/* + * Field masks and offsets for the SGM775_SDS_CPU_BOOTCTR structure. + */ +#define SGM775_SDS_CPU_BOOTCTR_CPU0_MASK 0xFF +#define SGM775_SDS_CPU_BOOTCTR_CPU1_MASK 0xFF00 +#define SGM775_SDS_CPU_BOOTCTR_CPU2_MASK 0xFF0000 +#define SGM775_SDS_CPU_BOOTCTR_CPU3_MASK 0xFF000000 +#define SGM775_SDS_CPU_BOOTCTR_CPU4_MASK 0xFF +#define SGM775_SDS_CPU_BOOTCTR_CPU5_MASK 0xFF00 +#define SGM775_SDS_CPU_BOOTCTR_CPU6_MASK 0xFF0000 +#define SGM775_SDS_CPU_BOOTCTR_CPU7_MASK 0xFF000000 + + +#define SGM775_SDS_CPU_BOOTCTR_CPU0_POS 0 +#define SGM775_SDS_CPU_BOOTCTR_CPU1_POS 8 +#define SGM775_SDS_CPU_BOOTCTR_CPU2_POS 16 +#define SGM775_SDS_CPU_BOOTCTR_CPU3_POS 24 +#define SGM775_SDS_CPU_BOOTCTR_CPU4_POS 0 +#define SGM775_SDS_CPU_BOOTCTR_CPU5_POS 8 +#define SGM775_SDS_CPU_BOOTCTR_CPU6_POS 16 +#define SGM775_SDS_CPU_BOOTCTR_CPU7_POS 24 + +/* + * Field masks and offsets for the SGM775_SDS_CPU_FLAGS structure. + */ +#define SGM775_SDS_CPU_FLAGS_CPU0_WFI_MASK 0x1 +#define SGM775_SDS_CPU_FLAGS_CPU1_WFI_MASK 0x100 +#define SGM775_SDS_CPU_FLAGS_CPU2_WFI_MASK 0x10000 +#define SGM775_SDS_CPU_FLAGS_CPU3_WFI_MASK 0x1000000 +#define SGM775_SDS_CPU_FLAGS_CPU4_WFI_MASK 0x1 +#define SGM775_SDS_CPU_FLAGS_CPU5_WFI_MASK 0x100 +#define SGM775_SDS_CPU_FLAGS_CPU6_WFI_MASK 0x10000 +#define SGM775_SDS_CPU_FLAGS_CPU7_WFI_MASK 0x1000000 + +#define SGM775_SDS_CPU_FLAGS_CPU0_WFI_POS 0 +#define SGM775_SDS_CPU_FLAGS_CPU1_WFI_POS 8 +#define SGM775_SDS_CPU_FLAGS_CPU2_WFI_POS 16 +#define SGM775_SDS_CPU_FLAGS_CPU3_WFI_POS 24 +#define SGM775_SDS_CPU_FLAGS_CPU4_WFI_POS 0 +#define SGM775_SDS_CPU_FLAGS_CPU5_WFI_POS 8 +#define SGM775_SDS_CPU_FLAGS_CPU6_WFI_POS 16 +#define SGM775_SDS_CPU_FLAGS_CPU7_WFI_POS 24 +/* + * Field masks and offsets for the SGM775_SDS_BOOTLOADER structure. + */ +#define SGM775_SDS_BOOTLOADER_VALID_MASK 0x1 +#define SGM775_SDS_BOOTLOADER_OFFSET_MASK 0xFFFFFFFF +#define SGM775_SDS_BOOTLOADER_SIZE_MASK 0xFFFFFFFF + +#define SGM775_SDS_BOOTLOADER_VALID_POS 0 +#define SGM775_SDS_BOOTLOADER_OFFSET_POS 0 +#define SGM775_SDS_BOOTLOADER_SIZE_POS 0 + +#endif /* SGM775_SDS_H */ diff --git a/product/sgm775/include/sgm775_ssc.h b/product/sgm775/include/sgm775_ssc.h new file mode 100644 index 00000000..9b514a11 --- /dev/null +++ b/product/sgm775/include/sgm775_ssc.h @@ -0,0 +1,42 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGM775_SSC_H +#define SGM775_SSC_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief System Security Control (SSC) register definitions + */ +struct ssc_reg { + FWK_R uint32_t RESERVED1[4]; + FWK_R uint32_t SSC_DBGCFG_STAT; + FWK_W uint32_t SSC_DBGCFG_SET; + FWK_W uint32_t SSC_DBGCFG_CLR; + FWK_R uint32_t RESERVED2[2]; + FWK_RW uint32_t SSC_SWDHOD; + FWK_RW uint32_t SSC_AUXDBGCFG; + FWK_R uint32_t RESERVED3; + FWK_RW uint32_t SSC_GPRETN; + FWK_R uint32_t RESERVED4[3]; + FWK_R uint32_t SSC_VERSION; + FWK_R uint32_t RESERVED5[995]; + FWK_R uint32_t PID4; + FWK_R uint32_t RESERVED6[3]; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t COMPID0; + FWK_R uint32_t COMPID1; + FWK_R uint32_t COMPID2; + FWK_R uint32_t COMPID3; +}; + +#endif /* SGM775_SSC_H */ diff --git a/product/sgm775/include/software_mmap.h b/product/sgm775/include/software_mmap.h new file mode 100644 index 00000000..e0ce772f --- /dev/null +++ b/product/sgm775/include/software_mmap.h @@ -0,0 +1,128 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * Software defined memory map shared between SCP and AP cores. + */ + +#ifndef SOFTWARE_MMAP_H +#define SOFTWARE_MMAP_H + +#include <fwk_macros.h> +#include <system_mmap.h> + +/* + * The 4KiB AP/SCP Shared memory at the base of Trusted SRAM is used for several + * purposes. These are: the Shared Data Storage (SDS) Memory Region, the SCMI + * secure payload areas, and the context area for Application Processor + * firmware. + * + * Shared Data Storage (SDS) Memory Region: Used for structured storage of data + * that is shared between SCP Firmware and Application Processor firmware. The + * SDS Memory Region occupies the area between the context region base and + * the SCMI Secure Payload base. + * + * SCMI Secure Payload Areas: Storage for SCMI message contents in both the + * Agent->Platform and Platform->Agent directions. + * + * Application Processor Context Area: The usage of this area is defined by the + * firmware running on the Application Processors. The SCP Firmware must zero + * this memory before releasing any Application Processors. This area must + * always be located in the top 64 bytes of the 4KiB reserved region. + * + * +-----------------------+ 4096 + * | | + * 64B | AP Context Area | + * | | + * +-----------------------+ + * | | + * 256B | Unused | + * | | + * +-----------------------+ + * | | + * | SCMI Sec. Payload | + * 128B | Platform to Agent | + * | | + * +-----------------------+ + * | | + * 128B | SCMI Sec. Payload | + * | Agent to Platform | + * | | + * +-----------------------+ + * | | + * 3520B | SDS Memory Region | + * | | + * +-----------------------+ 0 + */ + +/* Secure shared memory at the base of Trusted SRAM */ +#define SHARED_SECURE_BASE (TRUSTED_RAM_BASE) +#define SHARED_SECURE_SIZE (4 * FWK_KIB) + +/* SDS Memory Region */ +#define SDS_MEM_BASE (SHARED_SECURE_BASE) +#define SDS_MEM_SIZE (3520) + +/* AP Context Area */ +#define AP_CONTEXT_BASE (SHARED_SECURE_BASE + SHARED_SECURE_SIZE - \ + AP_CONTEXT_SIZE) +#define AP_CONTEXT_SIZE (64) + +/* SCMI Secure Payload Areas */ +#define SCMI_PAYLOAD_SIZE (128) +#define SCMI_PAYLOAD_S_A2P_BASE (SDS_MEM_BASE + SDS_MEM_SIZE) +#define SCMI_PAYLOAD_S_P2A_BASE (SCMI_PAYLOAD_S_A2P_BASE + SCMI_PAYLOAD_SIZE) + +/* + * The 4KiB AP/SCP Shared memory at the base of Non-trusted SRAM is used for the + * SCMI non-secure payload areas. + * + * Two SCMI non-Secure Payload Areas: Storage for SCMI message contents in both + * the Agent->Platform and Platform->Agent directions. + * + * +-----------------------+ 4096 + * 3584B | Unused | + * +-----------------------+ + * | | + * | Non-Sec. Channel 1 | + * | SCMI non-Sec. Payload | + * 128B | Platform to Agent | + * | | + * +-----------------------+ + * | | + * | Non-Sec. Channel 1 | + * 128B | SCMI non-Sec. Payload | + * | Agent to Platform | + * | | + * +-----------------------+ + * | | + * | Non-Sec. Channel 0 | + * | SCMI non-Sec. Payload | + * 128B | Platform to Agent | + * | | + * +-----------------------+ + * | | + * | Non-Sec. Channel 0 | + * 128B | SCMI non-Sec. Payload | + * | Agent to Platform | + * | | + * +-----------------------+ 0 + */ + +/* Non-secure shared memory at the base of Non-trusted SRAM */ +#define SHARED_NONSECURE_BASE (NONTRUSTED_RAM_BASE) +#define SHARED_NONSECURE_SIZE (4 * FWK_KIB) + +/* SCMI Non-Secure Payload Areas */ +#define SCMI_PAYLOAD0_NS_A2P_BASE (SHARED_NONSECURE_BASE) +#define SCMI_PAYLOAD0_NS_P2A_BASE (SCMI_PAYLOAD0_NS_A2P_BASE + \ + SCMI_PAYLOAD_SIZE) +#define SCMI_PAYLOAD1_NS_A2P_BASE (SCMI_PAYLOAD0_NS_P2A_BASE + \ + SCMI_PAYLOAD_SIZE) +#define SCMI_PAYLOAD1_NS_P2A_BASE (SCMI_PAYLOAD1_NS_A2P_BASE + \ + SCMI_PAYLOAD_SIZE) + +#endif /* SOFTWARE_MMAP_H */ diff --git a/product/sgm775/include/system_clock.h b/product/sgm775/include/system_clock.h new file mode 100644 index 00000000..c3f5a76c --- /dev/null +++ b/product/sgm775/include/system_clock.h @@ -0,0 +1,28 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SYSTEM_CLOCK_H +#define SYSTEM_CLOCK_H + +#include <fwk_macros.h> + +/*! + * \brief Calculates the necessary divider for obtaining a target frequency + * from a given clock. + * + * \param CLOCK_RATE The tick rate of the clock to be divided. + * + * \param TARGET_FREQ The target frequency to be obtained by the division. + * + * \return The divider needed to obtain TARGET_FREQ from CLOCK_RATE. + */ +#define DIV_FROM_CLOCK(CLOCK_RATE, TARGET_FREQ) ((CLOCK_RATE) / (TARGET_FREQ)) + +#define CLOCK_RATE_REFCLK (50UL * FWK_MHZ) +#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) + +#endif /* SYSTEM_CLOCK_H */ diff --git a/product/sgm775/include/system_mmap.h b/product/sgm775/include/system_mmap.h new file mode 100644 index 00000000..697f7811 --- /dev/null +++ b/product/sgm775/include/system_mmap.h @@ -0,0 +1,61 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SYSTEM_MMAP_H +#define SYSTEM_MMAP_H + +#include <sgm775_mmap.h> + +#define DMC_EXTERNAL0 (SYS0_BASE + 0x3FBE0000) +#define DMC_EXTERNAL1 (SYS0_BASE + 0x3FBF0000) +#define DMC_EXTERNAL2 (SYS0_BASE + 0x3FC00000) +#define DMC_EXTERNAL3 (SYS0_BASE + 0x3FC10000) + +#define BOARD_UART1_BASE (SYS0_BASE + 0x3FF70000) +#define PLAT_BASE (SYS0_BASE + 0x3FFE0000) + +#define PLL_GPU (PLAT_BASE + 0x00000008) +#define PLL_SYSTEM (PLAT_BASE + 0x0000000C) +#define PLL_VIDEO (PLAT_BASE + 0x00000010) +#define PLL_DISPLAY (PLAT_BASE + 0x00000014) + +#define PIX0_CONTROL (PLAT_BASE + 0x00000018) +#define PIX1_CONTROL (PLAT_BASE + 0x0000001C) + +#define SWCLKTCK_CONTROL (PLAT_BASE + 0x00000020) +#define SENSOR_SOC_TEMP (PLAT_BASE + 0x00000080) +#define PLATFORM_ID (PLAT_BASE + 0x000000E0) + +#define PLL_CLUS0_0 (PLAT_BASE + 0x00000100) +#define PLL_CLUS0_1 (PLAT_BASE + 0x00000104) +#define PLL_CLUS0_2 (PLAT_BASE + 0x00000108) +#define PLL_CLUS0_3 (PLAT_BASE + 0x0000010C) +#define PLL_CLUS0_4 (PLAT_BASE + 0x00000110) +#define PLL_CLUS0_5 (PLAT_BASE + 0x00000114) +#define PLL_CLUS0_6 (PLAT_BASE + 0x00000118) +#define PLL_CLUS0_7 (PLAT_BASE + 0x0000011C) + +#define DDR_PHY0 (SYS0_BASE + 0x3FB60000) +#define DDR_PHY1 (SYS0_BASE + 0x3FB70000) +#define DDR_PHY2 (SYS0_BASE + 0x3FB80000) +#define DDR_PHY3 (SYS0_BASE + 0x3FB90000) + +#define GPV_CCI_GPU1 (SYS1_BASE + 0x2A004000) +#define GPV_CCI_GPU0 (SYS1_BASE + 0x2A005000) +#define GPV_CCI_LITTLE (SYS1_BASE + 0x2A006000) +#define GPV_CCI_BIG (SYS1_BASE + 0x2A007000) +#define GPV_VPU (SYS1_BASE + 0x2A243000) +#define GPV_DPU0 (SYS1_BASE + 0x2A244000) +#define GPV_DPU1 (SYS1_BASE + 0x2A245000) + +#define DMC_INTERNAL0 (SYS1_BASE + 0x2A500000) +#define DMC_INTERNAL1 (SYS1_BASE + 0x2A540000) +#define DMC_INTERNAL2 (SYS1_BASE + 0x2A580000) +#define DMC_INTERNAL3 (SYS1_BASE + 0x2A5C0000) + + +#endif /* SYSTEM_MMAP_H */ diff --git a/product/sgm775/include/system_mmap_scp.h b/product/sgm775/include/system_mmap_scp.h new file mode 100644 index 00000000..097e4316 --- /dev/null +++ b/product/sgm775/include/system_mmap_scp.h @@ -0,0 +1,21 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * SCP ROM and RAM memory sizes. These definitions are kept isolated without + * the UINT32_C() or UL decorators allowing them to be used in the linker + * script. + */ + +#ifndef SYSTEM_MMAP_SCP_H +#define SYSTEM_MMAP_SCP_H + +#include <sgm775_mmap_scp.h> + +#define SCP_ROM_SIZE (64 * 1024) +#define SCP_RAM_SIZE (128 * 1024) + +#endif /* SYSTEM_MMAP_SCP_H */ |