diff options
-rw-r--r-- | product/n1sdp/scp_ramfw/firmware.mk | 65 | ||||
-rw-r--r-- | product/n1sdp/scp_ramfw/fmw_memory.ld.S | 32 |
2 files changed, 97 insertions, 0 deletions
diff --git a/product/n1sdp/scp_ramfw/firmware.mk b/product/n1sdp/scp_ramfw/firmware.mk new file mode 100644 index 00000000..4e2d2cfe --- /dev/null +++ b/product/n1sdp/scp_ramfw/firmware.mk @@ -0,0 +1,65 @@ +# +# Arm SCP/MCP Software +# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BS_FIRMWARE_CPU := cortex-m7 +BS_FIRMWARE_HAS_MULTITHREADING := yes +BS_FIRMWARE_HAS_NOTIFICATION := yes +BS_FIRMWARE_MODULE_HEADERS_ONLY := + +BS_FIRMWARE_MODULES := \ + armv7m_mpu \ + pl011 \ + log \ + cmn600 \ + apcontext \ + power_domain \ + ppu_v1 \ + ppu_v0 \ + system_power \ + n1sdp_pll \ + dmc620 \ + ddr_phy500 \ + mhu \ + smt \ + scmi \ + sds \ + pik_clock \ + css_clock \ + clock \ + gtimer \ + timer \ + scmi_power_domain \ + scmi_system_power \ + n1sdp_flash \ + n1sdp_system + +BS_FIRMWARE_SOURCES := \ + config_system_power.c \ + rtx_config.c \ + n1sdp_core.c \ + config_armv7m_mpu.c \ + config_log.c \ + config_power_domain.c \ + config_ppu_v0.c \ + config_ppu_v1.c \ + config_dmc620.c \ + config_ddr_phy500.c \ + config_mhu.c \ + config_smt.c \ + config_scmi.c \ + config_sds.c \ + config_timer.c \ + config_cmn600.c \ + config_scmi_system_power.c \ + config_n1sdp_pll.c \ + config_pik_clock.c \ + config_css_clock.c \ + config_clock.c \ + config_n1sdp_flash.c \ + config_apcontext.c + +include $(BS_DIR)/firmware.mk diff --git a/product/n1sdp/scp_ramfw/fmw_memory.ld.S b/product/n1sdp/scp_ramfw/fmw_memory.ld.S new file mode 100644 index 00000000..f9cff704 --- /dev/null +++ b/product/n1sdp/scp_ramfw/fmw_memory.ld.S @@ -0,0 +1,32 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * RAM firmware memory layout for the linker script. + */ + +#ifndef FMW_MEMORY_LD_S +#define FMW_MEMORY_LD_S + +#include <n1sdp_scp_system_mmap.h> + +#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION + +/* + * RAM instruction memory + */ +#define FIRMWARE_MEM0_SIZE SCP_RAM0_SIZE +#define FIRMWARE_MEM0_BASE SCP_RAM0_BASE + +/* + * RAM data memory + */ +#define FIRMWARE_MEM1_SIZE SCP_RAM1_SIZE +#define FIRMWARE_MEM1_BASE SCP_RAM1_BASE + +#define FIRMWARE_STACK_SIZE (1 * 1024) + +#endif /* FMW_MEMORY_LD_S */ |