n1sdp: add pik header files for n1sdp SCP

Change-Id: I169f9a1e43dd309934a1eb63e2c38f0cdab0c3a7
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

4 files changed, 303 insertions, 0 deletions

diff --git a/product/n1sdp/include/n1sdp_pik_cpu.h b/product/n1sdp/include/n1sdp_pik_cpu.h
new file mode 100644
index 00000000..9d236974
--- /dev/null
+++ b/product/n1sdp/include/n1sdp_pik_cpu.h
@@ -0,0 +1,87 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef N1SDP_PIK_CPU_H
+#define N1SDP_PIK_CPU_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+
+#define PE_COUNT_MAX 16
+
+/*!
+ * \brief PE Static Configuration register definitions
+ */
+struct static_config_reg {
+    FWK_RW  uint32_t STATIC_CONFIG;
+    FWK_RW  uint32_t RVBARADDR_LW;
+    FWK_RW  uint32_t RVBARADDR_UP;
+            uint32_t RESERVED;
+};
+
+/*!
+ * \brief AP cores clock control register definitions
+ */
+struct coreclk_reg {
+    FWK_RW  uint32_t CTRL;
+    FWK_RW  uint32_t DIV;
+            uint32_t RESERVED;
+    FWK_RW  uint32_t MOD;
+};
+
+/*!
+ * \brief CPU (V8.2) PIK register definitions
+ */
+struct pik_cpu_reg {
+  FWK_RW  uint32_t   CLUSTER_CONFIG;
+          uint8_t    RESERVED0[0x10 - 0x4];
+  struct static_config_reg  STATIC_CONFIG[PE_COUNT_MAX];
+          uint8_t    RESERVED1[0x800 - 0x110];
+  FWK_RW  uint32_t   PPUCLK_CTRL;
+  FWK_RW  uint32_t   PPUCLK_DIV1;
+          uint8_t    RESERVED2[0x810 - 0x808];
+  FWK_RW  uint32_t   PCLK_CTRL;
+          uint8_t    RESERVED3[0x820 - 0x814];
+  FWK_RW  uint32_t   ATCLK_CTRL;
+          uint8_t    RESERVED4[0x830 - 0x824];
+  FWK_RW  uint32_t   GICCLK_CTRL;
+          uint8_t    RESERVED5[0x840 - 0x834];
+  FWK_RW  uint32_t   AMBACLK_CTRL;
+          uint8_t    RESERVED6[0x850 - 0x844];
+  FWK_RW  uint32_t   CLUSCLK_CTRL;
+  FWK_RW  uint32_t   CLUSCLK_DIV1;
+          uint8_t    RESERVED7[0x860 - 0x858];
+  struct coreclk_reg CORECLK[8];
+          uint8_t    RESERVED8[0xA00 - 0x8E0];
+  FWK_R   uint32_t   CLKFORCE_STATUS;
+  FWK_RW  uint32_t   CLKFORCE_SET;
+  FWK_RW  uint32_t   CLKFORCE_CLR;
+          uint8_t    RESERVED9[0xFB8 - 0xA0C];
+  FWK_R   uint32_t   CAP2;
+  FWK_R   uint32_t   CAP;
+  FWK_R   uint32_t   PIK_CONFIG;
+  FWK_R   uint8_t    RESERVED10[0xFD0 - 0xFC4];
+  FWK_R   uint32_t   PID4;
+  FWK_R   uint32_t   PID5;
+  FWK_R   uint32_t   PID6;
+  FWK_R   uint32_t   PID7;
+  FWK_R   uint32_t   PID0;
+  FWK_R   uint32_t   PID1;
+  FWK_R   uint32_t   PID2;
+  FWK_R   uint32_t   PID3;
+  FWK_R   uint32_t   ID0;
+  FWK_R   uint32_t   ID1;
+  FWK_R   uint32_t   ID2;
+  FWK_R   uint32_t   ID3;
+};
+
+#define PIK_CPU_CAP_CLUSSYNC       UINT32_C(0x00000001)
+#define PIK_CPU_CAP_CORESYNC(CORE) ((uint32_t)(1 << ((CORE) + 1)))
+#define PIK_CPU_CAP_PE_MASK        UINT32_C(0xF0000000)
+#define PIK_CPU_CAP_PE_POS         28
+
+#endif  /* N1SDP_PIK_CPU_H */
diff --git a/product/n1sdp/include/n1sdp_pik_debug.h b/product/n1sdp/include/n1sdp_pik_debug.h
new file mode 100644
index 00000000..f84df2bd
--- /dev/null
+++ b/product/n1sdp/include/n1sdp_pik_debug.h
@@ -0,0 +1,54 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef N1SDP_PIK_DEBUG_H
+#define N1SDP_PIK_DEBUG_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+
+/*!
+ * \brief Debug register definitions
+ */
+struct pik_debug_reg {
+  FWK_RW  uint32_t  DEBUG_CTRL;
+  FWK_R   uint32_t  DEBUG_STATUS;
+  FWK_RW  uint32_t  DEBUG_CONFIG;
+          uint32_t  RESERVED0;
+  FWK_R   uint32_t  APP_DAP_TARGET_ID;
+  FWK_R   uint32_t  SCP_DAP_TARGET_ID;
+  FWK_R   uint32_t  DAP_INSTANCE_ID;
+          uint8_t   RESERVED1[0x810-0x01C];
+  FWK_RW  uint32_t  TRACECLK_CTRL;
+  FWK_RW  uint32_t  TRACECLK_DIV1;
+          uint8_t   RESERVED2[0x820-0x818];
+  FWK_RW  uint32_t  PCLKDBG_CTRL;
+          uint8_t   RESERVED3[0x830-0x824];
+  FWK_RW  uint32_t  ATCLKDBG_CTRL;
+  FWK_RW  uint32_t  ATCLKDBG_DIV1;
+          uint8_t   RESERVED4[0xFC0-0x838];
+  FWK_R   uint32_t  PCL_CONFIG;
+          uint8_t   RESERVED5[0xFD0-0xFC4];
+  FWK_R   uint32_t  PID4;
+  FWK_R   uint32_t  PID5;
+  FWK_R   uint32_t  PID6;
+  FWK_R   uint32_t  PID7;
+  FWK_R   uint32_t  PID0;
+  FWK_R   uint32_t  PID1;
+  FWK_R   uint32_t  PID2;
+  FWK_R   uint32_t  PID3;
+  FWK_R   uint32_t  ID0;
+  FWK_R   uint32_t  ID1;
+  FWK_R   uint32_t  ID2;
+  FWK_R   uint32_t  ID3;
+};
+
+#define CSYSPWRUPACK  UINT32_C(0x00000004)
+#define CDBGPWRUPACK  UINT32_C(0x00000002)
+#define CDBGRSTACK    UINT32_C(0x00000001)
+
+#endif  /* N1SDP_PIK_DEBUG_H */
diff --git a/product/n1sdp/include/n1sdp_pik_scp.h b/product/n1sdp/include/n1sdp_pik_scp.h
new file mode 100644
index 00000000..b636eb8d
--- /dev/null
+++ b/product/n1sdp/include/n1sdp_pik_scp.h
@@ -0,0 +1,88 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     SCP PIK registers
+ */
+
+#ifndef N1SDP_PIK_SCP_H
+#define N1SDP_PIK_SCP_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+
+/*!
+ * \brief SCP PIK register definitions
+ */
+struct pik_scp_reg {
+            uint8_t   RESERVED0[0x10 - 0x0];
+    FWK_RW  uint32_t  RESET_SYNDROME;
+            uint8_t   RESERVED1[0x20 - 0x14];
+    FWK_RW  uint32_t  SURVIVAL_RESET_STATUS;
+            uint8_t   RESERVED2[0x30 - 0x24];
+    FWK_RW  uint32_t  MCP_SEC_CTRL;
+    FWK_RW  uint32_t  ADDR_TRANS;
+    FWK_RW  uint32_t  DBG_ADDR_TRANS;
+            uint8_t   RESERVED3[0x40 - 0x3C];
+    FWK_RW  uint32_t  WS1_TIMER_MATCH;
+    FWK_RW  uint32_t  WS1_TIMER_EN;
+            uint8_t   RESERVED4[0x200 - 0x48];
+    FWK_R   uint32_t  SS_RESET_STATUS;
+    FWK_W   uint32_t  SS_RESET_SET;
+    FWK_W   uint32_t  SS_RESET_CLR;
+            uint8_t   RESERVED5[0x810 - 0x20C];
+    FWK_RW  uint32_t  CORECLK_CTRL;
+    FWK_RW  uint32_t  CORECLK_DIV1;
+            uint8_t   RESERVED6[0x820 - 0x818];
+    FWK_RW  uint32_t  ACLK_CTRL;
+    FWK_RW  uint32_t  ACLK_DIV1;
+            uint8_t   RESERVED7[0xA10 - 0x828];
+    FWK_R   uint32_t  PLL_STATUS[17];
+            uint8_t   RESERVED8[0xA60 - 0xA54];
+    FWK_R   uint32_t  CONS_MMUTCU_INT_STATUS;
+    FWK_R   uint32_t  CONS_MMUTBU_INT_STATUS0;
+    FWK_R   uint32_t  CONS_MMUTBU_INT_STATUS1;
+            uint8_t   RESERVED9[0xB00 - 0xA6C];
+    FWK_R   uint32_t  MHU_NS_INT_STATUS;
+    FWK_R   uint32_t  MHU_S_INT_STATUS;
+            uint8_t   RESERVED10[0xB20 - 0xB08];
+    FWK_R   uint32_t  CPU_PPU_INT_STATUS[8];
+    FWK_R   uint32_t  CLUS_PPU_INT_STATUS;
+            uint8_t   RESERVED11[0xB60 - 0xB44];
+    FWK_R   uint32_t  TIMER_INT_STATUS[8];
+    FWK_R   uint32_t  CPU_PLL_LOCK_STATUS[8];
+            uint8_t   RESERVED12[0xBC0 - 0xBA0];
+    FWK_R   uint32_t  CPU_PLL_UNLOCK_STATUS[8];
+            uint8_t   RESERVED13[0xBF0 - 0xBE0];
+    FWK_R   uint32_t  CLUSTER_PLL_LOCK_STATUS;
+    FWK_R   uint32_t  CLUSTER_PLL_UNLOCK_STATUS;
+            uint8_t   RESERVED14[0xC00 - 0xBF8];
+    FWK_R   uint32_t  CLUS_FAULT_INT_STATUS;
+            uint8_t   RESERVED15[0xC30 - 0xC04];
+    FWK_R   uint32_t  CLUSTER_ECCERR_INT_STATUS;
+            uint8_t   RESERVED16[0xD00 - 0xC34];
+    FWK_R   uint32_t  DMC0_4_INT_STATUS;
+    FWK_R   uint32_t  DMC1_5_INT_STATUS;
+    FWK_R   uint32_t  DMC2_6_INT_STATUS;
+    FWK_R   uint32_t  DMC3_7_INT_STATUS;
+            uint8_t   RESERVED17[0xFC0 - 0xD10];
+    FWK_R   uint32_t  PCL_CFG;
+            uint8_t   RESERVED18[0xFD0 - 0xFC4];
+    FWK_R   uint32_t  PID4;
+    FWK_R   uint32_t  PID5;
+    FWK_R   uint32_t  PID6;
+    FWK_R   uint32_t  PID7;
+    FWK_R   uint32_t  PID0;
+    FWK_R   uint32_t  PID1;
+    FWK_R   uint32_t  PID2;
+    FWK_R   uint32_t  PID3;
+    FWK_R   uint32_t  ID0;
+    FWK_R   uint32_t  ID1;
+    FWK_R   uint32_t  ID2;
+    FWK_R   uint32_t  ID3;
+};
+
+#endif  /* N1SDP_PIK_SCP_H */
diff --git a/product/n1sdp/include/n1sdp_pik_system.h b/product/n1sdp/include/n1sdp_pik_system.h
new file mode 100644
index 00000000..cbe196c0
--- /dev/null
+++ b/product/n1sdp/include/n1sdp_pik_system.h
@@ -0,0 +1,74 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef N1SDP_PIK_SYSTEM_H
+#define N1SDP_PIK_SYSTEM_H
+
+#include <stdint.h>
+#include <fwk_macros.h>
+
+/*!
+ * \brief TCU clock register definitions
+ */
+struct tcuclk_ctrl_reg {
+    FWK_RW uint32_t   TCUCLK_CTRL;
+    FWK_RW uint32_t   TCUCLK_DIV1;
+};
+
+/*!
+ * \brief System PIK register definitions
+ */
+struct pik_system_reg {
+            uint8_t         RESERVED0[0x800 - 0x0];
+    FWK_RW  uint32_t        PPUCLK_CTRL;
+    FWK_RW  uint32_t        PPUCLK_DIV1;
+            uint8_t         RESERVED1[0x820 - 0x808];
+    FWK_RW  uint32_t        INTCLK_CTRL;
+    FWK_RW  uint32_t        INTCLK_DIV1;
+            uint8_t         RESERVED2[0x830 - 0x828];
+    struct tcuclk_ctrl_reg  TCUCLK[4];
+    FWK_RW  uint32_t        GICCLK_CTRL;
+    FWK_RW  uint32_t        GICCLK_DIV1;
+            uint8_t         RESERVED3[0x860 - 0x858];
+    FWK_RW  uint32_t        PCLKSCP_CTRL;
+    FWK_RW  uint32_t        PCLKSCP_DIV1;
+            uint8_t         RESERVED4[0x870 - 0x868];
+    FWK_RW  uint32_t        SYSPERCLK_CTRL;
+    FWK_RW  uint32_t        SYSPERCLK_DIV1;
+            uint8_t         RESERVED5[0x880 - 0x878];
+    FWK_RW  uint32_t        DMCCLK_CTRL;
+    FWK_RW  uint32_t        DMCCLK_DIV1;
+            uint8_t         RESERVED6[0x890 - 0x888];
+    FWK_RW  uint32_t        SYSPCLKDBG_CTRL;
+    FWK_RW  uint32_t        SYSPCLKDBG_DIV1;
+            uint8_t         RESERVED7[0x8A0 - 0x898];
+    FWK_RW  uint32_t        UARTCLK_CTRL;
+    FWK_RW  uint32_t        UARTCLK_DIV1;
+            uint8_t         RESERVED8[0xA00 - 0x8A8];
+    FWK_R   uint32_t        CLKFORCE_STATUS;
+    FWK_W   uint32_t        CLKFORCE_SET;
+    FWK_W   uint32_t        CLKFORCE_CLR;
+            uint8_t         RESERVED9[0xB0C - 0xA0C];
+    FWK_RW  uint32_t        SYSTOP_RST_DLY;
+            uint8_t         RESERVED10[0xFC0 - 0xB10];
+    FWK_R   uint32_t        PCL_CONFIG;
+            uint8_t         RESERVED11[0xFD0 - 0xFC4];
+    FWK_R   uint32_t        PID4;
+    FWK_R   uint32_t        PID5;
+    FWK_R   uint32_t        PID6;
+    FWK_R   uint32_t        PID7;
+    FWK_R   uint32_t        PID0;
+    FWK_R   uint32_t        PID1;
+    FWK_R   uint32_t        PID2;
+    FWK_R   uint32_t        PID3;
+    FWK_R   uint32_t        ID0;
+    FWK_R   uint32_t        ID1;
+    FWK_R   uint32_t        ID2;
+    FWK_R   uint32_t        ID3;
+};
+
+#endif  /* N1SDP_PIK_SYSTEM_H */