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authorManoj Kumar <manoj.kumar3@arm.com>2018-10-26 11:30:45 +0530
committerdavidcunado-arm <david.cunado@arm.com>2018-10-30 16:58:33 +0000
commit6e7eb5b397a6154d8991bb1b34b4f85beb147635 (patch)
tree0b157aa02391614749e2ff923c5939e2064f64f6 /product/n1sdp
parent173b44e86668ec707a4a38109a69341e1aae3e14 (diff)
n1sdp: scp_ramfw - add CMN-600 config file
Change-Id: Iac7c567256b8f52d84dbe2a9e51425411e6cb7bd Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Diffstat (limited to 'product/n1sdp')
-rw-r--r--product/n1sdp/scp_ramfw/config_cmn600.c136
1 files changed, 136 insertions, 0 deletions
diff --git a/product/n1sdp/scp_ramfw/config_cmn600.c b/product/n1sdp/scp_ramfw/config_cmn600.c
new file mode 100644
index 00000000..c1b29896
--- /dev/null
+++ b/product/n1sdp/scp_ramfw/config_cmn600.c
@@ -0,0 +1,136 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_cmn600.h>
+#include <n1sdp_scp_mmap.h>
+#include <config_clock.h>
+
+/*
+ * CMN600 nodes
+ */
+#define DMC0_ID 0x60
+#define DMC1_ID 0x6C
+#define NODE_ID_HND 0x68
+#define NODE_ID_SBSX 0x64
+
+static const unsigned int snf_table[] = {
+ DMC0_ID, /* Maps to HN-F logical node 0 */
+ DMC0_ID, /* Maps to HN-F logical node 1 */
+ DMC1_ID, /* Maps to HN-F logical node 2 */
+ DMC1_ID, /* Maps to HN-F logical node 3 */
+};
+
+static const struct mod_cmn600_memory_region_map mmap[] = {
+ {
+ /*
+ * System cache backed region
+ * Map: 0x0000_0000_0000 - 0x03FF_FFFF_FFFF (4 TB)
+ */
+ .base = UINT64_C(0x000000000000),
+ .size = UINT64_C(4) * FWK_TIB,
+ .type = MOD_CMN600_MEMORY_REGION_TYPE_SYSCACHE,
+ },
+ {
+ /*
+ * Boot region
+ * Map: 0x0000_0000_0000 - 0x0000_07FF_FFFF (128 MB)
+ */
+ .base = UINT64_C(0x000000000000),
+ .size = UINT64_C(128) * FWK_MIB,
+ .type = MOD_CMN600_REGION_TYPE_SYSCACHE_SUB,
+ .node_id = NODE_ID_SBSX,
+ },
+ {
+ /*
+ * Peripherals
+ * Map: 0x00_0800_0000 - 0x00_0FFF_FFFF (128 MB)
+ */
+ .base = UINT64_C(0x0008000000),
+ .size = UINT64_C(128) * FWK_MIB,
+ .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+ .node_id = NODE_ID_HND,
+ },
+ {
+ /*
+ * Peripherals
+ * Map: 0x00_1000_0000 - 0x00_1FFF_FFFF (256 MB)
+ */
+ .base = UINT64_C(0x0010000000),
+ .size = UINT64_C(256) * FWK_MIB,
+ .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+ .node_id = NODE_ID_HND,
+ },
+ {
+ /*
+ * Peripherals
+ * Map: 0x00_2000_0000 - 0x00_3FFF_FFFF (512 MB)
+ */
+ .base = UINT64_C(0x0020000000),
+ .size = UINT64_C(512) * FWK_MIB,
+ .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+ .node_id = NODE_ID_HND,
+ },
+ {
+ /*
+ * Peripherals
+ * Map: 0x00_4000_0000 - 0x00_7FFF_FFFF (1 GB)
+ */
+ .base = UINT64_C(0x0040000000),
+ .size = UINT64_C(1) * FWK_GIB,
+ .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+ .node_id = NODE_ID_HND,
+ },
+ {
+ /*
+ * Peripherals
+ * Map: 0x04_0000_0000 - 0x07_FFFF_FFFF (16 GB)
+ */
+ .base = UINT64_C(0x0400000000),
+ .size = UINT64_C(16) * FWK_GIB,
+ .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+ .node_id = NODE_ID_HND,
+ },
+ {
+ /*
+ * Peripherals
+ * Map: 0x08_0000_0000 - 0x0F_FFFF_FFFF (32 GB)
+ */
+ .base = UINT64_C(0x0800000000),
+ .size = UINT64_C(32) * FWK_GIB,
+ .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+ .node_id = NODE_ID_HND,
+ },
+ {
+ /*
+ * Peripherals
+ * Map: 0x10_0000_0000 - 0x1F_FFFF_FFFF (64 GB)
+ */
+ .base = UINT64_C(0x1000000000),
+ .size = UINT64_C(64) * FWK_GIB,
+ .type = MOD_CMN600_MEMORY_REGION_TYPE_IO,
+ .node_id = NODE_ID_HND,
+ },
+};
+
+const struct fwk_module_config config_cmn600 = {
+ .get_element_table = NULL,
+ .data = &((struct mod_cmn600_config) {
+ .base = SCP_CMN600_BASE,
+ .mesh_size_x = 4,
+ .mesh_size_y = 2,
+ .hnd_node_id = NODE_ID_HND,
+ .snf_table = snf_table,
+ .snf_count = FWK_ARRAY_SIZE(snf_table),
+ .mmap_table = mmap,
+ .mmap_count = FWK_ARRAY_SIZE(mmap),
+ .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK,
+ CLOCK_IDX_INTERCONNECT),
+ }),
+};