n1sdp: add memory map include files for n1sdp MCP

This patch adds the following header files:

n1sdp_mcp_mmap.h -> N1SDP MCP's peripheral memory map information.
n1sdp_mcp_software_mmap.h -> Definitions of software mapping of
                             hardware memories.
n1sdp_mcp_system_mmap.h -> Definitions of external & internal
                           memories connected to MCP.

Change-Id: I1283885b4b7676a18f9c20b0b586309b27db8d60
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

3 files changed, 129 insertions, 0 deletions

diff --git a/product/n1sdp/include/n1sdp_mcp_mmap.h b/product/n1sdp/include/n1sdp_mcp_mmap.h
new file mode 100644
index 00000000..60004c2e
--- /dev/null
+++ b/product/n1sdp/include/n1sdp_mcp_mmap.h
@@ -0,0 +1,68 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef N1SDP_MCP_MMAP_H
+#define N1SDP_MCP_MMAP_H
+
+#include <stdint.h>
+
+/*
+ * Top-level base addresses
+ */
+#define MCP_SOC_EXPANSION1_BASE       UINT32_C(0x01000000)
+#define MCP_SOC_EXPANSION2_BASE       UINT32_C(0x21000000)
+#define MCP_SOC_EXPANSION3_BASE       UINT32_C(0x40000000)
+#define MCP_SOC_EXPANSION4_BASE       UINT32_C(0x48000000)
+#define MCP_PERIPH_BASE               UINT32_C(0x4C000000)
+#define MCP_MEMORY_CONTROLLER         UINT32_C(0x4E000000)
+#define MCP_POWER_PERIPH_BASE         UINT32_C(0x50000000)
+#define MCP_SYS0_BASE                 UINT32_C(0x60000000)
+#define MCP_SYS1_BASE                 UINT32_C(0xA0000000)
+#define MCP_PPB_BASE_INTERNAL         UINT32_C(0xE0000000)
+#define MCP_PPB_BASE_EXTERNAL         UINT32_C(0xE0040000)
+
+/*
+ * Peripherals
+ */
+#define MCP_REFCLK_CNTCTL_BASE        (MCP_PERIPH_BASE)
+#define MCP_REFCLK_CNTBASE0_BASE      (MCP_PERIPH_BASE + 0x1000)
+#define MCP_UART0_BASE                (MCP_PERIPH_BASE + 0x2000)
+#define MCP_WDOG_BASE                 (MCP_PERIPH_BASE + 0x6000)
+
+#define MCP_I2C0_BASE                 (0x3FFFE000)
+#define MCP_I2C1_BASE                 (0x3FFFF000)
+
+/*
+ * Power control peripherals
+ */
+#define MCP_PIK_BASE                  (MCP_POWER_PERIPH_BASE)
+
+/*
+ * Base addresses of MHUv1 devices
+ */
+#define MCP_MHU_AP_BASE               (MCP_PERIPH_BASE + 0x400000)
+#define MCP_MHU_SCP_BASE              UINT32_C(0x45600000)
+
+#define MHU_MCP_TO_AP_NS              (MCP_MHU_AP_BASE + 0x0020)
+#define MHU_AP_TO_MCP_NS              (MCP_MHU_AP_BASE + 0x0120)
+#define MHU_MCP_TO_AP_S               (MCP_MHU_AP_BASE + 0x0200)
+#define MHU_AP_TO_MCP_S               (MCP_MHU_AP_BASE + 0x0300)
+
+#define MHU_SCP_TO_MCP_NS             (MCP_MHU_SCP_BASE + 0x0020)
+#define MHU_MCP_TO_SCP_NS             (MCP_MHU_SCP_BASE + 0x0120)
+#define MHU_SCP_TO_MCP_S              (MCP_MHU_SCP_BASE + 0x0200)
+#define MHU_MCP_TO_SCP_S              (MCP_MHU_SCP_BASE + 0x0300)
+
+/*
+ * Shared memory regions
+ */
+#define MCP_AP_SHARED_SECURE_RAM      (MCP_PERIPH_BASE + 0x420000)
+#define MCP_AP_SHARED_NONSECURE_RAM   (MCP_PERIPH_BASE + 0x410000)
+#define MCP_SCP_SHARED_SECURE_RAM     (0x45620000)
+#define MCP_SCP_SHARED_NONSECURE_RAM  (0x45610000)
+
+#endif /* N1SDP_MCP_MMAP_H */
diff --git a/product/n1sdp/include/n1sdp_mcp_software_mmap.h b/product/n1sdp/include/n1sdp_mcp_software_mmap.h
new file mode 100644
index 00000000..a64aecd1
--- /dev/null
+++ b/product/n1sdp/include/n1sdp_mcp_software_mmap.h
@@ -0,0 +1,29 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     Software defined memory map shared between SCP and MCP cores.
+ */
+
+#ifndef N1SDP_MCP_SOFTWARE_MMAP_H
+#define N1SDP_MCP_SOFTWARE_MMAP_H
+
+#include <n1sdp_mcp_mmap.h>
+
+/* SCMI payload size */
+#define MCP_SCMI_PAYLOAD_SIZE      (128)
+
+/* SCMI non-secure payload areas */
+#define SCMI_PAYLOAD_SCP_TO_MCP_NS (MCP_SCP_SHARED_NONSECURE_RAM)
+#define SCMI_PAYLOAD_MCP_TO_SCP_NS (MCP_SCP_SHARED_NONSECURE_RAM + \
+                                                MCP_SCMI_PAYLOAD_SIZE)
+
+/* SCMI secure payload areas */
+#define SCMI_PAYLOAD_SCP_TO_MCP_S  (MCP_SCP_SHARED_SECURE_RAM)
+#define SCMI_PAYLOAD_MCP_TO_SCP_S  (MCP_SCP_SHARED_SECURE_RAM + \
+                                                MCP_SCMI_PAYLOAD_SIZE)
+
+#endif /* N1SDP_MCP_SOFTWARE_MMAP_H */
diff --git a/product/n1sdp/include/n1sdp_mcp_system_mmap.h b/product/n1sdp/include/n1sdp_mcp_system_mmap.h
new file mode 100644
index 00000000..98c8d087
--- /dev/null
+++ b/product/n1sdp/include/n1sdp_mcp_system_mmap.h
@@ -0,0 +1,32 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef N1SDP_MCP_SYSTEM_MMAP_H
+#define N1SDP_MCP_SYSTEM_MMAP_H
+
+/*
+ * External QSPI flash memory - mapped address
+ */
+#define MCP_QSPI_FLASH_BASE_ADDR     0x30000000
+#define MCP_QSPI_FLASH_BASE_ADDR_ALT 0x00800000
+#define MCP_QSPI_FLASH_SIZE          0x02000000
+
+/*
+ * Internal MCP's ROM/RAM base address
+ */
+#define MCP_ROM_BASE                 0x00000000
+#define MCP_RAM0_BASE                0x00800000
+#define MCP_RAM1_BASE                0x20000000
+
+/*
+ * Internal MCP's ROM/RAM sizes
+ */
+#define MCP_ROM_SIZE                 (128 * 1024)
+#define MCP_RAM0_SIZE                (512 * 1024)
+#define MCP_RAM1_SIZE                (256 * 1024)
+
+#endif /* N1SDP_MCP_SYSTEM_MMAP_H */