Platform/ARM/N1sdp: implement the PciHostBridgeLib support.

N1SDP includes a Pcie root complex. So implement the
PciHostBridgeLib glue Layer and enable support for the
PCIe.

Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>

8 files changed, 347 insertions, 3 deletions

diff --git a/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/AcpiTables.inf b/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/AcpiTables.inf
index 991796b8..ff047e86 100644
--- a/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/AcpiTables.inf
+++ b/Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/AcpiTables.inf
@@ -28,7 +28,6 @@
   Madt.aslc
   Spcr.aslc
 
-
 [Packages]
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
@@ -41,7 +40,6 @@
   gArmPlatformTokenSpaceGuid.PcdClusterCount
   gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
   gArmPlatformTokenSpaceGuid.PL011UartInterrupt
-
   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
diff --git a/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
new file mode 100644
index 00000000..b20bfd4b
--- /dev/null
+++ b/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -0,0 +1,194 @@
+/** @file

+*  PCI Host Bridge Library instance for ARM n1sdp platform

+*

+*  Copyright (c) 2018, ARM Limited. All rights reserved.

+*

+*  This program and the accompanying materials are licensed and made available

+*  under the terms and conditions of the BSD License which accompanies this

+*  distribution.  The full text of the license may be found at

+*  http://opensource.org/licenses/bsd-license.php

+*

+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+*

+**/

+

+#include <PiDxe.h>

+#include <Library/DebugLib.h>

+#include <Library/DevicePathLib.h>

+#include <Library/MemoryAllocationLib.h>

+#include <Library/PcdLib.h>

+#include <Library/PciHostBridgeLib.h>

+#include <Protocol/PciHostBridgeResourceAllocation.h>

+#include <Protocol/PciRootBridgeIo.h>

+

+#define ROOT_COMPLEX_NUM 1

+

+GLOBAL_REMOVE_IF_UNREFERENCED

+STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {

+  L"Mem", L"I/O", L"Bus"

+};

+

+#pragma pack(1)

+typedef struct {

+  ACPI_HID_DEVICE_PATH     AcpiDevicePath;

+  EFI_DEVICE_PATH_PROTOCOL EndDevicePath;

+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;

+#pragma pack ()

+

+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath [ROOT_COMPLEX_NUM] = {

+//PCIe

+  {

+    {

+      {

+        ACPI_DEVICE_PATH,

+        ACPI_DP,

+        {

+          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),

+          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)

+        }

+      },

+      EISA_PNP_ID(0x0A08), // PCIe

+      0

+    },

+    {

+      END_DEVICE_PATH_TYPE,

+      END_ENTIRE_DEVICE_PATH_SUBTYPE,

+      {

+        END_DEVICE_PATH_LENGTH,

+        0

+      }

+    }

+  }

+};

+

+STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {

+  {

+    0,                                              // Segment

+    0,                                              // Supports

+    0,                                              // Attributes

+    TRUE,                                           // DmaAbove4G

+    FALSE,                                          // NoExtendedConfigSpace

+    FALSE,                                          // ResourceAssigned

+    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes

+    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,

+    {

+      // Bus

+      FixedPcdGet32 (PcdPcieBusMin),

+      FixedPcdGet32 (PcdPcieBusMax)

+    }, {

+      // Io

+      FixedPcdGet64 (PcdPcieIoBase),

+      FixedPcdGet64 (PcdPcieIoBase) + FixedPcdGet64 (PcdPcieIoSize) - 1

+    }, {

+      // Mem

+      FixedPcdGet32 (PcdPcieMmio32Base),

+      FixedPcdGet32 (PcdPcieMmio32Base) + FixedPcdGet32 (PcdPcieMmio32Size) - 1

+    }, {

+      // MemAbove4G

+      FixedPcdGet64 (PcdPcieMmio64Base),

+      FixedPcdGet64 (PcdPcieMmio64Base) + FixedPcdGet64 (PcdPcieMmio64Size) - 1

+    }, {

+      // PMem

+      MAX_UINT64,

+      0

+    }, {

+      // PMemAbove4G

+      MAX_UINT64,

+      0

+    },

+    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]

+  },

+};

+

+/**

+  Return all the root bridge instances in an array.

+

+  @param Count  Return the count of root bridge instances.

+

+  @return All the root bridge instances in an array.

+          The array should be passed into PciHostBridgeFreeRootBridges()

+          when it's not used.

+**/

+PCI_ROOT_BRIDGE *

+EFIAPI

+PciHostBridgeGetRootBridges (

+  UINTN *Count

+  )

+{

+  *Count = ARRAY_SIZE (mPciRootBridge);

+  return mPciRootBridge;

+}

+

+/**

+  Free the root bridge instances array returned from PciHostBridgeGetRootBridges().

+

+  @param Bridges The root bridge instances array.

+  @param Count   The count of the array.

+**/

+VOID

+EFIAPI

+PciHostBridgeFreeRootBridges (

+  PCI_ROOT_BRIDGE *Bridges,

+  UINTN           Count

+  )

+{

+}

+

+/**

+  Inform the platform that the resource conflict happens.

+

+  @param HostBridgeHandle Handle of the Host Bridge.

+  @param Configuration    Pointer to PCI I/O and PCI memory resource

+                          descriptors. The Configuration contains the resources

+                          for all the root bridges. The resource for each root

+                          bridge is terminated with END descriptor and an

+                          additional END is appended indicating the end of the

+                          entire resources. The resource descriptor field

+                          values follow the description in

+                          EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL

+                          .SubmitResources().

+**/

+VOID

+EFIAPI

+PciHostBridgeResourceConflict (

+  EFI_HANDLE                        HostBridgeHandle,

+  VOID                              *Configuration

+  )

+{

+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;

+  UINTN                             RootBridgeIndex;

+  DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));

+

+  RootBridgeIndex = 0;

+  Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;

+  while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {

+    DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));

+    for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {

+      ASSERT (Descriptor->ResType <

+              (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /

+               sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])

+               )

+              );

+      DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",

+              mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],

+              Descriptor->AddrLen, Descriptor->AddrRangeMax

+              ));

+      if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {

+        DEBUG ((DEBUG_ERROR, "     Granularity/SpecificFlag = %ld / %02x%s\n",

+                Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,

+                ((Descriptor->SpecificFlag &

+                  EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE

+                  ) != 0) ? L" (Prefetchable)" : L""

+                ));

+      }

+    }

+    //

+    // Skip the END descriptor for root bridge

+    //

+    ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);

+    Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(

+                   (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1

+                   );

+  }

+}

diff --git a/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
new file mode 100644
index 00000000..42d9a77f
--- /dev/null
+++ b/Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -0,0 +1,62 @@
+## @file

+#  PCI Host Bridge Library instance for ARM n1sdp platform.

+#

+#  Copyright (c) 2018, ARM Limited. All rights reserved.

+#

+#  This program and the accompanying materials are licensed and made available

+#  under the terms and conditions of the BSD License which accompanies this

+#  distribution. The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR

+#  IMPLIED.

+#

+##

+

+[Defines]

+  INF_VERSION                    = 0x0001001A

+  BASE_NAME                      = PciHostBridgeLib

+  FILE_GUID                      = 6879CEAD-DC94-42EB-895C-096D36B8083C

+  MODULE_TYPE                    = DXE_DRIVER

+  VERSION_STRING                 = 1.0

+  LIBRARY_CLASS                  = PciHostBridgeLib|DXE_DRIVER

+

+#

+# The following information is for reference only and not required by the build

+# tools.

+#

+#  VALID_ARCHITECTURES           = AARCH64 ARM

+#

+

+[Sources]

+  PciHostBridgeLib.c

+

+[Packages]

+  ArmPkg/ArmPkg.dec

+  MdeModulePkg/MdeModulePkg.dec

+  MdePkg/MdePkg.dec

+  Platform/ARM/N1SdpPkg/N1SdpPlatform.dec

+

+[LibraryClasses]

+  BaseLib

+  DebugLib

+  DevicePathLib

+  IoLib

+  MemoryAllocationLib

+  UefiBootServicesTableLib

+

+[FixedPcd]

+  gArmN1SdpTokenSpaceGuid.PcdPcieBusMin

+  gArmN1SdpTokenSpaceGuid.PcdPcieBusMax

+  gArmN1SdpTokenSpaceGuid.PcdPcieIoBase

+  gArmN1SdpTokenSpaceGuid.PcdPcieIoSize

+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Base

+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Size

+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Base

+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Size

+

+[Protocols]

+  gEfiCpuIo2ProtocolGuid          ## CONSUMES

+

+[Depex]

+  gEfiCpuIo2ProtocolGuid

diff --git a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf
index 9cdfd8e5..1f696b57 100644
--- a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf
+++ b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf
@@ -53,6 +53,16 @@
   gArmTokenSpaceGuid.PcdArmPrimaryCore
   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
 
+  gArmN1SdpTokenSpaceGuid.PcdPcieBusMax
+  gArmN1SdpTokenSpaceGuid.PcdPcieBusMin
+  gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Base
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Size
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Base
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Size
+  gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
+  gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
+
   [Guids]
   gEfiHobListGuid          ## CONSUMES  ## SystemTable
 
diff --git a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c
index f35a27f2..c1a0e70b 100644
--- a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c
@@ -21,7 +21,7 @@
 #include <N1SdpPlatform.h>
 
 // The total number of descriptors, including the final "end-of-table" descriptor.
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
 
 /**
   Returns the Virtual Memory Map of the platform.
@@ -75,6 +75,32 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length          = N1SDP_NON_SECURE_SRAM_SZ;
   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
 
+  // PCIe RC Configuration Space
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet32 (PcdPcieRootPortConfigBaseAddress);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet32 (PcdPcieRootPortConfigBaseAddress);
+  VirtualMemoryTable[Index].Length          = PcdGet32 (PcdPcieRootPortConfigBaseSize);
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // PCIe ECAM Configuration Space
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet32 (PcdPcieExpressBaseAddress);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet32 (PcdPcieExpressBaseAddress);
+  VirtualMemoryTable[Index].Length          = (FixedPcdGet32 (PcdPcieBusMax) -
+                                               FixedPcdGet32 (PcdPcieBusMin) + 1) *
+                                               SIZE_1MB;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // PCIe MMIO32 Memory Space
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet32 (PcdPcieMmio32Base);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet32 (PcdPcieMmio32Base);
+  VirtualMemoryTable[Index].Length          = PcdGet32 (PcdPcieMmio32Size);
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // PCIe MMIO64 Memory Space
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPcieMmio64Base);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPcieMmio64Base);
+  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdPcieMmio64Size);
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
   // OnChip Pheripherals - UART0
   VirtualMemoryTable[++Index].PhysicalBase  = N1SDP_UART0_BASE;
   VirtualMemoryTable[Index].VirtualBase     = N1SDP_UART0_BASE;
diff --git a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec
index af882b54..3a4e747f 100644
--- a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec
+++ b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec
@@ -35,6 +35,27 @@
 [PcdsFixedAtBuild]
   gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
   gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
+  #
+  # PCIe
+  #
+  gArmN1SdpTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000004
+  gArmN1SdpTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005
+  gArmN1SdpTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006
+  gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
+  gArmN1SdpTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000008
+  gArmN1SdpTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x00000009
+  gArmN1SdpTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x0000000A
+  gArmN1SdpTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0x0000000B
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x0000000C
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0x0000000D
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Size|0x04000000|UINT32|0x0000000E
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio32Translation|0x0|UINT32|0x0000000F
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Base|0x0900000000|UINT64|0x00000010
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000011
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000012
+  gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000013
+  gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000014
+  gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000015
 
 [PcdsFeatureFlag.common]
   gArmN1SdpTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000003
diff --git a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc
index 6780bb0f..0632fbce 100755..100644
--- a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc
@@ -75,6 +75,10 @@
 
 [LibraryClasses.common.DXE_DRIVER]
   FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+  PciHostBridgeLib|Platform/ARM/N1SdpPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
 
 [LibraryClasses.common.DXE_RUNTIME_DRIVER]
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
@@ -115,6 +119,12 @@
   gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
 
+  #
+  # PCIe
+  #
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
   ## PL011 - Serial Terminal
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2A400000
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
@@ -232,6 +242,20 @@
   }
 
   #
+  # Required by PCI
+  #
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  #
+  # PCI Support
+  #
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+  }
+
+  #
   # RAM Disk
   #
   MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
diff --git a/Platform/ARM/N1SdpPkg/N1SdpPlatform.fdf b/Platform/ARM/N1SdpPkg/N1SdpPlatform.fdf
index d8e0beed..a086dbdd 100644
--- a/Platform/ARM/N1SdpPkg/N1SdpPlatform.fdf
+++ b/Platform/ARM/N1SdpPkg/N1SdpPlatform.fdf
@@ -107,6 +107,15 @@ READ_LOCK_STATUS   = TRUE
   INF RuleOverride=ACPITABLE Platform/ARM/N1SdpPkg/AcpiTables/N1Sdp/AcpiTables.inf
   INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
 
+  # Required by PCI
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+  #
+  # PCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
   #
   # Multiple Console IO support
   #