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authorManoj Kumar <manoj.kumar3@arm.com>2019-03-26 22:05:44 +0530
committersudipto paul <sudipto.paul@arm.com>2019-03-29 19:18:58 +0000
commit39baed27d104365a6fbd1ba10f28d6745c0b0162 (patch)
tree30841daa4c614ae470b178c013a775a2057ee510
parentcb1e0041274d91bbe7ba0018dc2ca02a8fef9356 (diff)
Platform/ARM/N1sdp: increase system memory size from 2GB to 16GB
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
-rw-r--r--Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf3
-rw-r--r--Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c25
-rw-r--r--Platform/ARM/N1SdpPkg/N1SdpPlatform.dec5
-rw-r--r--Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc8
4 files changed, 37 insertions, 4 deletions
diff --git a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf
index 1f696b57..19254f3d 100644
--- a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf
+++ b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLib.inf
@@ -63,6 +63,9 @@
gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
+ gArmN1SdpTokenSpaceGuid.PcdDramBlock2Base
+ gArmN1SdpTokenSpaceGuid.PcdDramBlock2Size
+
[Guids]
gEfiHobListGuid ## CONSUMES ## SystemTable
diff --git a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c
index c1a0e70b..473cedd4 100644
--- a/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/N1SdpPkg/Library/PlatformLib/PlatformLibMem.c
@@ -21,7 +21,7 @@
#include <N1SdpPlatform.h>
// The total number of descriptors, including the final "end-of-table" descriptor.
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13
/**
Returns the Virtual Memory Map of the platform.
@@ -40,6 +40,21 @@ ArmPlatformGetVirtualMemoryMap (
{
UINTN Index = 0;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+
+ ResourceAttributes =
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FixedPcdGet64 (PcdDramBlock2Base),
+ FixedPcdGet64 (PcdDramBlock2Size));
ASSERT (VirtualMemoryMap != NULL);
Index = 0;
@@ -107,12 +122,18 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = N1SDP_UART0_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
- // DDR - (2GB - 16 MB)
+ // DDR Primary (2GB)
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+ // DDR Secondary (14GB)
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdDramBlock2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
//Expansion Peripherals
VirtualMemoryTable[++Index].PhysicalBase = N1SDP_EXP_PERIPH_BASE;
VirtualMemoryTable[Index].VirtualBase = N1SDP_EXP_PERIPH_BASE;
diff --git a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec
index 3a4e747f..007681cf 100644
--- a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec
+++ b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dec
@@ -56,6 +56,11 @@
gArmN1SdpTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000013
gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000014
gArmN1SdpTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000015
+ #
+ # Secondary DDR memory
+ #
+ gArmN1SdpTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000016
+ gArmN1SdpTokenSpaceGuid.PcdDramBlock2Size|0|UINT64|0x00000017
[PcdsFeatureFlag.common]
gArmN1SdpTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000003
diff --git a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc
index 11e47862..9d4f84e2 100644
--- a/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1SdpPkg/N1SdpPlatform.dsc
@@ -115,9 +115,13 @@
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0
- # System Memory (1GB - 16MB of Trusted DRAM at the top of the 32bit address space)
+ # System Memory (2GB)
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+
+ # Secondary DDR memory (14 GB)
+ gArmN1SdpTokenSpaceGuid.PcdDramBlock2Base|0x8080000000
+ gArmN1SdpTokenSpaceGuid.PcdDramBlock2Size|0x380000000
# GIC Base Addresses
gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000