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Diffstat (limited to 'product/corstone-700/include/firewall.h')
| -rw-r--r-- | product/corstone-700/include/firewall.h | 171 |
1 files changed, 171 insertions, 0 deletions
diff --git a/product/corstone-700/include/firewall.h b/product/corstone-700/include/firewall.h new file mode 100644 index 0000000..eb7aed8 --- /dev/null +++ b/product/corstone-700/include/firewall.h @@ -0,0 +1,171 @@ +/* + * + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef SE_FW_H +#define SE_FW_H + +#include <stdint.h> +#include <se_mmap.h> + +/* + * The Firewall occupies up to 2MB of address space in total. + * Each Firewall Component is allocated 64KB so in total a Firewall + * can have maximum of 32 Components with first component being + * FW controller. + */ +#define FW_TOTAL_SIZE 0x200000 +#define FW_CMP_SIZE 0x10000 +#define MAX_FW_CMP 32 + +/* + * boot processor contains a dedicated Firewall having one FW controller + * and one FW component which allows boot processor access to the Host System address + * space. + */ +#define SE_FCTLR_BASE SE_FIREWALL_BASE +#define SE_FC1_BASE SE_FIREWALL_BASE + FW_CMP_SIZE + +/* + * Common Firewall Registers, present in both Controller and Components. + */ +#define LD_CTRL 0x010 +#define RGN_SCTRL0 0x020 +#define RGN_SCTRL1 0x024 +#define RGN_SCTRL2 0x028 +#define RGN_SCTRL3 0x02C +#define RGN_SCTRL4 0x030 +#define RGN_SCTRL5 0x034 +#define RGN_SCTRL6 0x038 +#define RGN_SCTRL7 0x03C +#define RGN_SST0 0x040 +#define RGN_SST1 0x044 +#define RGN_SST2 0x048 +#define RGN_SST3 0x04C +#define RGN_SST4 0x050 +#define RGN_SST5 0x054 +#define RGN_SST6 0x058 +#define RGN_SST7 0x05C +#define FC_SCTRL 0x060 +#define FC_SST 0x064 +#define PE_CTRL 0x100 +#define PE_ST 0x104 +#define PE_BPS 0x108 +#define RWE_CTRL 0x10C +#define RGN_CTRL0 0x110 +#define RGN_CTRL1 0x114 +#define RGN_LCTRL 0x118 +#define RGN_ST 0x11C +#define RGN_CFG0 0x120 +#define RGN_CFG1 0x124 +#define RGN_SIZE 0x128 +#define RGN_TCFG0 0x130 +#define RGN_TCFG1 0x134 +#define RGN_TCFG2 0x138 +#define RGN_MID0 0x140 +#define RGN_MPL0 0x144 +#define RGN_MID1 0x148 +#define RGN_MPL1 0x14C +#define RGN_MID2 0x150 +#define RGN_MPL2 0x154 +#define RGN_MID3 0x158 +#define RGN_MPL3 0x15C +#define FE_TAL 0x180 +#define FE_TAU 0x184 +#define FE_TP 0x188 +#define FE_MID 0x18C +#define FE_CTRL 0x190 +#define ME_CTRL 0x200 +#define ME_ST 0x204 +#define EDR_TAL 0x260 +#define EDR_TAU 0x264 +#define EDR_TP 0x268 +#define EDR_MID 0x26C +#define EDR_CTRL 0x270 +/* Capability registers */ +#define FC_CAP0 0xFA0 +#define FC_CAP1 0xFA4 +#define FC_CAP2 0xFA8 +#define FC_CAP3 0xFAC +/* Configuration registers */ +#define FC_CFG0 0xFB0 +#define FC_CFG1 0xFB4 +#define FC_CFG2 0xFB8 +#define FC_CFG3 0xFBC + +/* + * Firewall Controller only Registers. + */ +#define FW_CTRL 0x000 +#define FW_ST 0x004 +#define FW_SR_CTRL 0x00C +#define FW_INT_ST 0xD90 +#define FW_TMP_TA 0xE90 +#define FW_TMP_TP 0xE98 +#define FW_TMP_MID 0xE9C +#define FW_TMP_CTRL 0xEA0 +#define IIDR 0xFC8 +#define AIDR 0xFCC +#define FC0_INT_ST 0xD00 +#define FC0_INT_MSK 0xE00 +#define FC_INT_ST(x) FC0_INT_ST+x*4 +#define FC_INT_MSK(x) FC0_INT_MSK+x*4 + +/* + * Generic Macros + */ +#define ENABLE 0x1 +#define DISABLE 0x0 +#define PE_ENABLE ENABLE << 31 +#define ADDR_TRANS_ENABLE ENABLE << 17 +#define RGN_SIZE_4KB 0x0C +#define RGN_SIZE_32MB 0x19 +#define RGN_SIZE_128MB 0x1B + + +/* + * Host access regions view from boot processor + */ +enum se_firewall_regions { + DEFAULT_REGION = 0, + HOST_BIR_REGION, + SHARED_RAM_REGION, + XIP_FLASH_REGION, + HOST_PERIPHERAL_REGION, + DRAM_REGION, + NUM_REGIONS +}; + +/* + * Region Master Permission List + * S: Secure, N: Non-secure + * P: Privileged, U: Unprivileged + * R: Read, W: Write, X: Execute + */ +#define ANY_MST ENABLE << 12 +#define SPX ENABLE << 11 +#define SPW ENABLE << 10 +#define SPR ENABLE << 9 +#define SUX ENABLE << 8 +#define SUW ENABLE << 7 +#define SUR ENABLE << 6 +#define NSPX ENABLE << 5 +#define NSPW ENABLE << 4 +#define NSPR ENABLE << 3 +#define NSUX ENABLE << 2 +#define NSUW ENABLE << 1 +#define NSUR ENABLE << 0 + +/* + * Master Permission Enable + */ +#define MPE3_EN ENABLE << 4 +#define MPE2_EN ENABLE << 3 +#define MPE1_EN ENABLE << 2 +#define MPE0_EN ENABLE << 1 + +#endif /* SE_FW_H */ |