1 files changed, 14 insertions, 14 deletions
diff --git a/Platforms/ARM/Juno/AcpiTables/Madt.aslc b/Platforms/ARM/Juno/AcpiTables/Madt.aslc
index 78531d2..dffa5d6 100644
--- a/Platforms/ARM/Juno/AcpiTables/Madt.aslc
+++ b/Platforms/ARM/Juno/AcpiTables/Madt.aslc
@@ -55,14 +55,14 @@
       //       For now we leave CPU2 (A53-0) at the first position.
       //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
       //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase))  // A57-1
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-0
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-1
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-2
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-3
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A57-0
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase))  // A57-1
     },
-    EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)
+    EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0)
   };
 #else
   #pragma pack (1)
@@ -100,25 +100,25 @@
       //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
       //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0
-          2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1
-          3, 1, GET_MPID(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          3, 1, GET_MPID(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2
-          4, 2, GET_MPID(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          4, 2, GET_MPID(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3
-          5, 3, GET_MPID(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          5, 3, GET_MPID(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0
-          0, 4, GET_MPID(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          0, 4, GET_MPID(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1
-          1, 5, GET_MPID(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          1, 5, GET_MPID(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
     },
-    EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 2),
+    EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 2),
     // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)
     EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)
   };