diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2014-03-24 10:35:35 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-08-11 21:39:26 +0100 |
| commit | fec428515d877aba91e5dbe59883584dc0afffba (patch) | |
| tree | 4df3b5ec3f93ffe5028376679b11d86bc6aa753a /arch/arm64/include/asm/pgtable.h | |
| parent | bd963e5ed978651e0086b898b613aebc181f6b77 (diff) | |
arm64: Remove pgprot_dmacoherent()
Since this macro is identical to pgprot_writecombine() and is only used
in a single place, remove it completely to avoid confusion. On ARMv7+
processors, the coherent DMA mapping must be Normal NonCacheable (a.k.a.
writecombine) to avoid mismatched hardware attribute aliases (with the
kernel linear mapping as Normal Cacheable).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 196adf2f3015eacac0567278ba538e3ffdd16d0e)
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'arch/arm64/include/asm/pgtable.h')
| -rw-r--r-- | arch/arm64/include/asm/pgtable.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 1acb1eedece6..65347e6efb93 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -280,8 +280,6 @@ static inline int has_transparent_hugepage(void) __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) #define pgprot_writecombine(prot) \ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) -#define pgprot_dmacoherent(prot) \ - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) #define __HAVE_PHYS_MEM_ACCESS_PROT struct file; extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, |