1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "k3-pinctrl.h"
&mcasp1 {
status = "disabled";
};
&main_pmx0 {
gpmc0_pins_default: gpmc0-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */
AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (L20) GPMC0_AD2 */
AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (L21) GPMC0_AD3 */
AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (M21) GPMC0_AD4 */
AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (L17) GPMC0_AD5 */
AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (L18) GPMC0_AD6 */
AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (M20) GPMC0_AD7 */
AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (P21) GPMC0_WAIT0 */
AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (J18) GPMC0_CSn0 */
AM62X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (K20) GPMC0_ADVn_ALE */
AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (K21) GPMC0_OEn_REn */
AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (J17) GPMC0_WEn */
AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (K17) GPMC0_BE0n_CLE */
AM62X_IOPAD(0x00a0, PIN_OUTPUT, 0) /* (J20) GPMC0_WPn */
>;
};
};
&elm0 {
status = "okay";
};
&gpmc0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&gpmc0_pins_default>;
#address-cells = <2>;
#size-cells = <1>;
nand@0,0 {
compatible = "ti,am64-nand";
reg = <0 0 64>; /* device IO registers */
interrupt-parent = <&gpmc0>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-xfer-type = "prefetch-polled";
ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
ti,elm-id = <&elm0>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <40>;
gpmc,cs-wr-off-ns = <40>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <25>;
gpmc,adv-wr-off-ns = <25>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <20>;
gpmc,oe-on-ns = <3>;
gpmc,oe-off-ns = <30>;
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.tiboot3";
reg = <0x00000000 0x00200000>; /* 2M */
};
partition@200000 {
label = "NAND.tispl";
reg = <0x00200000 0x00200000>; /* 2M */
};
partition@400000 {
label = "NAND.tiboot3.backup"; /* 2M */
reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
};
partition@600000 {
label = "NAND.u-boot";
reg = <0x00600000 0x00400000>; /* 4M */
};
partition@a00000 {
label = "NAND.u-boot-env";
reg = <0x00a00000 0x00040000>; /* 256K */
};
partition@a40000 {
label = "NAND.u-boot-env.backup";
reg = <0x00a40000 0x00040000>; /* 256K */
};
partition@a80000 {
label = "NAND.file-system";
reg = <0x00a80000 0x3f580000>;
};
};
};
};
|
