diff options
author | Michal Simek <michal.simek@amd.com> | 2024-06-17 08:37:41 +0200 |
---|---|---|
committer | Michal Simek <michal.simek@amd.com> | 2024-06-17 08:37:41 +0200 |
commit | 613af8986db8eefbc018364da62b9f3f9c94ba32 (patch) | |
tree | f43bfecae82c4de813eaff3ec6a1969104ff08b2 | |
parent | a1ebcd60bf4ea7169305821830dac9879a842976 (diff) | |
parent | f9508ef9976e8596f8a1139430ec439691f3337f (diff) |
Merge remote-tracking branch 'git/zynqmp/dt' into for-next
-rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 19 | ||||
-rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 41 | ||||
-rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 19 | ||||
-rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 8 | ||||
-rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 91 |
5 files changed, 156 insertions, 22 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index d7535a77b45e..95d16904d765 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -22,6 +22,17 @@ /plugin/; &{/} { + compatible = "xlnx,zynqmp-sk-kv260-revA", + "xlnx,zynqmp-sk-kv260-revY", + "xlnx,zynqmp-sk-kv260-revZ", + "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; + model = "ZynqMP KV260 revA"; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -68,7 +79,12 @@ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - /* u14 - 0x40 - ina260 */ + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; @@ -321,6 +337,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; conf-cd { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a7b8fffad499..a74d0ac7e07a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -17,6 +17,17 @@ /plugin/; &{/} { + compatible = "xlnx,zynqmp-sk-kv260-rev2", + "xlnx,zynqmp-sk-kv260-rev1", + "xlnx,zynqmp-sk-kv260-revB", + "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; + model = "ZynqMP KV260 revB"; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -52,6 +63,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -63,8 +86,13 @@ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - /* u14 - 0x40 - ina260 */ - /* u43 - 0x2d - usb5744 */ + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + /* u43 - 0x2d - USB hub */ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; @@ -81,6 +109,14 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; &zynqmp_dpdma { @@ -305,6 +341,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; conf-cd { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 51622896b1b1..86e6c4990560 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP SM-K26 rev1/B/A + * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -17,8 +18,9 @@ #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> / { - model = "ZynqMP SM-K26 Rev1/B/A"; - compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", + model = "ZynqMP SM-K26 Rev2/1/B/A"; + compatible = "xlnx,zynqmp-sm-k26-rev2", + "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; @@ -101,12 +103,23 @@ <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; + + pwm-fan { + compatible = "pwm-fan"; + status = "okay"; + pwms = <&ttc0 2 40000 0>; + }; }; &modepin_gpio { label = "modepin"; }; +&ttc0 { + status = "okay"; + #pwm-cells = <3>; +}; + &uart1 { /* MIO36/MIO37 */ status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts index 85b0d1677240..b804abe89d1d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A + * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -10,8 +11,9 @@ #include "zynqmp-sm-k26-revA.dts" / { - model = "ZynqMP SMK-K26 Rev1/B/A"; - compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", + model = "ZynqMP SMK-K26 Rev2/1/B/A"; + compatible = "xlnx,zynqmp-smk-k26-rev2", + "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 95796d6b5515..b1b31dcf6291 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -207,13 +207,71 @@ mbox-names = "tx", "rx"; }; - nvmem-firmware { + soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - soc_revision: soc-revision@0 { - reg = <0x0 0x4>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc-revision@0 { + reg = <0x0 0x4>; + }; + /* efuse access */ + efuse_dna: efuse-dna@c { + reg = <0xc 0xc>; + }; + efuse_usr0: efuse-usr0@20 { + reg = <0x20 0x4>; + }; + efuse_usr1: efuse-usr1@24 { + reg = <0x24 0x4>; + }; + efuse_usr2: efuse-usr2@28 { + reg = <0x28 0x4>; + }; + efuse_usr3: efuse-usr3@2c { + reg = <0x2c 0x4>; + }; + efuse_usr4: efuse-usr4@30 { + reg = <0x30 0x4>; + }; + efuse_usr5: efuse-usr5@34 { + reg = <0x34 0x4>; + }; + efuse_usr6: efuse-usr6@38 { + reg = <0x38 0x4>; + }; + efuse_usr7: efuse-usr7@3c { + reg = <0x3c 0x4>; + }; + efuse_miscusr: efuse-miscusr@40 { + reg = <0x40 0x4>; + }; + efuse_chash: efuse-chash@50 { + reg = <0x50 0x4>; + }; + efuse_pufmisc: efuse-pufmisc@54 { + reg = <0x54 0x4>; + }; + efuse_sec: efuse-sec@58 { + reg = <0x58 0x4>; + }; + efuse_spkid: efuse-spkid@5c { + reg = <0x5c 0x4>; + }; + efuse_aeskey: efuse-aeskey@60 { + reg = <0x60 0x20>; + }; + efuse_ppk0hash: efuse-ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + efuse_ppk1hash: efuse-ppk1hash@d0 { + reg = <0xd0 0x30>; + }; + efuse_pufuser: efuse-pufuser@100 { + reg = <0x100 0x7F>; + }; }; }; @@ -252,7 +310,7 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; - fpga_full: fpga-full { + fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; @@ -769,6 +827,13 @@ power-domains = <&zynqmp_firmware PD_I2C_1>; }; + ocm: memory-controller@ff960000 { + compatible = "xlnx,zynqmp-ocmc-1.0"; + reg = <0x0 0xff960000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; @@ -1026,10 +1091,11 @@ status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "host", "peripheral", "otg"; + interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clock-names = "ref"; /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; @@ -1057,10 +1123,11 @@ status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "host", "peripheral", "otg"; + interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clock-names = "ref"; /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; @@ -1109,8 +1176,6 @@ compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; - #address-cells = <1>; - #size-cells = <0>; }; }; |