diff options
| author | Jimmy Rubin <jimmy.rubin@stericsson.com> | 2010-10-12 14:21:00 +0200 |
|---|---|---|
| committer | Jonas ABERG <jonas.aberg@stericsson.com> | 2010-12-08 08:32:38 +0100 |
| commit | bffb8da32a433b0b67ba8e81194c1ceb81499b3c (patch) | |
| tree | 40110029c9bde0d6dcbd35bc22118b8bf2da156e /drivers/video/mcde/mcde_regs.h | |
| parent | 9fc85f544d2cbf50386df1f5da5848f663104f7c (diff) | |
MCDE: Add maja support
This patch does the following:
* Adds support for maja hw
* Enables HW MEM for Maja
ST Ericsson ID: WP 279382
Change-Id: I21e9841359f06ca00c75d36cbc6a5a29059b0a11
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/9963
Tested-by: Jimmy RUBIN <jimmy.rubin@stericsson.com>
Reviewed-by: Dan JOHANSSON <dan.johansson@stericsson.com>
Diffstat (limited to 'drivers/video/mcde/mcde_regs.h')
| -rw-r--r-- | drivers/video/mcde/mcde_regs.h | 40 |
1 files changed, 28 insertions, 12 deletions
diff --git a/drivers/video/mcde/mcde_regs.h b/drivers/video/mcde/mcde_regs.h index 88f295bd3cc..e9615ebe037 100644 --- a/drivers/video/mcde/mcde_regs.h +++ b/drivers/video/mcde/mcde_regs.h @@ -13,6 +13,14 @@ #define MCDE_CR_DSICMD1_EN_V1_MASK 0x00000002 #define MCDE_CR_DSICMD1_EN_V1(__x) \ MCDE_VAL2REG(MCDE_CR, DSICMD1_EN_V1, __x) +#define MCDE_CR_DSI0_EN_V3_SHIFT 0 +#define MCDE_CR_DSI0_EN_V3_MASK 0x00000001 +#define MCDE_CR_DSI0_EN_V3(__x) \ + MCDE_VAL2REG(MCDE_CR, DSI0_EN_V3, __x) +#define MCDE_CR_DSI1_EN_V3_SHIFT 1 +#define MCDE_CR_DSI1_EN_V3_MASK 0x00000002 +#define MCDE_CR_DSI1_EN_V3(__x) \ + MCDE_VAL2REG(MCDE_CR, DSI1_EN_V3, __x) #define MCDE_CR_DSICMD0_EN_V1_SHIFT 2 #define MCDE_CR_DSICMD0_EN_V1_MASK 0x00000004 #define MCDE_CR_DSICMD0_EN_V1(__x) \ @@ -37,6 +45,10 @@ #define MCDE_CR_DBIC0_EN_V1_MASK 0x00000080 #define MCDE_CR_DBIC0_EN_V1(__x) \ MCDE_VAL2REG(MCDE_CR, DBIC0_EN_V1, __x) +#define MCDE_CR_DBI_EN_V3_SHIFT 7 +#define MCDE_CR_DBI_EN_V3_MASK 0x00000080 +#define MCDE_CR_DBI_EN_V3(__x) \ + MCDE_VAL2REG(MCDE_CR, DBI_EN_V3, __x) #define MCDE_CR_DPIB_EN_V1_SHIFT 8 #define MCDE_CR_DPIB_EN_V1_MASK 0x00000100 #define MCDE_CR_DPIB_EN_V1(__x) \ @@ -45,6 +57,10 @@ #define MCDE_CR_DPIA_EN_V1_MASK 0x00000200 #define MCDE_CR_DPIA_EN_V1(__x) \ MCDE_VAL2REG(MCDE_CR, DPIA_EN_V1, __x) +#define MCDE_CR_DPI_EN_V3_SHIFT 9 +#define MCDE_CR_DPI_EN_V3_MASK 0x00000200 +#define MCDE_CR_DPI_EN_V3(__x) \ + MCDE_VAL2REG(MCDE_CR, DPI_EN_V3, __x) #define MCDE_CR_IFIFOCTRLEN_SHIFT 15 #define MCDE_CR_IFIFOCTRLEN_MASK 0x00008000 #define MCDE_CR_IFIFOCTRLEN(__x) \ @@ -3496,23 +3512,23 @@ MCDE_VAL2REG(MCDE_TVTIM1B, DHO, __x) #define MCDE_TVLBALWA 0x00000850 #define MCDE_TVLBALWA_GROUPOFFSET 0x200 -#define MCDE_TVLBALWA_LBW_SHIFT 0 -#define MCDE_TVLBALWA_LBW_MASK 0x000007FF -#define MCDE_TVLBALWA_LBW(__x) \ - MCDE_VAL2REG(MCDE_TVLBALWA, LBW, __x) -#define MCDE_TVLBALWA_ALW_SHIFT 16 -#define MCDE_TVLBALWA_ALW_MASK 0x07FF0000 +#define MCDE_TVLBALWA_ALW_SHIFT 0 +#define MCDE_TVLBALWA_ALW_MASK 0x000007FF #define MCDE_TVLBALWA_ALW(__x) \ MCDE_VAL2REG(MCDE_TVLBALWA, ALW, __x) +#define MCDE_TVLBALWA_LBW_SHIFT 16 +#define MCDE_TVLBALWA_LBW_MASK 0x07FF0000 +#define MCDE_TVLBALWA_LBW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWA, LBW, __x) #define MCDE_TVLBALWB 0x00000A50 -#define MCDE_TVLBALWB_LBW_SHIFT 0 -#define MCDE_TVLBALWB_LBW_MASK 0x000007FF -#define MCDE_TVLBALWB_LBW(__x) \ - MCDE_VAL2REG(MCDE_TVLBALWB, LBW, __x) -#define MCDE_TVLBALWB_ALW_SHIFT 16 -#define MCDE_TVLBALWB_ALW_MASK 0x07FF0000 +#define MCDE_TVLBALWB_ALW_SHIFT 0 +#define MCDE_TVLBALWB_ALW_MASK 0x000007FF #define MCDE_TVLBALWB_ALW(__x) \ MCDE_VAL2REG(MCDE_TVLBALWB, ALW, __x) +#define MCDE_TVLBALWB_LBW_SHIFT 16 +#define MCDE_TVLBALWB_LBW_MASK 0x07FF0000 +#define MCDE_TVLBALWB_LBW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWB, LBW, __x) #define MCDE_TVBL2A 0x00000854 #define MCDE_TVBL2A_GROUPOFFSET 0x200 #define MCDE_TVBL2A_BEL2_SHIFT 0 |