blob: 82dae1f57e86bf835c9e669bf5d087be38fd1a15 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
|
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _STM32F10X_GPIO_REGISTERS_H_
#define _STM32F10X_GPIO_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
* advanced ARM ® -based 32-bit MCUs
*
* Chapter 9: General-purpose and alternate-function I/Os
* (GPIOs and AFIOs)
*/
/* 9.2 GPIO registers - each GPIO port controls 16 pins */
struct stm32f10x_gpio {
uint32_t crl;
uint32_t crh;
uint32_t idr;
uint32_t odr;
uint32_t bsrr;
uint32_t brr;
uint32_t lckr;
};
/* 9.4.1 AFIO_EVCR */
union __afio_evcr {
uint32_t val;
struct {
uint32_t pin :4 __packed;
uint32_t port :3 __packed;
uint32_t evoe :1 __packed;
uint32_t rsvd__8_31 :24 __packed;
} bit;
};
/* 9.4.2 AFIO_MAPR */
/* TODO: support connectivity line devices */
union __afio_mapr {
uint32_t val;
struct {
uint32_t spi1_remap :1 __packed;
uint32_t i2c1_remap :1 __packed;
uint32_t usart1_remap :1 __packed;
uint32_t usart2_remap :1 __packed;
uint32_t usart3_remap :2 __packed;
uint32_t tim1_remap :2 __packed;
uint32_t tim2_remap :2 __packed;
uint32_t tim3_remap :2 __packed;
uint32_t tim4_remap :1 __packed;
uint32_t can_remap :2 __packed;
uint32_t pd01_remap :1 __packed;
uint32_t tim5ch4_iremap :1 __packed;
uint32_t adc1_etrginj_remap :1 __packed;
uint32_t adc1_etrgreg_remap :1 __packed;
uint32_t adc2_etrginj_remap :1 __packed;
uint32_t adc2_etrgreg_remap :1 __packed;
uint32_t rsvd__21_23 :3 __packed;
uint32_t swj_cfg :3 __packed;
uint32_t rsvd__27_31 :5 __packed;
} bit;
};
/* 9.4.{3,4,5,6} AFIO_EXTICRx */
union __afio_exticr {
uint32_t val;
struct {
uint16_t rsvd__16_31;
uint16_t exti;
} bit;
};
/* 9.4.7 AFIO_MAPR2 */
union __afio_mapr2 {
uint32_t val;
struct {
uint32_t rsvd__0_4 :5 __packed;
uint32_t tim9_remap :1 __packed;
uint32_t tim10_remap :1 __packed;
uint32_t tim11_remap :1 __packed;
uint32_t tim13_remap :1 __packed;
uint32_t tim14_remap :1 __packed;
uint32_t fsmc_nadv :1 __packed;
uint32_t rsvd__11_31 :21 __packed;
} bit;
};
/* 9.4 AFIO registers */
struct stm32f10x_afio {
union __afio_evcr evcr;
union __afio_mapr mapr;
union __afio_exticr exticr1;
union __afio_exticr exticr2;
union __afio_exticr exticr3;
union __afio_exticr exticr4;
union __afio_mapr2 mapr2;
};
#endif /* _STM32F10X_GPIO_REGISTERS_H_ */
|
