summaryrefslogtreecommitdiff
path: root/arch/arm/soc/st_stm32/stm32f1/flash_registers.h
blob: 276e23e70c469ea5f2fc9ab953f21f3926b7a8f9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
/*
 * Copyright (c) 2016 Open-RnD Sp. z o.o.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef _STM32F10X_FLASH_REGISTERS_H_
#define _STM32F10X_FLASH_REGISTERS_H_

/**
 * @brief
 *
 * Based on reference manual:
 *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
 *   advanced ARM ® -based 32-bit MCUs
 *
 * Chapter 3.3.3: Embedded Flash Memory
 */

enum {
	STM32F10X_FLASH_LATENCY_0 = 0x0,
	STM32F10X_FLASH_LATENCY_1 = 0x1,
	STM32F10X_FLASH_LATENCY_2 = 0x2,
};

/* 3.3.3 FLASH_ACR */
union __ef_acr {
	uint32_t val;
	struct {
		uint32_t latency :3 __packed;
		uint32_t hlfcya :1 __packed;
		uint32_t prftbe :1 __packed;
		uint32_t prftbs :1 __packed;
		uint32_t rsvd__6_31 :26 __packed;
	} bit;
};

/* 3.3.3 Embedded flash registers */
struct stm32f10x_flash {
	union __ef_acr acr;
	uint32_t keyr;
	uint32_t optkeyr;
	uint32_t sr;
	uint32_t cr;
	uint32_t ar;
	uint32_t rsvd;
	uint32_t obr;
	uint32_t wrpr;
};

#endif	/* _STM32F10X_FLASHREGISTERS_H_ */