From ef8200dfcd5d86683f7ed1af0f83559099791b05 Mon Sep 17 00:00:00 2001 From: Marcus Shawcroft Date: Sat, 31 Dec 2016 13:21:43 +0000 Subject: arm: Replace CONFIG_CPU_CORTEX_M3_M4 with CONFIG_ARMV7_M Precursor patches have arranged that conditional compilation hanging on CONFIG_CPU_CORTEX_M3_M4 provides support for ARMv7-M, rename the config variable to reflect this. Change-Id: Ifa56e3c1c04505d061b2af3aec9d8b9e55b5853d Signed-off-by: Marcus Shawcroft --- arch/arm/core/cortex_m/Kconfig | 10 +++++----- arch/arm/core/cortex_m/reset.S | 2 +- arch/arm/core/cortex_m/scb.c | 2 +- arch/arm/core/cortex_m/vector_table.S | 2 +- arch/arm/core/cortex_m/vector_table.h | 2 +- arch/arm/core/cpu_idle.S | 4 ++-- arch/arm/core/fault.c | 10 +++++----- arch/arm/core/fault_s.S | 6 +++--- arch/arm/core/isr_wrapper.S | 6 +++--- arch/arm/core/swap.S | 12 ++++++------ arch/arm/include/cortex_m/exc.h | 2 +- arch/arm/include/kernel_arch_func.h | 2 +- 12 files changed, 30 insertions(+), 30 deletions(-) (limited to 'arch') diff --git a/arch/arm/core/cortex_m/Kconfig b/arch/arm/core/cortex_m/Kconfig index 6278b7939..eaff1e52f 100644 --- a/arch/arm/core/cortex_m/Kconfig +++ b/arch/arm/core/cortex_m/Kconfig @@ -69,7 +69,7 @@ config ARMV6_M help This option signifies the use of an ARMv6-M processor implementation. -config CPU_CORTEX_M3_M4 +config ARMV7_M bool # Omit prompt to signify "hidden" option default n @@ -78,7 +78,7 @@ config CPU_CORTEX_M3_M4 select CPU_CORTEX_M_HAS_BASEPRI select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS help - This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU. + This option signifies the use of an ARMv7-M processor implementation. config CPU_CORTEX_M0 bool @@ -97,14 +97,14 @@ config CPU_CORTEX_M0PLUS config CPU_CORTEX_M3 bool # Omit prompt to signify "hidden" option - select CPU_CORTEX_M3_M4 + select ARMV7_M help This option signifies the use of a Cortex-M3 CPU config CPU_CORTEX_M4 bool # Omit prompt to signify "hidden" option - select CPU_CORTEX_M3_M4 + select ARMV7_M help This option signifies the use of a Cortex-M4 CPU @@ -211,7 +211,7 @@ config FLASH_BASE_ADDRESS endmenu menu "ARM Cortex-M0/M0+/M3/M4/M7 options" - depends on ARMV6_M || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7 + depends on ARMV6_M || ARMV7_M || CPU_CORTEX_M7 config IRQ_OFFLOAD bool "Enable IRQ offload" diff --git a/arch/arm/core/cortex_m/reset.S b/arch/arm/core/cortex_m/reset.S index 7108527c0..5f1ccd395 100644 --- a/arch/arm/core/cortex_m/reset.S +++ b/arch/arm/core/cortex_m/reset.S @@ -74,7 +74,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) /* lock interrupts: will get unlocked when switch to main task */ #if defined(CONFIG_ARMV6_M) cpsid i -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) movs.n r0, #_EXC_IRQ_DEFAULT_PRIO msr BASEPRI, r0 #else diff --git a/arch/arm/core/cortex_m/scb.c b/arch/arm/core/cortex_m/scb.c index 4e4f49417..09c139acb 100644 --- a/arch/arm/core/cortex_m/scb.c +++ b/arch/arm/core/cortex_m/scb.c @@ -91,7 +91,7 @@ void sys_arch_reboot(int type) } #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) /** * * @brief Set the number of priority groups based on the number of exception diff --git a/arch/arm/core/cortex_m/vector_table.S b/arch/arm/core/cortex_m/vector_table.S index 07193f95a..74c0f0f5d 100644 --- a/arch/arm/core/cortex_m/vector_table.S +++ b/arch/arm/core/cortex_m/vector_table.S @@ -66,7 +66,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start) .word __reserved .word __reserved /* SVC not used for now (PendSV used instead) */ .word __reserved -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) .word __mpu_fault .word __bus_fault .word __usage_fault diff --git a/arch/arm/core/cortex_m/vector_table.h b/arch/arm/core/cortex_m/vector_table.h index f9f7f4e0b..c7ad63b73 100644 --- a/arch/arm/core/cortex_m/vector_table.h +++ b/arch/arm/core/cortex_m/vector_table.h @@ -49,7 +49,7 @@ GTEXT(__reset) GTEXT(__nmi) GTEXT(__hard_fault) #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) GTEXT(__mpu_fault) GTEXT(__bus_fault) GTEXT(__usage_fault) diff --git a/arch/arm/core/cpu_idle.S b/arch/arm/core/cpu_idle.S index 0b4fa6184..7bb7fc5de 100644 --- a/arch/arm/core/cpu_idle.S +++ b/arch/arm/core/cpu_idle.S @@ -129,7 +129,7 @@ SECTION_FUNC(TEXT, k_cpu_idle) #if defined(CONFIG_ARMV6_M) cpsie i -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) /* clear BASEPRI so wfi is awakened by incoming interrupts */ eors.n r0, r0 msr BASEPRI, r0 @@ -193,7 +193,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle) cpsie i _irq_disabled: -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) /* r1: zero, for setting BASEPRI (needs a register) */ eors.n r1, r1 diff --git a/arch/arm/core/fault.c b/arch/arm/core/fault.c index 44e225d09..9586621c5 100644 --- a/arch/arm/core/fault.c +++ b/arch/arm/core/fault.c @@ -70,7 +70,7 @@ void _FaultDump(const NANO_ESF *esf, int fault) esf->pc); #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) int escalation = 0; if (3 == fault) { /* hard fault */ @@ -124,7 +124,7 @@ static void _FaultThreadShow(const NANO_ESF *esf) } #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) /** * @@ -266,7 +266,7 @@ static void _HardFault(const NANO_ESF *esf) #if defined(CONFIG_ARMV6_M) _FaultThreadShow(esf); -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) if (_ScbHardFaultIsBusErrOnVectorRead()) { PR_EXC(" Bus fault on vector table read\n"); } else if (_ScbHardFaultIsForced()) { @@ -327,7 +327,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault) _HardFault(esf); break; #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) case 4: _MpuFault(esf, 0); break; @@ -388,7 +388,7 @@ void _Fault(const NANO_ESF *esf) void _FaultInit(void) { #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) _ScbDivByZeroFaultEnable(); #else #error Unknown ARM architecture diff --git a/arch/arm/core/fault_s.S b/arch/arm/core/fault_s.S index ca5286fab..6a31ca939 100644 --- a/arch/arm/core/fault_s.S +++ b/arch/arm/core/fault_s.S @@ -33,7 +33,7 @@ GTEXT(_Fault) GTEXT(__hard_fault) #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) GTEXT(__mpu_fault) GTEXT(__bus_fault) GTEXT(__usage_fault) @@ -68,7 +68,7 @@ GTEXT(__reserved) SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault) #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault) SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault) SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault) @@ -95,7 +95,7 @@ _stack_frame_msp: mrs r0, MSP _stack_frame_endif: -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) /* force unlock interrupts */ eors.n r0, r0 msr BASEPRI, r0 diff --git a/arch/arm/core/isr_wrapper.S b/arch/arm/core/isr_wrapper.S index 9e722ea38..a93d91355 100644 --- a/arch/arm/core/isr_wrapper.S +++ b/arch/arm/core/isr_wrapper.S @@ -88,7 +88,7 @@ SECTION_FUNC(TEXT, _isr_wrapper) blx _sys_power_save_idle_exit _idle_state_cleared: -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) ittt ne movne r1, #0 /* clear kernel idle state */ @@ -106,7 +106,7 @@ _idle_state_cleared: ldr r1, =16 subs r0, r1 /* get IRQ number */ lsls r0, #3 /* table is 8-byte wide */ -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) sub r0, r0, #16 /* get IRQ number */ lsl r0, r0, #3 /* table is 8-byte wide */ #else @@ -122,7 +122,7 @@ _idle_state_cleared: #if defined(CONFIG_ARMV6_M) pop {r3} mov lr, r3 -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) pop {lr} #else #error Unknown ARM architecture diff --git a/arch/arm/core/swap.S b/arch/arm/core/swap.S index 6beee6032..64f487cc0 100644 --- a/arch/arm/core/swap.S +++ b/arch/arm/core/swap.S @@ -33,7 +33,7 @@ _ASM_FILE_PROLOGUE GTEXT(_Swap) #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) GTEXT(__svc) #else #error Unknown ARM architecture @@ -88,7 +88,7 @@ SECTION_FUNC(TEXT, __pendsv) mov r7, ip /* store r8-12 */ stmea r0!, {r3-r7} -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) stmia r0, {v1-v8, ip} #ifdef CONFIG_FP_SHARING add r0, r2, #_thread_offset_to_preempt_float @@ -111,7 +111,7 @@ SECTION_FUNC(TEXT, __pendsv) /* protect the kernel state while we play with the thread lists */ #if defined(CONFIG_ARMV6_M) cpsid i -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) movs.n r0, #_EXC_IRQ_DEFAULT_PRIO msr BASEPRI, r0 #else @@ -170,7 +170,7 @@ _thread_irq_disabled: /* restore r4-r7, go back 9*4 bytes to the start of the stored block */ subs r0, #36 ldmia r0!, {r4-r7} -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) /* restore BASEPRI for the incoming thread */ msr BASEPRI, r0 @@ -192,7 +192,7 @@ _thread_irq_disabled: bx lr #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) /** * * @brief Service call handler @@ -316,7 +316,7 @@ SECTION_FUNC(TEXT, _Swap) * of a higher priority pending. */ cpsie i -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) svc #0 #else #error Unknown ARM architecture diff --git a/arch/arm/include/cortex_m/exc.h b/arch/arm/include/cortex_m/exc.h index 16bbe635e..d809900dc 100644 --- a/arch/arm/include/cortex_m/exc.h +++ b/arch/arm/include/cortex_m/exc.h @@ -60,7 +60,7 @@ static ALWAYS_INLINE int _IsInIsr(void) */ #if defined(CONFIG_ARMV6_M) return (vector > 10) || (vector == 3); -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) return (vector > 10) || (vector && _ScbIsNestedExc()); #else #error Unknown ARM architecture diff --git a/arch/arm/include/kernel_arch_func.h b/arch/arm/include/kernel_arch_func.h index 82fc383a8..fd9c81ae2 100644 --- a/arch/arm/include/kernel_arch_func.h +++ b/arch/arm/include/kernel_arch_func.h @@ -69,7 +69,7 @@ _arch_switch_to_main_thread(char *main_stack, size_t main_stack_size, /* unlock interrupts */ #ifdef CONFIG_ARMV6_M "cpsie i \t\n" -#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) "movs %%r1, #0 \n\t" "msr BASEPRI, %%r1 \n\t" #else -- cgit v1.2.3