From 84cb997c62af43b99836daf3043894573b26782d Mon Sep 17 00:00:00 2001 From: Marcus Shawcroft Date: Sat, 31 Dec 2016 14:41:19 +0000 Subject: arm: Adjust cortex-m7 support to reflect its ARMv7-M architecture. The cortex-m7 is an implementation of armv7-m. Adjust the Kconfig support for cortex-m7 to reflect this and drop the unnecessary, explicit, conditional compilation. Change-Id: I6ec20e69c8c83c5a80b1f714506f7f9e295b15d5 Signed-off-by: Marcus Shawcroft --- arch/arm/core/cortex_m/Kconfig | 7 ++----- arch/arm/core/cortex_m/reset.S | 2 +- arch/arm/core/cortex_m/scb.c | 2 +- arch/arm/core/cortex_m/vector_table.S | 2 +- arch/arm/core/cortex_m/vector_table.h | 2 +- arch/arm/core/cpu_idle.S | 4 ++-- arch/arm/core/fault.c | 10 +++++----- arch/arm/core/fault_s.S | 6 +++--- arch/arm/core/isr_wrapper.S | 6 +++--- arch/arm/core/swap.S | 12 ++++++------ arch/arm/include/cortex_m/exc.h | 2 +- arch/arm/include/kernel_arch_func.h | 2 +- 12 files changed, 27 insertions(+), 30 deletions(-) (limited to 'arch') diff --git a/arch/arm/core/cortex_m/Kconfig b/arch/arm/core/cortex_m/Kconfig index eaff1e52f..dc35cad40 100644 --- a/arch/arm/core/cortex_m/Kconfig +++ b/arch/arm/core/cortex_m/Kconfig @@ -111,11 +111,8 @@ config CPU_CORTEX_M4 config CPU_CORTEX_M7 bool # Omit prompt to signify "hidden" option + select ARMV7_M default n - select ATOMIC_OPERATIONS_BUILTIN - select ISA_THUMB2 - select CPU_CORTEX_M_HAS_BASEPRI - select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS help This option signifies the use of a Cortex-M7 CPU @@ -211,7 +208,7 @@ config FLASH_BASE_ADDRESS endmenu menu "ARM Cortex-M0/M0+/M3/M4/M7 options" - depends on ARMV6_M || ARMV7_M || CPU_CORTEX_M7 + depends on ARMV6_M || ARMV7_M config IRQ_OFFLOAD bool "Enable IRQ offload" diff --git a/arch/arm/core/cortex_m/reset.S b/arch/arm/core/cortex_m/reset.S index 5f1ccd395..d69f3d086 100644 --- a/arch/arm/core/cortex_m/reset.S +++ b/arch/arm/core/cortex_m/reset.S @@ -74,7 +74,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) /* lock interrupts: will get unlocked when switch to main task */ #if defined(CONFIG_ARMV6_M) cpsid i -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) movs.n r0, #_EXC_IRQ_DEFAULT_PRIO msr BASEPRI, r0 #else diff --git a/arch/arm/core/cortex_m/scb.c b/arch/arm/core/cortex_m/scb.c index 09c139acb..0e23d3a4c 100644 --- a/arch/arm/core/cortex_m/scb.c +++ b/arch/arm/core/cortex_m/scb.c @@ -91,7 +91,7 @@ void sys_arch_reboot(int type) } #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) /** * * @brief Set the number of priority groups based on the number of exception diff --git a/arch/arm/core/cortex_m/vector_table.S b/arch/arm/core/cortex_m/vector_table.S index 74c0f0f5d..ceff57798 100644 --- a/arch/arm/core/cortex_m/vector_table.S +++ b/arch/arm/core/cortex_m/vector_table.S @@ -66,7 +66,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start) .word __reserved .word __reserved /* SVC not used for now (PendSV used instead) */ .word __reserved -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) .word __mpu_fault .word __bus_fault .word __usage_fault diff --git a/arch/arm/core/cortex_m/vector_table.h b/arch/arm/core/cortex_m/vector_table.h index c7ad63b73..a8857e1ed 100644 --- a/arch/arm/core/cortex_m/vector_table.h +++ b/arch/arm/core/cortex_m/vector_table.h @@ -49,7 +49,7 @@ GTEXT(__reset) GTEXT(__nmi) GTEXT(__hard_fault) #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) GTEXT(__mpu_fault) GTEXT(__bus_fault) GTEXT(__usage_fault) diff --git a/arch/arm/core/cpu_idle.S b/arch/arm/core/cpu_idle.S index 7bb7fc5de..7f78e3049 100644 --- a/arch/arm/core/cpu_idle.S +++ b/arch/arm/core/cpu_idle.S @@ -129,7 +129,7 @@ SECTION_FUNC(TEXT, k_cpu_idle) #if defined(CONFIG_ARMV6_M) cpsie i -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) /* clear BASEPRI so wfi is awakened by incoming interrupts */ eors.n r0, r0 msr BASEPRI, r0 @@ -193,7 +193,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle) cpsie i _irq_disabled: -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) /* r1: zero, for setting BASEPRI (needs a register) */ eors.n r1, r1 diff --git a/arch/arm/core/fault.c b/arch/arm/core/fault.c index 9586621c5..b5d60d7fb 100644 --- a/arch/arm/core/fault.c +++ b/arch/arm/core/fault.c @@ -70,7 +70,7 @@ void _FaultDump(const NANO_ESF *esf, int fault) esf->pc); #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) int escalation = 0; if (3 == fault) { /* hard fault */ @@ -124,7 +124,7 @@ static void _FaultThreadShow(const NANO_ESF *esf) } #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) /** * @@ -266,7 +266,7 @@ static void _HardFault(const NANO_ESF *esf) #if defined(CONFIG_ARMV6_M) _FaultThreadShow(esf); -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) if (_ScbHardFaultIsBusErrOnVectorRead()) { PR_EXC(" Bus fault on vector table read\n"); } else if (_ScbHardFaultIsForced()) { @@ -327,7 +327,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault) _HardFault(esf); break; #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) case 4: _MpuFault(esf, 0); break; @@ -388,7 +388,7 @@ void _Fault(const NANO_ESF *esf) void _FaultInit(void) { #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) _ScbDivByZeroFaultEnable(); #else #error Unknown ARM architecture diff --git a/arch/arm/core/fault_s.S b/arch/arm/core/fault_s.S index 6a31ca939..cdf064aa5 100644 --- a/arch/arm/core/fault_s.S +++ b/arch/arm/core/fault_s.S @@ -33,7 +33,7 @@ GTEXT(_Fault) GTEXT(__hard_fault) #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) GTEXT(__mpu_fault) GTEXT(__bus_fault) GTEXT(__usage_fault) @@ -68,7 +68,7 @@ GTEXT(__reserved) SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault) #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault) SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault) SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault) @@ -95,7 +95,7 @@ _stack_frame_msp: mrs r0, MSP _stack_frame_endif: -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) /* force unlock interrupts */ eors.n r0, r0 msr BASEPRI, r0 diff --git a/arch/arm/core/isr_wrapper.S b/arch/arm/core/isr_wrapper.S index a93d91355..4eee9fb43 100644 --- a/arch/arm/core/isr_wrapper.S +++ b/arch/arm/core/isr_wrapper.S @@ -88,7 +88,7 @@ SECTION_FUNC(TEXT, _isr_wrapper) blx _sys_power_save_idle_exit _idle_state_cleared: -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) ittt ne movne r1, #0 /* clear kernel idle state */ @@ -106,7 +106,7 @@ _idle_state_cleared: ldr r1, =16 subs r0, r1 /* get IRQ number */ lsls r0, #3 /* table is 8-byte wide */ -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) sub r0, r0, #16 /* get IRQ number */ lsl r0, r0, #3 /* table is 8-byte wide */ #else @@ -122,7 +122,7 @@ _idle_state_cleared: #if defined(CONFIG_ARMV6_M) pop {r3} mov lr, r3 -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) pop {lr} #else #error Unknown ARM architecture diff --git a/arch/arm/core/swap.S b/arch/arm/core/swap.S index 64f487cc0..93f18e0f2 100644 --- a/arch/arm/core/swap.S +++ b/arch/arm/core/swap.S @@ -33,7 +33,7 @@ _ASM_FILE_PROLOGUE GTEXT(_Swap) #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) GTEXT(__svc) #else #error Unknown ARM architecture @@ -88,7 +88,7 @@ SECTION_FUNC(TEXT, __pendsv) mov r7, ip /* store r8-12 */ stmea r0!, {r3-r7} -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) stmia r0, {v1-v8, ip} #ifdef CONFIG_FP_SHARING add r0, r2, #_thread_offset_to_preempt_float @@ -111,7 +111,7 @@ SECTION_FUNC(TEXT, __pendsv) /* protect the kernel state while we play with the thread lists */ #if defined(CONFIG_ARMV6_M) cpsid i -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) movs.n r0, #_EXC_IRQ_DEFAULT_PRIO msr BASEPRI, r0 #else @@ -170,7 +170,7 @@ _thread_irq_disabled: /* restore r4-r7, go back 9*4 bytes to the start of the stored block */ subs r0, #36 ldmia r0!, {r4-r7} -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) /* restore BASEPRI for the incoming thread */ msr BASEPRI, r0 @@ -192,7 +192,7 @@ _thread_irq_disabled: bx lr #if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) /** * * @brief Service call handler @@ -316,7 +316,7 @@ SECTION_FUNC(TEXT, _Swap) * of a higher priority pending. */ cpsie i -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) svc #0 #else #error Unknown ARM architecture diff --git a/arch/arm/include/cortex_m/exc.h b/arch/arm/include/cortex_m/exc.h index d809900dc..5d030aeb7 100644 --- a/arch/arm/include/cortex_m/exc.h +++ b/arch/arm/include/cortex_m/exc.h @@ -60,7 +60,7 @@ static ALWAYS_INLINE int _IsInIsr(void) */ #if defined(CONFIG_ARMV6_M) return (vector > 10) || (vector == 3); -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) return (vector > 10) || (vector && _ScbIsNestedExc()); #else #error Unknown ARM architecture diff --git a/arch/arm/include/kernel_arch_func.h b/arch/arm/include/kernel_arch_func.h index fd9c81ae2..965c6eb0a 100644 --- a/arch/arm/include/kernel_arch_func.h +++ b/arch/arm/include/kernel_arch_func.h @@ -69,7 +69,7 @@ _arch_switch_to_main_thread(char *main_stack, size_t main_stack_size, /* unlock interrupts */ #ifdef CONFIG_ARMV6_M "cpsie i \t\n" -#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7) +#elif defined(CONFIG_ARMV7_M) "movs %%r1, #0 \n\t" "msr BASEPRI, %%r1 \n\t" #else -- cgit v1.2.3