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Lets not confuse user with this code, it is clearly not a sample.
Change-Id: I3a0209fb34b2c97383b0f5382f156b80470fdaf7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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Ensure that we catch all fatal faults and report them as such (we were
only catching the ones in fibers).
Change-Id: Id734cdd02f4950d19717467a212032433a7dcc61
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
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This board now has an official name and will be available soon:
http://www.intel.com/content/www/us/en/embedded/products/quark/mcu/se-soc/overview.html
Jira: ZEP-758
Change-Id: Ia16d33722308cf81471321c3063bdc75055a4d50
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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Fix "TCF: especify ARCH when building" missed feeding ARCH to the
initconfig phase, that some projects require.
Change-Id: Ie44c9056d2d44198abbac6aeb6e0df05aff4dc36
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
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By default TCF was running test single core test cases in both Quark
SE cores at the same time.
This worked because the ARC output came through the IPM console to
x86, which enabled them to coexist.
However, after default configuration changes, this is no longer
possible without adding extra hardware to the current test setup,
which is cost prohibitive, and thus we are driving ARC output to the
same port as the x86 output.
This would make the output single-core test cases that are ran at the
same time in the x86 and ARC cores mix their outputs.
So we have that scenario disabled (and makes us run less test
cases). However, multicore test cases still can be run by selecting:
@targets bsp_model:x86+arc
Change-Id: I5f6b43246a24d0b263fd4a47866c7f0f99d20505
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
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The current code redirects the ARC output to UART0.
Our test setup is laid out with a single serial port (which is mostly
UART1). For simplicity (as the extra cabling would be prohibitive), we
will change the default test building to redirect output back to ARC1.
This implies that the output from test cases will be intermixed when
test cases are not prepared to share the serial port, so running of
testcases combined in x86+arc will have to be disabled by default and
only done in testcases which declare they need to do so.
Change-Id: I5a6b79ecb48ecfb2d711be7f5fdbe08b4c3d34e9
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
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Currently it plucks configuration strings in/out of the $O/.config and
that is quite dirty.
There is a cleaner way to do that with configuration fragments which
is now enabled by being able to include them from the object
directory.
Change-Id: Id51881391293ace89b58153c5de7db1afe67118a
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
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Some test cases and samples require ARCH being specified. In TCF, that
information is carried by the BSP variable.
This is a workaround hack to a historical carry over that should be
removed once the extra work to do so is completed (ZEP-754). Tagged as
such.
Change-Id: I640efce3e65f46473443c5413807cdc7cdfd8be8
Jira: ZEP-760
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
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This introduces the default language to use for building, deploying
and evaluating testcases on real hardware in the automation framework.
To be able to filter testcases out based on .config values, we split
the build process into generating the configuration file, filtering
and then the actual building.
The configuration step is done first, to be able to skip as soon
as possible.
This file is in the top level as the test runner will look for
defaults in parent directories.
Note that the default's entry in tests/.tcdefaults takes advantage of
the fact that all:
- the test cases under tests/ print standarized strings for success
or failure.
- the tc_util.h kernel header will print the passed runid if specified
when finalizing the testcase. We will make sure it is found to deem
the TC succesful, ensuring that the right image is flashed and
verified.
Change-Id: If40b226aef9583f7ce4064405d9334de379f2b00
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
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