diff options
| author | Marcus Shawcroft <marcus.shawcroft@arm.com> | 2017-01-24 10:56:39 +0000 |
|---|---|---|
| committer | Marcus Shawcroft <marcus.shawcroft@arm.com> | 2017-01-25 08:47:22 +0000 |
| commit | cf94f6144d31f5de1bdb2d5ef40bb45bde031f29 (patch) | |
| tree | 04ce6468abcd2d71ec34788c188da4252ab2964d /arch | |
| parent | 8324e938128c20b35856d80f8455aa4d7878ce3f (diff) | |
gpio/stm32: Move from the OPEN_DRAIN interface to the DRIVE_STRENGTH interface
The STM32 GPIO driver extended the generic GPIO driver interace with
the concept of OPEN_DRAIN. There is previous discussion about
representing such concepts in the GPIO interface in a more general
fashion here:
https://lists.zephyrproject.org/archives/list/devel@lists.zephyrproject.org/thread/6DCFUAKCOOOBHUO3ZK45ES6IQXOEOFWN/
The DRIVE STRENGTH interface supports the concepts of OPEN DRAIN and
other variants supports by other vendors hardware.
Adjust the STM32 GPIO driver to use the DRIVE STRENGTH interface. A
following patch will address the simplication of gpio.h
Change-Id: I56b0792ec2b21f1adc673dff019288dc8573d005
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/soc/st_stm32/stm32f3/soc_gpio.c | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/arch/arm/soc/st_stm32/stm32f3/soc_gpio.c b/arch/arm/soc/st_stm32/stm32f3/soc_gpio.c index 2c9cbde17..a30205c9c 100644 --- a/arch/arm/soc/st_stm32/stm32f3/soc_gpio.c +++ b/arch/arm/soc/st_stm32/stm32f3/soc_gpio.c @@ -58,21 +58,25 @@ int stm32_gpio_flags_to_conf(int flags, int *pincfg) int pud = flags & GPIO_PUD_MASK; if (direction == GPIO_DIR_OUT) { - int type = flags & GPIO_PP_OD_MASK; + int type = flags & GPIO_DS_HIGH_MASK; - if (type == GPIO_PUSH_PULL) { - *pincfg = STM32F3X_PIN_CONFIG_DRIVE_PUSH_PULL; + if (type == GPIO_DS_DISCONNECT_HIGH) { + *pincfg = STM32F3X_PIN_CONFIG_DRIVE_OPEN_DRAIN; if (pud == GPIO_PUD_PULL_UP) { - *pincfg = STM32F3X_PIN_CONFIG_DRIVE_PUSH_PULL_PU; + *pincfg = + STM32F3X_PIN_CONFIG_DRIVE_OPEN_DRAIN_PU; } else if (pud == GPIO_PUD_PULL_DOWN) { - *pincfg = STM32F3X_PIN_CONFIG_DRIVE_PUSH_PULL_PD; + *pincfg = + STM32F3X_PIN_CONFIG_DRIVE_OPEN_DRAIN_PD; } - } else if (type == GPIO_OPEN_DRAIN) { - *pincfg = STM32F3X_PIN_CONFIG_DRIVE_OPEN_DRAIN; + } else { + *pincfg = STM32F3X_PIN_CONFIG_DRIVE_PUSH_PULL; if (pud == GPIO_PUD_PULL_UP) { - *pincfg = STM32F3X_PIN_CONFIG_DRIVE_OPEN_DRAIN_PU; + *pincfg = + STM32F3X_PIN_CONFIG_DRIVE_PUSH_PULL_PU; } else if (pud == GPIO_PUD_PULL_DOWN) { - *pincfg = STM32F3X_PIN_CONFIG_DRIVE_OPEN_DRAIN_PD; + *pincfg = + STM32F3X_PIN_CONFIG_DRIVE_PUSH_PULL_PD; } } } else if (direction == GPIO_DIR_IN) { |