diff options
| author | Steven Kinney <steven.kinney@linaro.org> | 2013-11-21 10:30:53 -0600 |
|---|---|---|
| committer | Steven Kinney <steven.kinney@linaro.org> | 2013-11-21 10:30:53 -0600 |
| commit | 6893e05f1b8d2598415bc47e253f04b7bb10f884 (patch) | |
| tree | 255b9e0f847c06fba8d0544f23bd438a3f7f9d81 | |
| parent | bc803f26a04ae18ed0b5831fc4cf7497b96645ba (diff) | |
| parent | b94fabd981aa2437a8e2e1d41b4d8645bf62ca21 (diff) | |
Merge branch 'linaro-topic-upstream' into linaro-tracking-2013.11linaro-uefi-2013.11-rc4
| -rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicDxe.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c index ce96831a42..45a52be1c7 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c @@ -378,12 +378,12 @@ InterruptDxeInitialize ( CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
- // cannot be 0.
- ASSERT (CpuTarget != 0);
-
- // The 8 first Interrupt Processor Targets Registers are read-only
- for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
- MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
+ // is 0 when we run on a uniprocessor platform. + if (CpuTarget != 0) { + // The 8 first Interrupt Processor Targets Registers are read-only + for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) { + MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget); + } }
// Set binary point reg to 0x7 (no preemption)
|