##
#  Copyright (c) 2013, AppliedMicro Corp. All rights reserved.
#
#  This program and the accompanying materials
#  are licensed and made available under the terms and conditions of the BSD License
#  which accompanies this distribution.  The full text of the license may be found at
#  http://opensource.org/licenses/bsd-license.php
#
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##

[Defines]
  DEC_SPECIFICATION              = 0x00010005
  PACKAGE_NAME                   = APMXGenePkg
  PACKAGE_GUID                   = 84139d17-9469-44ca-980a-bff540e792b3
  PACKAGE_VERSION                = 0.1

################################################################################
#
# Include Section - list of Include Paths that are provided by this package.
#                   Comments are used for Keywords and Module Types.
#
# Supported Module Types:
#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
################################################################################
[Includes.common]
  Include                        # Root include for the package

[Guids.common]
  gArmPlatformTokenSpaceGuid   = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
  #
  # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
  #
  gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }

  ## Include/Guid/ArmGlobalVariableHob.h
  gArmGlobalVariableGuid      = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }

[Ppis]
  ## Include/Ppi/ArmGlobalVariable.h
  gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }

[PcdsFeatureFlag.common]
  # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|TRUE|BOOLEAN|0x00000012

  gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE|BOOLEAN|0x00000002
  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004

  gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C
  #PCIE
  gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeResetGpio|FALSE|BOOLEAN|0x00000076

[PcdsFixedAtBuild.common]
  # Stack for CPU Cores in Secure Mode (Top of OCM)
  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x1D0FF000|UINT32|0x00000005
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000|UINT32|0x00000036
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006

  # Stack for CPU Cores in Secure Monitor Mode
  #gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
  #gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008

  # Stack for CPU Cores in Non Secure Mode
  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x0|UINT64|0x00000009
  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A

  # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015

  # Size to reserve in the primary core stack for PEI Global Variables
  #  = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
  gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
  # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
  # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017
  gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018

  # Size to reserve in the primary core stack for SEC Global Variables
  gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031

  #
  # XGene Peripherals
  #

  # DW UART
  gArmPlatformTokenSpaceGuid.DWUartClkInHz|10000000|UINT32|0x0000001F
  gArmPlatformTokenSpaceGuid.DWUartInteger|0|UINT32|0x00000020
  gArmPlatformTokenSpaceGuid.DWUartFractional|0|UINT32|0x0000002D


  # AHBC
  gArmPlatformTokenSpaceGuid.PcdAHBCRegisterBase|0x1f2a0000|UINT64|0x0000003E

  # SLimPro
  gArmPlatformTokenSpaceGuid.PcdAPM88XXXXSlimproScuBase|0x17000000|UINT64|0x00000024

  #
  # BDS - Boot Manager
  #
  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
  gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E
  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""|VOID*|0x000000F
  # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath:
  #  - 0 = an EFI application
  #  - 1 = a Linux kernel with ATAG support
  #  - 2 = a Linux kernel with FDT support
  gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010
  gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011
  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x07000000|UINT32|0x00000020

  ## Timeout value for displaying progressing bar in before boot OS.
  #  According to UEFI 2.0 spec, the default TimeOut should be 0xffff.
  gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A

  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C

  # SDIO
  gArmPlatformTokenSpaceGuid.PcdSDIOHostPhyEnableMask|0x00000001|UINT32|0x0000003D
  gArmPlatformTokenSpaceGuid.PcdSDIORegisterBase|0x1C000000|UINT64|0x0000003F
  gArmPlatformTokenSpaceGuid.PcdSDIOCapLow|0x0|UINT32|0x00000040
  gArmPlatformTokenSpaceGuid.PcdSDIOCapHigh|0x0|UINT32|0x00000041

  # DW SPI
  gArmPlatformTokenSpaceGuid.PcdDWSpiClkInHz|4000000|UINT32|0x00000042
  gArmPlatformTokenSpaceGuid.PcdDWSpiBaseAddress|0x1C025000|UINT64|0x00000043
  gArmPlatformTokenSpaceGuid.PcdDWSpiMaxCS|3|UINT32|0x00000044
  gArmPlatformTokenSpaceGuid.PcdDWSpiFifoDepth|256|UINT32|0x00000045
  gArmPlatformTokenSpaceGuid.PcdDWSpiSysClk|100000000|UINT32|0x00000046
  gArmPlatformTokenSpaceGuid.PcdDWSpiVerId|0x3331352A|UINT32|0x00000047

  gArmPlatformTokenSpaceGuid.PcdSysClkInHz|100000000|UINT32|0x00000048

  gArmPlatformTokenSpaceGuid.PcdSPIFlashBus|0x0|UINT32|0x00000049
  gArmPlatformTokenSpaceGuid.PcdSPIFlashCS|0x0|UINT32|0x00000050
  gArmPlatformTokenSpaceGuid.PcdSPIFlashMaxHz|4000000|UINT32|0x00000051

  # AHCI common (Enable controller 2 and 3)
  gArmPlatformTokenSpaceGuid.PcdSataControllerMask|0x1|UINT32|0x00000079
  
  # AHCI Controller 3 (Enabled)
  gArmPlatformTokenSpaceGuid.PcdAHCI3RegisterBase|0x1a800000|UINT64|0x00000055
  gArmPlatformTokenSpaceGuid.PcdSata3SerdesRegisterBase|0x1f230000|UINT64|0x00000056
  gArmPlatformTokenSpaceGuid.PcdSata3GenMax|3|UINT32|0x00000057
  gArmPlatformTokenSpaceGuid.PcdSata3Irq|136|UINT32|0x00000058

  # AHCI Controller 2 (Enabled)
  gArmPlatformTokenSpaceGuid.PcdAHCI2RegisterBase|0x1a400000|UINT64|0x00000059
  gArmPlatformTokenSpaceGuid.PcdSata2SerdesRegisterBase|0x1f220000|UINT64|0x0000005A
  gArmPlatformTokenSpaceGuid.PcdSata2GenMax|3|UINT32|0x0000005B
  gArmPlatformTokenSpaceGuid.PcdSata2Irq|135|UINT32|0x0000005C

  # AHCI Controller 1 (disabled)
  gArmPlatformTokenSpaceGuid.PcdAHCI1RegisterBase|0x1a000000|UINT64|0x0000005D
  gArmPlatformTokenSpaceGuid.PcdSata1SerdesRegisterBase|0x1f210000|UINT64|0x0000005E
  gArmPlatformTokenSpaceGuid.PcdSata1GenMax|3|UINT32|0x0000005F
  gArmPlatformTokenSpaceGuid.PcdSata1Irq|134|UINT32|0x00000060

  # XHCI common
  gArmPlatformTokenSpaceGuid.PcdUsbControllerMask|0x0|UINT32|0x0000007D

  # XHCI Controller 2
  gArmPlatformTokenSpaceGuid.PcdXHCI2RegisterBase|0x19800000|UINT64|0x00000061
  gArmPlatformTokenSpaceGuid.PcdUsb2CsrRegisterBase|0x1f290000|UINT64|0x00000062
  gArmPlatformTokenSpaceGuid.PcdUsb2Irq|137|UINT32|0x00000063
  gArmPlatformTokenSpaceGuid.PcdUsb2ClkSel|0|UINT32|0x00000064
  gArmPlatformTokenSpaceGuid.PcdUsb2OvrcurEn|0|UINT32|0x00000065
  gArmPlatformTokenSpaceGuid.PcdUsb2OvrcurIvrt|0|UINT32|0x00000066

  # XHCI Controller 1
  gArmPlatformTokenSpaceGuid.PcdXHCI1RegisterBase|0x19000000|UINT64|0x00000067
  gArmPlatformTokenSpaceGuid.PcdUsb1CsrRegisterBase|0x1f280000|UINT64|0x00000068
  gArmPlatformTokenSpaceGuid.PcdUsb1Irq|136|UINT32|0x00000069
  gArmPlatformTokenSpaceGuid.PcdUsb1ClkSel|0|UINT32|0x0000006A
  gArmPlatformTokenSpaceGuid.PcdUsb1OvrcurEn|0|UINT32|0x0000006B
  gArmPlatformTokenSpaceGuid.PcdUsb1OvrcurIvrt|0|UINT32|0x0000006C

  #PCIE
  gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeMask|0|UINT32|0x00000073
  gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeGen|0x33333|UINT32|0x00000074
  gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeWidth|0x48148|UINT32|0x00000075
  gArmPlatformTokenSpaceGuid.PcdPcieRootBridgeResetGpioPin|0x0|UINT64|0x00000077

  # AHBC
  gArmPlatformTokenSpaceGuid.PcdGPIORegisterBase|0x1c024000|UINT64|0x00000078

  # Misc
  gArmPlatformTokenSpaceGuid.PcdMemSizeAddr|0|UINT64|0x0000007A

  gArmPlatformTokenSpaceGuid.PcdKernMailboxAddr|0|UINT64|0x0000007B
  gArmPlatformTokenSpaceGuid.PcdTTBBaseAddr|0|UINT64|0x0000007C

  ## APM RealTimeClock
  gArmPlatformTokenSpaceGuid.PcdApmRtcBase|0x10510000|UINT64|0x0000007E

  gArmPlatformTokenSpaceGuid.PcdL3cSize|8|UINT32|0x0000007F

[PcdsDynamic.common]
  gArmTokenSpaceGuid.PcdBootingLinuxUEFI|0|UINT32|0x00000080