diff options
Diffstat (limited to 'sgx/services4/srvkm/hwdefs')
| -rw-r--r-- | sgx/services4/srvkm/hwdefs/ocpdefs.h | 90 | ||||
| -rw-r--r-- | sgx/services4/srvkm/hwdefs/sgx530defs.h | 107 | ||||
| -rw-r--r-- | sgx/services4/srvkm/hwdefs/sgx540defs.h | 111 | ||||
| -rw-r--r-- | sgx/services4/srvkm/hwdefs/sgx544defs.h | 173 | ||||
| -rw-r--r-- | sgx/services4/srvkm/hwdefs/sgxdefs.h | 81 | ||||
| -rw-r--r-- | sgx/services4/srvkm/hwdefs/sgxerrata.h | 652 | ||||
| -rw-r--r-- | sgx/services4/srvkm/hwdefs/sgxfeaturedefs.h | 106 | ||||
| -rw-r--r-- | sgx/services4/srvkm/hwdefs/sgxmmu.h | 80 | ||||
| -rw-r--r-- | sgx/services4/srvkm/hwdefs/sgxmpdefs.h | 90 |
9 files changed, 855 insertions, 635 deletions
diff --git a/sgx/services4/srvkm/hwdefs/ocpdefs.h b/sgx/services4/srvkm/hwdefs/ocpdefs.h index 3bbab7b..cc4d54e 100644 --- a/sgx/services4/srvkm/hwdefs/ocpdefs.h +++ b/sgx/services4/srvkm/hwdefs/ocpdefs.h @@ -1,37 +1,55 @@ -/********************************************************************** - * - * Copyright (C) Imagination Technologies Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful but, except - * as otherwise stated in writing, without any warranty; without even the - * implied warranty of merchantability or fitness for a particular purpose. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - * Contact Information: - * Imagination Technologies Ltd. <gpl-support@imgtec.com> - * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK - * - ******************************************************************************/ +/*************************************************************************/ /*! +@Title OCP HW definitions. +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ /**************************************************************************/ #ifndef _OCPDEFS_H_ #define _OCPDEFS_H_ +/* Register EUR_CR_OCP_REVISION */ #define EUR_CR_OCP_REVISION 0xFE00 #define EUR_CR_OCP_REVISION_REV_MASK 0xFFFFFFFFUL #define EUR_CR_OCP_REVISION_REV_SHIFT 0 #define EUR_CR_OCP_REVISION_REV_SIGNED 0 +/* Register EUR_CR_OCP_HWINFO */ #define EUR_CR_OCP_HWINFO 0xFE04 #define EUR_CR_OCP_HWINFO_SYS_BUS_WIDTH_MASK 0x00000003UL #define EUR_CR_OCP_HWINFO_SYS_BUS_WIDTH_SHIFT 0 @@ -41,6 +59,7 @@ #define EUR_CR_OCP_HWINFO_MEM_BUS_WIDTH_SHIFT 2 #define EUR_CR_OCP_HWINFO_MEM_BUS_WIDTH_SIGNED 0 +/* Register EUR_CR_OCP_SYSCONFIG */ #define EUR_CR_OCP_SYSCONFIG 0xFE10 #define EUR_CR_OCP_SYSCONFIG_IDLE_MODE_MASK 0x0000000CUL #define EUR_CR_OCP_SYSCONFIG_IDLE_MODE_SHIFT 2 @@ -50,66 +69,79 @@ #define EUR_CR_OCP_SYSCONFIG_STANDBY_MODE_SHIFT 4 #define EUR_CR_OCP_SYSCONFIG_STANDBY_MODE_SIGNED 0 +/* Register EUR_CR_OCP_IRQSTATUS_RAW_0 */ #define EUR_CR_OCP_IRQSTATUS_RAW_0 0xFE24 #define EUR_CR_OCP_IRQSTATUS_RAW_0_INIT_MASK 0x00000001UL #define EUR_CR_OCP_IRQSTATUS_RAW_0_INIT_SHIFT 0 #define EUR_CR_OCP_IRQSTATUS_RAW_0_INIT_SIGNED 0 +/* Register EUR_CR_OCP_IRQSTATUS_RAW_1 */ #define EUR_CR_OCP_IRQSTATUS_RAW_1 0xFE28 #define EUR_CR_OCP_IRQSTATUS_RAW_1_TARGET_MASK 0x00000001UL #define EUR_CR_OCP_IRQSTATUS_RAW_1_TARGET_SHIFT 0 #define EUR_CR_OCP_IRQSTATUS_RAW_1_TARGET_SIGNED 0 +/* Register EUR_CR_OCP_IRQSTATUS_RAW_2 */ #define EUR_CR_OCP_IRQSTATUS_RAW_2 0xFE2C #define EUR_CR_OCP_IRQSTATUS_RAW_2_SGXCORE_MASK 0x00000001UL #define EUR_CR_OCP_IRQSTATUS_RAW_2_SGXCORE_SHIFT 0 #define EUR_CR_OCP_IRQSTATUS_RAW_2_SGXCORE_SIGNED 0 +/* Register EUR_CR_OCP_IRQSTATUS_0 */ #define EUR_CR_OCP_IRQSTATUS_0 0xFE30 #define EUR_CR_OCP_IRQSTATUS_0_INIT_MASK 0x00000001UL #define EUR_CR_OCP_IRQSTATUS_0_INIT_SHIFT 0 #define EUR_CR_OCP_IRQSTATUS_0_INIT_SIGNED 0 +/* Register EUR_CR_OCP_IRQSTATUS_1 */ #define EUR_CR_OCP_IRQSTATUS_1 0xFE34 #define EUR_CR_OCP_IRQSTATUS_1_TARGET_MASK 0x00000001UL #define EUR_CR_OCP_IRQSTATUS_1_TARGET_SHIFT 0 #define EUR_CR_OCP_IRQSTATUS_1_TARGET_SIGNED 0 +/* Register EUR_CR_OCP_IRQSTATUS_2 */ #define EUR_CR_OCP_IRQSTATUS_2 0xFE38 #define EUR_CR_OCP_IRQSTATUS_2_SGXCORE_MASK 0x00000001UL #define EUR_CR_OCP_IRQSTATUS_2_SGXCORE_SHIFT 0 #define EUR_CR_OCP_IRQSTATUS_2_SGXCORE_SIGNED 0 +/* Register EUR_CR_OCP_IRQENABLE_SET_0 */ #define EUR_CR_OCP_IRQENABLE_SET_0 0xFE3C #define EUR_CR_OCP_IRQENABLE_SET_0_INIT_MASK 0x00000001UL #define EUR_CR_OCP_IRQENABLE_SET_0_INIT_SHIFT 0 #define EUR_CR_OCP_IRQENABLE_SET_0_INIT_SIGNED 0 +/* Register EUR_CR_OCP_IRQENABLE_SET_1 */ #define EUR_CR_OCP_IRQENABLE_SET_1 0xFE40 #define EUR_CR_OCP_IRQENABLE_SET_1_TARGET_MASK 0x00000001UL #define EUR_CR_OCP_IRQENABLE_SET_1_TARGET_SHIFT 0 #define EUR_CR_OCP_IRQENABLE_SET_1_TARGET_SIGNED 0 +/* Register EUR_CR_OCP_IRQENABLE_SET_2 */ #define EUR_CR_OCP_IRQENABLE_SET_2 0xFE44 #define EUR_CR_OCP_IRQENABLE_SET_2_SGXCORE_MASK 0x00000001UL #define EUR_CR_OCP_IRQENABLE_SET_2_SGXCORE_SHIFT 0 #define EUR_CR_OCP_IRQENABLE_SET_2_SGXCORE_SIGNED 0 +/* Register EUR_CR_OCP_IRQENABLE_CLR_0 */ #define EUR_CR_OCP_IRQENABLE_CLR_0 0xFE48 #define EUR_CR_OCP_IRQENABLE_CLR_0_INIT_MASK 0x00000001UL #define EUR_CR_OCP_IRQENABLE_CLR_0_INIT_SHIFT 0 #define EUR_CR_OCP_IRQENABLE_CLR_0_INIT_SIGNED 0 +/* Register EUR_CR_OCP_IRQENABLE_CLR_1 */ #define EUR_CR_OCP_IRQENABLE_CLR_1 0xFE4C #define EUR_CR_OCP_IRQENABLE_CLR_1_TARGET_MASK 0x00000001UL #define EUR_CR_OCP_IRQENABLE_CLR_1_TARGET_SHIFT 0 #define EUR_CR_OCP_IRQENABLE_CLR_1_TARGET_SIGNED 0 +/* Register EUR_CR_OCP_IRQENABLE_CLR_2 */ #define EUR_CR_OCP_IRQENABLE_CLR_2 0xFE50 #define EUR_CR_OCP_IRQENABLE_CLR_2_SGXCORE_MASK 0x00000001UL #define EUR_CR_OCP_IRQENABLE_CLR_2_SGXCORE_SHIFT 0 #define EUR_CR_OCP_IRQENABLE_CLR_2_SGXCORE_SIGNED 0 +/* Register EUR_CR_OCP_PAGE_CONFIG */ #define EUR_CR_OCP_PAGE_CONFIG 0xFF00 #define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_SIZE_MASK 0x00000001UL #define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_SIZE_SHIFT 0 @@ -123,6 +155,7 @@ #define EUR_CR_OCP_PAGE_CONFIG_SIZE_SHIFT 3 #define EUR_CR_OCP_PAGE_CONFIG_SIZE_SIGNED 0 +/* Register EUR_CR_OCP_INTERRUPT_EVENT */ #define EUR_CR_OCP_INTERRUPT_EVENT 0xFF04 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_MASK 0x00000001UL #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_SHIFT 0 @@ -160,6 +193,7 @@ #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_SHIFT 10 #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_SIGNED 0 +/* Register EUR_CR_OCP_DEBUG_CONFIG */ #define EUR_CR_OCP_DEBUG_CONFIG 0xFF08 #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_TARGET_IDLE_MASK 0x00000003UL #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_TARGET_IDLE_SHIFT 0 @@ -181,6 +215,7 @@ #define EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_SHIFT 31 #define EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_SIGNED 0 +/* Register EUR_CR_OCP_DEBUG_STATUS */ #define EUR_CR_OCP_DEBUG_STATUS 0xFF0C #define EUR_CR_OCP_DEBUG_STATUS_TARGET_MCONNECT_MASK 0x00000003UL #define EUR_CR_OCP_DEBUG_STATUS_TARGET_MCONNECT_SHIFT 0 @@ -267,5 +302,8 @@ #define EUR_CR_OCP_DEBUG_STATUS_CMD_DEBUG_STATE_SIGNED 0 -#endif +#endif /* _OCPDEFS_H_ */ +/***************************************************************************** + End of file (ocpdefs.h) +*****************************************************************************/ diff --git a/sgx/services4/srvkm/hwdefs/sgx530defs.h b/sgx/services4/srvkm/hwdefs/sgx530defs.h index 810cb81..d4ec16f 100644 --- a/sgx/services4/srvkm/hwdefs/sgx530defs.h +++ b/sgx/services4/srvkm/hwdefs/sgx530defs.h @@ -1,32 +1,49 @@ -/********************************************************************** - * - * Copyright (C) Imagination Technologies Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful but, except - * as otherwise stated in writing, without any warranty; without even the - * implied warranty of merchantability or fitness for a particular purpose. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - * Contact Information: - * Imagination Technologies Ltd. <gpl-support@imgtec.com> - * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK - * - ******************************************************************************/ +/*************************************************************************/ /*! +@Title Hardware defs for SGX530. +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ /**************************************************************************/ #ifndef _SGX530DEFS_KM_H_ #define _SGX530DEFS_KM_H_ +/* Register EUR_CR_CLKGATECTL */ #define EUR_CR_CLKGATECTL 0x0000 #define EUR_CR_CLKGATECTL_2D_CLKG_MASK 0x00000003U #define EUR_CR_CLKGATECTL_2D_CLKG_SHIFT 0 @@ -42,6 +59,7 @@ #define EUR_CR_CLKGATECTL_USE_CLKG_SHIFT 20 #define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U #define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 +/* Register EUR_CR_CLKGATESTATUS */ #define EUR_CR_CLKGATESTATUS 0x0004 #define EUR_CR_CLKGATESTATUS_2D_CLKS_MASK 0x00000001U #define EUR_CR_CLKGATESTATUS_2D_CLKS_SHIFT 0 @@ -55,6 +73,7 @@ #define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 16 #define EUR_CR_CLKGATESTATUS_USE_CLKS_MASK 0x00100000U #define EUR_CR_CLKGATESTATUS_USE_CLKS_SHIFT 20 +/* Register EUR_CR_CLKGATECTLOVR */ #define EUR_CR_CLKGATECTLOVR 0x0008 #define EUR_CR_CLKGATECTLOVR_2D_CLKO_MASK 0x00000003U #define EUR_CR_CLKGATECTLOVR_2D_CLKO_SHIFT 0 @@ -68,11 +87,13 @@ #define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 16 #define EUR_CR_CLKGATECTLOVR_USE_CLKO_MASK 0x00300000U #define EUR_CR_CLKGATECTLOVR_USE_CLKO_SHIFT 20 +/* Register EUR_CR_CORE_ID */ #define EUR_CR_CORE_ID 0x0010 #define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU #define EUR_CR_CORE_ID_CONFIG_SHIFT 0 #define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U #define EUR_CR_CORE_ID_ID_SHIFT 16 +/* Register EUR_CR_CORE_REVISION */ #define EUR_CR_CORE_REVISION 0x0014 #define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU #define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 @@ -82,12 +103,15 @@ #define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 #define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U #define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 +/* Register EUR_CR_DESIGNER_REV_FIELD1 */ #define EUR_CR_DESIGNER_REV_FIELD1 0x0018 #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 +/* Register EUR_CR_DESIGNER_REV_FIELD2 */ #define EUR_CR_DESIGNER_REV_FIELD2 0x001C #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 +/* Register EUR_CR_SOFT_RESET */ #define EUR_CR_SOFT_RESET 0x0080 #define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U #define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 @@ -103,6 +127,7 @@ #define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5 #define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000040U #define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 6 +/* Register EUR_CR_EVENT_HOST_ENABLE2 */ #define EUR_CR_EVENT_HOST_ENABLE2 0x0110 #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 @@ -114,6 +139,7 @@ #define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 +/* Register EUR_CR_EVENT_HOST_CLEAR2 */ #define EUR_CR_EVENT_HOST_CLEAR2 0x0114 #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 @@ -125,6 +151,7 @@ #define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 +/* Register EUR_CR_EVENT_STATUS2 */ #define EUR_CR_EVENT_STATUS2 0x0118 #define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U #define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 @@ -136,6 +163,7 @@ #define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 +/* Register EUR_CR_EVENT_STATUS */ #define EUR_CR_EVENT_STATUS 0x012CU #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 @@ -199,6 +227,7 @@ #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 +/* Register EUR_CR_EVENT_HOST_ENABLE */ #define EUR_CR_EVENT_HOST_ENABLE 0x0130 #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 @@ -262,6 +291,7 @@ #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 +/* Register EUR_CR_EVENT_HOST_CLEAR */ #define EUR_CR_EVENT_HOST_CLEAR 0x0134 #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 @@ -325,38 +355,49 @@ #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 +/* Register EUR_CR_PDS_EXEC_BASE */ #define EUR_CR_PDS_EXEC_BASE 0x0AB8 #define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20 +/* Register EUR_CR_EVENT_KICKER */ #define EUR_CR_EVENT_KICKER 0x0AC4 #define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0x0FFFFFF0U #define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 +/* Register EUR_CR_EVENT_KICK */ #define EUR_CR_EVENT_KICK 0x0AC8 #define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U #define EUR_CR_EVENT_KICK_NOW_SHIFT 0 +/* Register EUR_CR_EVENT_TIMER */ #define EUR_CR_EVENT_TIMER 0x0ACC #define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U #define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 #define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU #define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 +/* Register EUR_CR_PDS_INV0 */ #define EUR_CR_PDS_INV0 0x0AD0 #define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV0_DSC_SHIFT 0 +/* Register EUR_CR_PDS_INV1 */ #define EUR_CR_PDS_INV1 0x0AD4 #define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV1_DSC_SHIFT 0 +/* Register EUR_CR_PDS_INV2 */ #define EUR_CR_PDS_INV2 0x0AD8 #define EUR_CR_PDS_INV2_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV2_DSC_SHIFT 0 +/* Register EUR_CR_PDS_INV3 */ #define EUR_CR_PDS_INV3 0x0ADC #define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV3_DSC_SHIFT 0 +/* Register EUR_CR_PDS_INV_CSC */ #define EUR_CR_PDS_INV_CSC 0x0AE0 #define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U #define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 +/* Register EUR_CR_PDS_PC_BASE */ #define EUR_CR_PDS_PC_BASE 0x0B2C #define EUR_CR_PDS_PC_BASE_ADDRESS_MASK 0x3FFFFFFFU #define EUR_CR_PDS_PC_BASE_ADDRESS_SHIFT 0 +/* Register EUR_CR_BIF_CTRL */ #define EUR_CR_BIF_CTRL 0x0C00 #define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U #define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 @@ -384,6 +425,7 @@ #define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 #define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U #define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 +/* Register EUR_CR_BIF_INT_STAT */ #define EUR_CR_BIF_INT_STAT 0x0C04 #define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU #define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0 @@ -391,32 +433,41 @@ #define EUR_CR_BIF_INT_STAT_PF_N_RW_SHIFT 14 #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15 +/* Register EUR_CR_BIF_FAULT */ #define EUR_CR_BIF_FAULT 0x0C08 #define EUR_CR_BIF_FAULT_ADDR_MASK 0x0FFFF000U #define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 +/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ #define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 +/* Register EUR_CR_BIF_TWOD_REQ_BASE */ #define EUR_CR_BIF_TWOD_REQ_BASE 0x0C88 #define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_SHIFT 20 +/* Register EUR_CR_BIF_TA_REQ_BASE */ #define EUR_CR_BIF_TA_REQ_BASE 0x0C90 #define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 +/* Register EUR_CR_BIF_MEM_REQ_STAT */ #define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 #define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU #define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 +/* Register EUR_CR_BIF_3D_REQ_BASE */ #define EUR_CR_BIF_3D_REQ_BASE 0x0CAC #define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 +/* Register EUR_CR_BIF_ZLS_REQ_BASE */ #define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 +/* Register EUR_CR_2D_BLIT_STATUS */ #define EUR_CR_2D_BLIT_STATUS 0x0E04 #define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU #define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 #define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U #define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 +/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ #define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 @@ -426,6 +477,7 @@ #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 +/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ #define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 @@ -433,11 +485,14 @@ #define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 +/* Table EUR_CR_USE_CODE_BASE */ +/* Register EUR_CR_USE_CODE_BASE */ #define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) #define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x00FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 #define EUR_CR_USE_CODE_BASE_DM_MASK 0x03000000U #define EUR_CR_USE_CODE_BASE_DM_SHIFT 24 +/* Number of entries in table EUR_CR_USE_CODE_BASE */ #define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 #define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 #define EUR_CR_MNE_CR_CTRL 0x0D00 @@ -484,5 +539,5 @@ #define EUR_CR_MNE_CR_EVENT_CLEAR_INVAL_SHIFT 0 #define EUR_CR_MNE_CR_CTRL_INVAL 0x0D20 -#endif +#endif /* _SGX530DEFS_KM_H_ */ diff --git a/sgx/services4/srvkm/hwdefs/sgx540defs.h b/sgx/services4/srvkm/hwdefs/sgx540defs.h index c09aa26..25f9ec1 100644 --- a/sgx/services4/srvkm/hwdefs/sgx540defs.h +++ b/sgx/services4/srvkm/hwdefs/sgx540defs.h @@ -1,32 +1,49 @@ -/********************************************************************** - * - * Copyright (C) Imagination Technologies Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful but, except - * as otherwise stated in writing, without any warranty; without even the - * implied warranty of merchantability or fitness for a particular purpose. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - * Contact Information: - * Imagination Technologies Ltd. <gpl-support@imgtec.com> - * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK - * - ******************************************************************************/ +/*************************************************************************/ /*! +@Title Hardware defs for SGX540. +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ /**************************************************************************/ #ifndef _SGX540DEFS_KM_H_ #define _SGX540DEFS_KM_H_ +/* Register EUR_CR_CLKGATECTL */ #define EUR_CR_CLKGATECTL 0x0000 #define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U #define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0 @@ -52,6 +69,7 @@ #define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28 +/* Register EUR_CR_CLKGATECTL2 */ #define EUR_CR_CLKGATECTL2 0x0004 #define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U #define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0 @@ -75,6 +93,7 @@ #define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18 #define EUR_CR_CLKGATECTL2_MADD1_CLKG_MASK 0x00300000U #define EUR_CR_CLKGATECTL2_MADD1_CLKG_SHIFT 20 +/* Register EUR_CR_CLKGATESTATUS */ #define EUR_CR_CLKGATESTATUS 0x0008 #define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U #define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0 @@ -118,6 +137,7 @@ #define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19 #define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U #define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20 +/* Register EUR_CR_CLKGATECTLOVR */ #define EUR_CR_CLKGATECTLOVR 0x000C #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 @@ -139,14 +159,17 @@ #define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16 #define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U #define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18 +/* Register EUR_CR_POWER */ #define EUR_CR_POWER 0x001C #define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U #define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0 +/* Register EUR_CR_CORE_ID */ #define EUR_CR_CORE_ID 0x0020 #define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU #define EUR_CR_CORE_ID_CONFIG_SHIFT 0 #define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U #define EUR_CR_CORE_ID_ID_SHIFT 16 +/* Register EUR_CR_CORE_REVISION */ #define EUR_CR_CORE_REVISION 0x0024 #define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU #define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 @@ -156,12 +179,15 @@ #define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 #define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U #define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 +/* Register EUR_CR_DESIGNER_REV_FIELD1 */ #define EUR_CR_DESIGNER_REV_FIELD1 0x0028 #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 +/* Register EUR_CR_DESIGNER_REV_FIELD2 */ #define EUR_CR_DESIGNER_REV_FIELD2 0x002C #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 +/* Register EUR_CR_SOFT_RESET */ #define EUR_CR_SOFT_RESET 0x0080 #define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U #define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 @@ -199,6 +225,7 @@ #define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16 #define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U #define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17 +/* Register EUR_CR_EVENT_HOST_ENABLE2 */ #define EUR_CR_EVENT_HOST_ENABLE2 0x0110 #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 @@ -210,6 +237,7 @@ #define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 +/* Register EUR_CR_EVENT_HOST_CLEAR2 */ #define EUR_CR_EVENT_HOST_CLEAR2 0x0114 #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 @@ -221,6 +249,7 @@ #define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 +/* Register EUR_CR_EVENT_STATUS2 */ #define EUR_CR_EVENT_STATUS2 0x0118 #define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U #define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 @@ -232,6 +261,7 @@ #define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 +/* Register EUR_CR_EVENT_STATUS */ #define EUR_CR_EVENT_STATUS 0x012CU #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 @@ -295,6 +325,7 @@ #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 +/* Register EUR_CR_EVENT_HOST_ENABLE */ #define EUR_CR_EVENT_HOST_ENABLE 0x0130 #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 @@ -358,6 +389,7 @@ #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 +/* Register EUR_CR_EVENT_HOST_CLEAR */ #define EUR_CR_EVENT_HOST_CLEAR 0x0134 #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 @@ -421,47 +453,61 @@ #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 +/* Register EUR_CR_TIMER */ #define EUR_CR_TIMER 0x0144 #define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU #define EUR_CR_TIMER_VALUE_SHIFT 0 +/* Register EUR_CR_EVENT_KICK1 */ #define EUR_CR_EVENT_KICK1 0x0AB0 #define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU #define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 +/* Register EUR_CR_PDS_EXEC_BASE */ #define EUR_CR_PDS_EXEC_BASE 0x0AB8 #define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20 +/* Register EUR_CR_EVENT_KICK2 */ #define EUR_CR_EVENT_KICK2 0x0AC0 #define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U #define EUR_CR_EVENT_KICK2_NOW_SHIFT 0 +/* Register EUR_CR_EVENT_KICKER */ #define EUR_CR_EVENT_KICKER 0x0AC4 #define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0x0FFFFFF0U #define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 +/* Register EUR_CR_EVENT_KICK */ #define EUR_CR_EVENT_KICK 0x0AC8 #define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U #define EUR_CR_EVENT_KICK_NOW_SHIFT 0 +/* Register EUR_CR_EVENT_TIMER */ #define EUR_CR_EVENT_TIMER 0x0ACC #define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U #define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 #define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU #define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 +/* Register EUR_CR_PDS_INV0 */ #define EUR_CR_PDS_INV0 0x0AD0 #define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV0_DSC_SHIFT 0 +/* Register EUR_CR_PDS_INV1 */ #define EUR_CR_PDS_INV1 0x0AD4 #define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV1_DSC_SHIFT 0 +/* Register EUR_CR_EVENT_KICK3 */ #define EUR_CR_EVENT_KICK3 0x0AD8 #define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U #define EUR_CR_EVENT_KICK3_NOW_SHIFT 0 +/* Register EUR_CR_PDS_INV3 */ #define EUR_CR_PDS_INV3 0x0ADC #define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV3_DSC_SHIFT 0 +/* Register EUR_CR_PDS_INV_CSC */ #define EUR_CR_PDS_INV_CSC 0x0AE0 #define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U #define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 +/* Register EUR_CR_PDS_PC_BASE */ #define EUR_CR_PDS_PC_BASE 0x0B2C #define EUR_CR_PDS_PC_BASE_ADDRESS_MASK 0x00FFFFFFU #define EUR_CR_PDS_PC_BASE_ADDRESS_SHIFT 0 +/* Register EUR_CR_BIF_CTRL */ #define EUR_CR_BIF_CTRL 0x0C00 #define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U #define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 @@ -487,6 +533,7 @@ #define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 #define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U #define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 +/* Register EUR_CR_BIF_INT_STAT */ #define EUR_CR_BIF_INT_STAT 0x0C04 #define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU #define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0 @@ -494,31 +541,39 @@ #define EUR_CR_BIF_INT_STAT_PF_N_RW_SHIFT 14 #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15 +/* Register EUR_CR_BIF_FAULT */ #define EUR_CR_BIF_FAULT 0x0C08 #define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U #define EUR_CR_BIF_FAULT_SB_SHIFT 4 #define EUR_CR_BIF_FAULT_ADDR_MASK 0x0FFFF000U #define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 +/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ #define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 +/* Register EUR_CR_BIF_TA_REQ_BASE */ #define EUR_CR_BIF_TA_REQ_BASE 0x0C90 #define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 +/* Register EUR_CR_BIF_MEM_REQ_STAT */ #define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 #define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU #define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 +/* Register EUR_CR_BIF_3D_REQ_BASE */ #define EUR_CR_BIF_3D_REQ_BASE 0x0CAC #define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 +/* Register EUR_CR_BIF_ZLS_REQ_BASE */ #define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 +/* Register EUR_CR_2D_BLIT_STATUS */ #define EUR_CR_2D_BLIT_STATUS 0x0E04 #define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU #define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 #define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U #define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 +/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ #define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 @@ -528,6 +583,7 @@ #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 +/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ #define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 @@ -535,13 +591,16 @@ #define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 +/* Table EUR_CR_USE_CODE_BASE */ +/* Register EUR_CR_USE_CODE_BASE */ #define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) #define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x00FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 #define EUR_CR_USE_CODE_BASE_DM_MASK 0x03000000U #define EUR_CR_USE_CODE_BASE_DM_SHIFT 24 +/* Number of entries in table EUR_CR_USE_CODE_BASE */ #define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 #define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 -#endif +#endif /* _SGX540DEFS_KM_H_ */ diff --git a/sgx/services4/srvkm/hwdefs/sgx544defs.h b/sgx/services4/srvkm/hwdefs/sgx544defs.h index c18b8ad..c35a259 100644 --- a/sgx/services4/srvkm/hwdefs/sgx544defs.h +++ b/sgx/services4/srvkm/hwdefs/sgx544defs.h @@ -1,32 +1,49 @@ -/********************************************************************** - * - * Copyright (C) Imagination Technologies Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful but, except - * as otherwise stated in writing, without any warranty; without even the - * implied warranty of merchantability or fitness for a particular purpose. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - * Contact Information: - * Imagination Technologies Ltd. <gpl-support@imgtec.com> - * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK - * - ******************************************************************************/ +/*************************************************************************/ /*! +@Title Hardware defs for SGX544. +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ /**************************************************************************/ #ifndef _SGX544DEFS_KM_H_ #define _SGX544DEFS_KM_H_ +/* Register EUR_CR_CLKGATECTL */ #define EUR_CR_CLKGATECTL 0x0000 #define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U #define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0 @@ -67,6 +84,7 @@ #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28 #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SIGNED 0 +/* Register EUR_CR_CLKGATECTL2 */ #define EUR_CR_CLKGATECTL2 0x0004 #define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U #define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0 @@ -104,6 +122,7 @@ #define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_MASK 0x0C000000U #define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SHIFT 26 #define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SIGNED 0 +/* Register EUR_CR_CLKGATESTATUS */ #define EUR_CR_CLKGATESTATUS 0x0008 #define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U #define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0 @@ -174,6 +193,7 @@ #define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_MASK 0x01000000U #define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SHIFT 24 #define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SIGNED 0 +/* Register EUR_CR_CLKGATECTLOVR */ #define EUR_CR_CLKGATECTLOVR 0x000C #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 @@ -208,10 +228,12 @@ #define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_MASK 0x00300000U #define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SHIFT 20 #define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SIGNED 0 +/* Register EUR_CR_POWER */ #define EUR_CR_POWER 0x001C #define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U #define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0 #define EUR_CR_POWER_PIPE_DISABLE_SIGNED 0 +/* Register EUR_CR_CORE_ID */ #define EUR_CR_CORE_ID 0x0020 #define EUR_CR_CORE_ID_CONFIG_MULTI_MASK 0x00000001U #define EUR_CR_CORE_ID_CONFIG_MULTI_SHIFT 0 @@ -231,6 +253,7 @@ #define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U #define EUR_CR_CORE_ID_ID_SHIFT 16 #define EUR_CR_CORE_ID_ID_SIGNED 0 +/* Register EUR_CR_CORE_REVISION */ #define EUR_CR_CORE_REVISION 0x0024 #define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU #define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 @@ -244,14 +267,17 @@ #define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U #define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 #define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0 +/* Register EUR_CR_DESIGNER_REV_FIELD1 */ #define EUR_CR_DESIGNER_REV_FIELD1 0x0028 #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0 +/* Register EUR_CR_DESIGNER_REV_FIELD2 */ #define EUR_CR_DESIGNER_REV_FIELD2 0x002C #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0 +/* Register EUR_CR_SOFT_RESET */ #define EUR_CR_SOFT_RESET 0x0080 #define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U #define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 @@ -310,6 +336,7 @@ #define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK 0x00080000U #define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SHIFT 19 #define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SIGNED 0 +/* Register EUR_CR_EVENT_HOST_ENABLE2 */ #define EUR_CR_EVENT_HOST_ENABLE2 0x0110 #define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U #define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 @@ -347,6 +374,7 @@ #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0 +/* Register EUR_CR_EVENT_HOST_CLEAR2 */ #define EUR_CR_EVENT_HOST_CLEAR2 0x0114 #define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U #define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 @@ -384,6 +412,7 @@ #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0 +/* Register EUR_CR_EVENT_STATUS2 */ #define EUR_CR_EVENT_STATUS2 0x0118 #define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U #define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 @@ -421,6 +450,7 @@ #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0 +/* Register EUR_CR_EVENT_STATUS */ #define EUR_CR_EVENT_STATUS 0x012C #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 @@ -506,6 +536,7 @@ #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0 +/* Register EUR_CR_EVENT_HOST_ENABLE */ #define EUR_CR_EVENT_HOST_ENABLE 0x0130 #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 @@ -591,6 +622,7 @@ #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0 +/* Register EUR_CR_EVENT_HOST_CLEAR */ #define EUR_CR_EVENT_HOST_CLEAR 0x0134 #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 @@ -676,26 +708,32 @@ #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0 +/* Register EUR_CR_TIMER */ #define EUR_CR_TIMER 0x0144 #define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU #define EUR_CR_TIMER_VALUE_SHIFT 0 #define EUR_CR_TIMER_VALUE_SIGNED 0 +/* Register EUR_CR_EVENT_KICK1 */ #define EUR_CR_EVENT_KICK1 0x0AB0 #define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU #define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 #define EUR_CR_EVENT_KICK1_NOW_SIGNED 0 +/* Register EUR_CR_EVENT_KICK2 */ #define EUR_CR_EVENT_KICK2 0x0AC0 #define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U #define EUR_CR_EVENT_KICK2_NOW_SHIFT 0 #define EUR_CR_EVENT_KICK2_NOW_SIGNED 0 +/* Register EUR_CR_EVENT_KICKER */ #define EUR_CR_EVENT_KICKER 0x0AC4 #define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 #define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0 +/* Register EUR_CR_EVENT_KICK */ #define EUR_CR_EVENT_KICK 0x0AC8 #define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U #define EUR_CR_EVENT_KICK_NOW_SHIFT 0 #define EUR_CR_EVENT_KICK_NOW_SIGNED 0 +/* Register EUR_CR_EVENT_TIMER */ #define EUR_CR_EVENT_TIMER 0x0ACC #define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U #define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 @@ -703,26 +741,32 @@ #define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU #define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 #define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0 +/* Register EUR_CR_PDS_INV0 */ #define EUR_CR_PDS_INV0 0x0AD0 #define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV0_DSC_SHIFT 0 #define EUR_CR_PDS_INV0_DSC_SIGNED 0 +/* Register EUR_CR_PDS_INV1 */ #define EUR_CR_PDS_INV1 0x0AD4 #define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV1_DSC_SHIFT 0 #define EUR_CR_PDS_INV1_DSC_SIGNED 0 +/* Register EUR_CR_EVENT_KICK3 */ #define EUR_CR_EVENT_KICK3 0x0AD8 #define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U #define EUR_CR_EVENT_KICK3_NOW_SHIFT 0 #define EUR_CR_EVENT_KICK3_NOW_SIGNED 0 +/* Register EUR_CR_PDS_INV3 */ #define EUR_CR_PDS_INV3 0x0ADC #define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV3_DSC_SHIFT 0 #define EUR_CR_PDS_INV3_DSC_SIGNED 0 +/* Register EUR_CR_PDS_INV_CSC */ #define EUR_CR_PDS_INV_CSC 0x0AE0 #define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U #define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 #define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0 +/* Register EUR_CR_BIF_CTRL */ #define EUR_CR_BIF_CTRL 0x0C00 #define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U #define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 @@ -763,6 +807,7 @@ #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19 #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0 +/* Register EUR_CR_BIF_INT_STAT */ #define EUR_CR_BIF_INT_STAT 0x0C04 #define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x00003FFFU #define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0 @@ -773,6 +818,7 @@ #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19 #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0 +/* Register EUR_CR_BIF_FAULT */ #define EUR_CR_BIF_FAULT 0x0C08 #define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU #define EUR_CR_BIF_FAULT_CID_SHIFT 0 @@ -783,6 +829,7 @@ #define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 #define EUR_CR_BIF_FAULT_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_TILE0 */ #define EUR_CR_BIF_TILE0 0x0C0C #define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0 @@ -793,6 +840,7 @@ #define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE0_CFG_SHIFT 24 #define EUR_CR_BIF_TILE0_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE1 */ #define EUR_CR_BIF_TILE1 0x0C10 #define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0 @@ -803,6 +851,7 @@ #define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE1_CFG_SHIFT 24 #define EUR_CR_BIF_TILE1_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE2 */ #define EUR_CR_BIF_TILE2 0x0C14 #define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0 @@ -813,6 +862,7 @@ #define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE2_CFG_SHIFT 24 #define EUR_CR_BIF_TILE2_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE3 */ #define EUR_CR_BIF_TILE3 0x0C18 #define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0 @@ -823,6 +873,7 @@ #define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE3_CFG_SHIFT 24 #define EUR_CR_BIF_TILE3_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE4 */ #define EUR_CR_BIF_TILE4 0x0C1C #define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0 @@ -833,6 +884,7 @@ #define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE4_CFG_SHIFT 24 #define EUR_CR_BIF_TILE4_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE5 */ #define EUR_CR_BIF_TILE5 0x0C20 #define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0 @@ -843,6 +895,7 @@ #define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE5_CFG_SHIFT 24 #define EUR_CR_BIF_TILE5_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE6 */ #define EUR_CR_BIF_TILE6 0x0C24 #define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0 @@ -853,6 +906,7 @@ #define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE6_CFG_SHIFT 24 #define EUR_CR_BIF_TILE6_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE7 */ #define EUR_CR_BIF_TILE7 0x0C28 #define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0 @@ -863,6 +917,7 @@ #define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE7_CFG_SHIFT 24 #define EUR_CR_BIF_TILE7_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE8 */ #define EUR_CR_BIF_TILE8 0x0C2C #define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0 @@ -873,6 +928,7 @@ #define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE8_CFG_SHIFT 24 #define EUR_CR_BIF_TILE8_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE9 */ #define EUR_CR_BIF_TILE9 0x0C30 #define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0 @@ -883,6 +939,7 @@ #define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE9_CFG_SHIFT 24 #define EUR_CR_BIF_TILE9_CFG_SIGNED 0 +/* Register EUR_CR_BIF_CTRL_INVAL */ #define EUR_CR_BIF_CTRL_INVAL 0x0C34 #define EUR_CR_BIF_CTRL_INVAL_PTE_MASK 0x00000004U #define EUR_CR_BIF_CTRL_INVAL_PTE_SHIFT 2 @@ -890,34 +947,42 @@ #define EUR_CR_BIF_CTRL_INVAL_ALL_MASK 0x00000008U #define EUR_CR_BIF_CTRL_INVAL_ALL_SHIFT 3 #define EUR_CR_BIF_CTRL_INVAL_ALL_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE1 */ #define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38 #define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE2 */ #define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C #define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE3 */ #define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40 #define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE4 */ #define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44 #define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE5 */ #define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48 #define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE6 */ #define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C #define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE7 */ #define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50 #define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_BANK_SET */ #define EUR_CR_BIF_BANK_SET 0x0C74 #define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U #define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0 @@ -937,6 +1002,7 @@ #define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U #define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9 #define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0 +/* Register EUR_CR_BIF_BANK0 */ #define EUR_CR_BIF_BANK0 0x0C78 #define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU #define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0 @@ -950,6 +1016,7 @@ #define EUR_CR_BIF_BANK0_INDEX_PTLA_MASK 0x000F0000U #define EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT 16 #define EUR_CR_BIF_BANK0_INDEX_PTLA_SIGNED 0 +/* Register EUR_CR_BIF_BANK1 */ #define EUR_CR_BIF_BANK1 0x0C7C #define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU #define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0 @@ -960,26 +1027,32 @@ #define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U #define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12 #define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ #define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_TA_REQ_BASE */ #define EUR_CR_BIF_TA_REQ_BASE 0x0C90 #define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U #define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 #define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_MEM_REQ_STAT */ #define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 #define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU #define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 #define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0 +/* Register EUR_CR_BIF_3D_REQ_BASE */ #define EUR_CR_BIF_3D_REQ_BASE 0x0CAC #define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U #define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 #define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_ZLS_REQ_BASE */ #define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_BANK_STATUS */ #define EUR_CR_BIF_BANK_STATUS 0x0CB4 #define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U #define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0 @@ -987,6 +1060,7 @@ #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0 +/* Register EUR_CR_BIF_MMU_CTRL */ #define EUR_CR_BIF_MMU_CTRL 0x0CD0 #define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U #define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0 @@ -1003,6 +1077,7 @@ #define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_MASK 0x00000020U #define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SHIFT 5 #define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SIGNED 0 +/* Register EUR_CR_2D_BLIT_STATUS */ #define EUR_CR_2D_BLIT_STATUS 0x0E04 #define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU #define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 @@ -1010,6 +1085,7 @@ #define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U #define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 #define EUR_CR_2D_BLIT_STATUS_BUSY_SIGNED 0 +/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ #define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 @@ -1023,6 +1099,7 @@ #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SIGNED 0 +/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ #define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 @@ -1033,14 +1110,17 @@ #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SIGNED 0 +/* Register EUR_CR_BREAKPOINT0_START */ #define EUR_CR_BREAKPOINT0_START 0x0F44 #define EUR_CR_BREAKPOINT0_START_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT0_START_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT0_START_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT0_END */ #define EUR_CR_BREAKPOINT0_END 0x0F48 #define EUR_CR_BREAKPOINT0_END_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT0_END_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT0_END_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT0 */ #define EUR_CR_BREAKPOINT0 0x0F4C #define EUR_CR_BREAKPOINT0_MASK_DM_MASK 0x00000038U #define EUR_CR_BREAKPOINT0_MASK_DM_SHIFT 3 @@ -1054,14 +1134,17 @@ #define EUR_CR_BREAKPOINT0_CTRL_RENABLE_MASK 0x00000001U #define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SHIFT 0 #define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SIGNED 0 +/* Register EUR_CR_BREAKPOINT1_START */ #define EUR_CR_BREAKPOINT1_START 0x0F50 #define EUR_CR_BREAKPOINT1_START_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT1_START_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT1_START_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT1_END */ #define EUR_CR_BREAKPOINT1_END 0x0F54 #define EUR_CR_BREAKPOINT1_END_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT1_END_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT1_END_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT1 */ #define EUR_CR_BREAKPOINT1 0x0F58 #define EUR_CR_BREAKPOINT1_MASK_DM_MASK 0x00000038U #define EUR_CR_BREAKPOINT1_MASK_DM_SHIFT 3 @@ -1075,14 +1158,17 @@ #define EUR_CR_BREAKPOINT1_CTRL_RENABLE_MASK 0x00000001U #define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SHIFT 0 #define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SIGNED 0 +/* Register EUR_CR_BREAKPOINT2_START */ #define EUR_CR_BREAKPOINT2_START 0x0F5C #define EUR_CR_BREAKPOINT2_START_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT2_START_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT2_START_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT2_END */ #define EUR_CR_BREAKPOINT2_END 0x0F60 #define EUR_CR_BREAKPOINT2_END_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT2_END_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT2_END_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT2 */ #define EUR_CR_BREAKPOINT2 0x0F64 #define EUR_CR_BREAKPOINT2_MASK_DM_MASK 0x00000038U #define EUR_CR_BREAKPOINT2_MASK_DM_SHIFT 3 @@ -1096,14 +1182,17 @@ #define EUR_CR_BREAKPOINT2_CTRL_RENABLE_MASK 0x00000001U #define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SHIFT 0 #define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SIGNED 0 +/* Register EUR_CR_BREAKPOINT3_START */ #define EUR_CR_BREAKPOINT3_START 0x0F68 #define EUR_CR_BREAKPOINT3_START_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT3_START_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT3_START_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT3_END */ #define EUR_CR_BREAKPOINT3_END 0x0F6C #define EUR_CR_BREAKPOINT3_END_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT3_END_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT3_END_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT3 */ #define EUR_CR_BREAKPOINT3 0x0F70 #define EUR_CR_BREAKPOINT3_MASK_DM_MASK 0x00000038U #define EUR_CR_BREAKPOINT3_MASK_DM_SHIFT 3 @@ -1117,10 +1206,12 @@ #define EUR_CR_BREAKPOINT3_CTRL_RENABLE_MASK 0x00000001U #define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SHIFT 0 #define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SIGNED 0 +/* Register EUR_CR_BREAKPOINT_READ */ #define EUR_CR_BREAKPOINT_READ 0x0F74 #define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0 +/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP */ #define EUR_CR_PARTITION_BREAKPOINT_TRAP 0x0F78 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U #define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 @@ -1128,6 +1219,7 @@ #define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U #define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 +/* Register EUR_CR_PARTITION_BREAKPOINT */ #define EUR_CR_PARTITION_BREAKPOINT 0x0F7C #define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_MASK 0x000003C0U #define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SHIFT 6 @@ -1141,10 +1233,12 @@ #define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_MASK 0x00000004U #define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SHIFT 2 #define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SIGNED 0 +/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 */ #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 0x0F80 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 +/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 */ #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 0x0F84 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 @@ -1161,6 +1255,7 @@ #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_0 */ #define EUR_CR_USE_CODE_BASE_0 0x0A0C #define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0 @@ -1168,6 +1263,7 @@ #define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_1 */ #define EUR_CR_USE_CODE_BASE_1 0x0A10 #define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0 @@ -1175,6 +1271,7 @@ #define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_2 */ #define EUR_CR_USE_CODE_BASE_2 0x0A14 #define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0 @@ -1182,6 +1279,7 @@ #define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_3 */ #define EUR_CR_USE_CODE_BASE_3 0x0A18 #define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0 @@ -1189,6 +1287,7 @@ #define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_4 */ #define EUR_CR_USE_CODE_BASE_4 0x0A1C #define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0 @@ -1196,6 +1295,7 @@ #define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_5 */ #define EUR_CR_USE_CODE_BASE_5 0x0A20 #define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0 @@ -1203,6 +1303,7 @@ #define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_6 */ #define EUR_CR_USE_CODE_BASE_6 0x0A24 #define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0 @@ -1210,6 +1311,7 @@ #define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_7 */ #define EUR_CR_USE_CODE_BASE_7 0x0A28 #define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0 @@ -1217,6 +1319,7 @@ #define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_8 */ #define EUR_CR_USE_CODE_BASE_8 0x0A2C #define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0 @@ -1224,6 +1327,7 @@ #define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_9 */ #define EUR_CR_USE_CODE_BASE_9 0x0A30 #define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0 @@ -1231,6 +1335,7 @@ #define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_10 */ #define EUR_CR_USE_CODE_BASE_10 0x0A34 #define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0 @@ -1238,6 +1343,7 @@ #define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_11 */ #define EUR_CR_USE_CODE_BASE_11 0x0A38 #define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0 @@ -1245,6 +1351,7 @@ #define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_12 */ #define EUR_CR_USE_CODE_BASE_12 0x0A3C #define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0 @@ -1252,6 +1359,7 @@ #define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_13 */ #define EUR_CR_USE_CODE_BASE_13 0x0A40 #define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0 @@ -1259,6 +1367,7 @@ #define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_14 */ #define EUR_CR_USE_CODE_BASE_14 0x0A44 #define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0 @@ -1266,6 +1375,7 @@ #define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_15 */ #define EUR_CR_USE_CODE_BASE_15 0x0A48 #define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0 @@ -1273,6 +1383,7 @@ #define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0 +/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP */ #define EUR_CR_PIPE0_BREAKPOINT_TRAP 0x0F88 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U #define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 @@ -1280,6 +1391,7 @@ #define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U #define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 +/* Register EUR_CR_PIPE0_BREAKPOINT */ #define EUR_CR_PIPE0_BREAKPOINT 0x0F8C #define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_MASK 0x000003C0U #define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SHIFT 6 @@ -1293,10 +1405,12 @@ #define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_MASK 0x00000004U #define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SHIFT 2 #define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SIGNED 0 +/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 */ #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 0x0F90 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 +/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 */ #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 0x0F94 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 @@ -1313,6 +1427,7 @@ #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 +/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP */ #define EUR_CR_PIPE1_BREAKPOINT_TRAP 0x0F98 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U #define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 @@ -1320,6 +1435,7 @@ #define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U #define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 +/* Register EUR_CR_PIPE1_BREAKPOINT */ #define EUR_CR_PIPE1_BREAKPOINT 0x0F9C #define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_MASK 0x000003C0U #define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SHIFT 6 @@ -1333,10 +1449,12 @@ #define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_MASK 0x00000004U #define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SHIFT 2 #define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SIGNED 0 +/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 */ #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 0x0FA0 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 +/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 */ #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 0x0FA4 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 @@ -1353,6 +1471,8 @@ #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 +/* Table EUR_CR_USE_CODE_BASE */ +/* Register EUR_CR_USE_CODE_BASE */ #define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) #define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 @@ -1360,8 +1480,9 @@ #define EUR_CR_USE_CODE_BASE_DM_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_SIGNED 0 +/* Number of entries in table EUR_CR_USE_CODE_BASE */ #define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 #define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 -#endif +#endif /* _SGX544DEFS_KM_H_ */ diff --git a/sgx/services4/srvkm/hwdefs/sgxdefs.h b/sgx/services4/srvkm/hwdefs/sgxdefs.h index b3a2583..dee7bce 100644 --- a/sgx/services4/srvkm/hwdefs/sgxdefs.h +++ b/sgx/services4/srvkm/hwdefs/sgxdefs.h @@ -1,28 +1,44 @@ -/********************************************************************** - * - * Copyright (C) Imagination Technologies Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful but, except - * as otherwise stated in writing, without any warranty; without even the - * implied warranty of merchantability or fitness for a particular purpose. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - * Contact Information: - * Imagination Technologies Ltd. <gpl-support@imgtec.com> - * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK - * - ******************************************************************************/ +/*************************************************************************/ /*! +@Title SGX hw definitions +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ /**************************************************************************/ #ifndef _SGXDEFS_H_ #define _SGXDEFS_H_ @@ -79,12 +95,19 @@ #include "sgxmpplusdefs.h" #else #include "sgxmpdefs.h" -#endif -#else +#endif /* SGX554 */ +#else /* SGX_FEATURE_MP */ #if defined(SGX_FEATURE_SYSTEM_CACHE) #include "mnemedefs.h" #endif -#endif +#endif /* SGX_FEATURE_MP */ + +/***************************************************************************** + Core specific defines. +*****************************************************************************/ -#endif +#endif /* _SGXDEFS_H_ */ +/***************************************************************************** + End of file (sgxdefs.h) +*****************************************************************************/ diff --git a/sgx/services4/srvkm/hwdefs/sgxerrata.h b/sgx/services4/srvkm/hwdefs/sgxerrata.h index ccfafd5..36d8b30 100644 --- a/sgx/services4/srvkm/hwdefs/sgxerrata.h +++ b/sgx/services4/srvkm/hwdefs/sgxerrata.h @@ -1,215 +1,200 @@ -/********************************************************************** - * - * Copyright (C) Imagination Technologies Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful but, except - * as otherwise stated in writing, without any warranty; without even the - * implied warranty of merchantability or fitness for a particular purpose. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - * Contact Information: - * Imagination Technologies Ltd. <gpl-support@imgtec.com> - * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK - * - ******************************************************************************/ +/*************************************************************************/ /*! +@Title SGX HW errata definitions +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@Description Specifies associations between SGX core revisions + and SW workarounds required to fix HW errata that exist + in specific core revisions +@License Dual MIT/GPLv2 +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ /**************************************************************************/ #ifndef _SGXERRATA_KM_H_ #define _SGXERRATA_KM_H_ +/* ignore warnings about unrecognised preprocessing directives in conditional inclusion directives */ +/* PRQA S 3115 ++ */ + #if defined(SGX520) && !defined(SGX_CORE_DEFINED) - + /* define the _current_ SGX520 RTL head revision */ #define SGX_CORE_REV_HEAD 0 #if defined(USE_SGX_CORE_REV_HEAD) - + /* build config selects Core Revision to be the Head */ #define SGX_CORE_REV SGX_CORE_REV_HEAD #endif - #if SGX_CORE_REV == 100 - #define FIX_HW_BRN_28889 - #else #if SGX_CORE_REV == 111 - #define FIX_HW_BRN_28889 #else #if SGX_CORE_REV == SGX_CORE_REV_HEAD - + /* RTL head - no BRNs to apply */ #else #error "sgxerrata.h: SGX520 Core Revision unspecified" #endif #endif - #endif - + /* signal that the Core Version has a valid definition */ #define SGX_CORE_DEFINED #endif #if defined(SGX530) && !defined(SGX_CORE_DEFINED) - + /* define the _current_ SGX530 RTL head revision */ #define SGX_CORE_REV_HEAD 0 #if defined(USE_SGX_CORE_REV_HEAD) - + /* build config selects Core Revision to be the Head */ #define SGX_CORE_REV SGX_CORE_REV_HEAD #endif - #if SGX_CORE_REV == 110 - #define FIX_HW_BRN_22934 - #define FIX_HW_BRN_28889 - #else - #if SGX_CORE_REV == 111 - #define FIX_HW_BRN_22934 - #define FIX_HW_BRN_28889 - #else - #if SGX_CORE_REV == 1111 - #define FIX_HW_BRN_22934 - #define FIX_HW_BRN_28889 - #else #if SGX_CORE_REV == 120 - #define FIX_HW_BRN_22934 - #define FIX_HW_BRN_28889 + #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ + #define FIX_HW_BRN_28889/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == 121 - #define FIX_HW_BRN_22934 - #define FIX_HW_BRN_28889 + #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ + #define FIX_HW_BRN_28889/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == 125 - #define FIX_HW_BRN_22934 - #define FIX_HW_BRN_28889 + #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ + #define FIX_HW_BRN_28889/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == 130 - #define FIX_HW_BRN_22934 - #define FIX_HW_BRN_28889 + #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ + #define FIX_HW_BRN_28889/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == SGX_CORE_REV_HEAD - + /* RTL head - no BRNs to apply */ #else #error "sgxerrata.h: SGX530 Core Revision unspecified" #endif #endif #endif - #endif - #endif - #endif #endif #endif - + /* signal that the Core Version has a valid definition */ #define SGX_CORE_DEFINED #endif #if defined(SGX531) && !defined(SGX_CORE_DEFINED) - + /* define the _current_ SGX531 RTL head revision */ #define SGX_CORE_REV_HEAD 0 #if defined(USE_SGX_CORE_REV_HEAD) - + /* build config selects Core Revision to be the Head */ #define SGX_CORE_REV SGX_CORE_REV_HEAD #endif #if SGX_CORE_REV == 101 - #define FIX_HW_BRN_26620 - #define FIX_HW_BRN_28011 - #define FIX_HW_BRN_34028 + #define FIX_HW_BRN_26620/* Workaround in services (srvkm) */ + #define FIX_HW_BRN_28011/* Workaround in services (srvkm) */ + #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == 110 - #define FIX_HW_BRN_34028 + #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == SGX_CORE_REV_HEAD - + /* RTL head - no BRNs to apply */ #else #error "sgxerrata.h: SGX531 Core Revision unspecified" #endif #endif #endif - + /* signal that the Core Version has a valid definition */ #define SGX_CORE_DEFINED #endif #if (defined(SGX535) || defined(SGX535_V1_1)) && !defined(SGX_CORE_DEFINED) - + /* define the _current_ SGX535 RTL head revision */ #define SGX_CORE_REV_HEAD 0 #if defined(USE_SGX_CORE_REV_HEAD) - + /* build config selects Core Revision to be the Head */ #define SGX_CORE_REV SGX_CORE_REV_HEAD #endif - #if SGX_CORE_REV == 112 - #define FIX_HW_BRN_23281 - #define FIX_HW_BRN_23410 - #define FIX_HW_BRN_22693 - #define FIX_HW_BRN_22934 - #define FIX_HW_BRN_22997 - #define FIX_HW_BRN_23030 - #else - #if SGX_CORE_REV == 113 - #define FIX_HW_BRN_22934 - #define FIX_HW_BRN_23281 - #define FIX_HW_BRN_23944 - #define FIX_HW_BRN_23410 - #else #if SGX_CORE_REV == 121 - #define FIX_HW_BRN_22934 - #define FIX_HW_BRN_23944 - #define FIX_HW_BRN_23410 + #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ + #define FIX_HW_BRN_23944/* Workaround in code (services) */ + #define FIX_HW_BRN_23410/* Workaround in code (services) and ucode */ #else #if SGX_CORE_REV == 126 - #define FIX_HW_BRN_22934 + #define FIX_HW_BRN_22934/* Workaround in sgx featuredefs */ #else #if SGX_CORE_REV == SGX_CORE_REV_HEAD - + /* RTL head - no BRNs to apply */ #else #error "sgxerrata.h: SGX535 Core Revision unspecified" #endif #endif #endif - #endif - #endif - + /* signal that the Core Version has a valid definition */ #define SGX_CORE_DEFINED #endif #if defined(SGX540) && !defined(SGX_CORE_DEFINED) - + /* define the _current_ SGX540 RTL head revision */ #define SGX_CORE_REV_HEAD 0 #if defined(USE_SGX_CORE_REV_HEAD) - + /* build config selects Core Revision to be the Head */ #define SGX_CORE_REV SGX_CORE_REV_HEAD #endif #if SGX_CORE_REV == 101 - #define FIX_HW_BRN_25499 - #define FIX_HW_BRN_25503 - #define FIX_HW_BRN_26620 - #define FIX_HW_BRN_28011 - #define FIX_HW_BRN_34028 + #define FIX_HW_BRN_25499/* Workaround in sgx featuredefs */ + #define FIX_HW_BRN_25503/* Workaround in code (services) */ + #define FIX_HW_BRN_26620/* Workaround in services (srvkm) */ + #define FIX_HW_BRN_28011/* Workaround in services (srvkm) */ + #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == 110 - #define FIX_HW_BRN_25503 - #define FIX_HW_BRN_26620 - #define FIX_HW_BRN_28011 - #define FIX_HW_BRN_34028 + #define FIX_HW_BRN_25503/* Workaround in code (services) */ + #define FIX_HW_BRN_26620/* Workaround in services (srvkm) */ + #define FIX_HW_BRN_28011/* Workaround in services (srvkm) */ + #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == 120 - #define FIX_HW_BRN_26620 - #define FIX_HW_BRN_28011 - #define FIX_HW_BRN_34028 + #define FIX_HW_BRN_26620/* Workaround in services (srvkm) */ + #define FIX_HW_BRN_28011/* Workaround in services (srvkm) */ + #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == 121 - #define FIX_HW_BRN_28011 - #define FIX_HW_BRN_34028 + #define FIX_HW_BRN_28011/* Workaround in services (srvkm) */ + #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == 130 - #define FIX_HW_BRN_34028 + #define FIX_HW_BRN_34028/* Workaround in services (srvkm) */ #else #if SGX_CORE_REV == SGX_CORE_REV_HEAD - + /* RTL head - no BRNs to apply */ #else #error "sgxerrata.h: SGX540 Core Revision unspecified" #endif @@ -218,243 +203,145 @@ #endif #endif #endif - + /* signal that the Core Version has a valid definition */ #define SGX_CORE_DEFINED #endif -#if defined(SGX541) && !defined(SGX_CORE_DEFINED) - #if defined(SGX_FEATURE_MP) - - #define SGX_CORE_REV_HEAD 0 - #if defined(USE_SGX_CORE_REV_HEAD) - - #define SGX_CORE_REV SGX_CORE_REV_HEAD - #endif - - #if SGX_CORE_REV == 100 - #define FIX_HW_BRN_27270 - #define FIX_HW_BRN_28011 - #define FIX_HW_BRN_27510 - - #else - #if SGX_CORE_REV == SGX_CORE_REV_HEAD - - #else - #error "sgxerrata.h: SGX541 Core Revision unspecified" - #endif - #endif - - #define SGX_CORE_DEFINED - #else - #error "sgxerrata.h: SGX541 only supports MP configs (SGX_FEATURE_MP)" - #endif -#endif #if defined(SGX543) && !defined(SGX_CORE_DEFINED) - + /* define the _current_ SGX543 RTL head revision */ #define SGX_CORE_REV_HEAD 0 #if defined(USE_SGX_CORE_REV_HEAD) - + /* build config selects Core Revision to be the Head */ #define SGX_CORE_REV SGX_CORE_REV_HEAD #endif - #if SGX_CORE_REV == 113 - #define FIX_HW_BRN_29954 - #define FIX_HW_BRN_29997 - #define FIX_HW_BRN_30954 - #define FIX_HW_BRN_31093 - #define FIX_HW_BRN_31195 - #define FIX_HW_BRN_31272 - #define FIX_HW_BRN_31278 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #define FIX_HW_BRN_31620 - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_31542 - #define FIX_HW_BRN_32044 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 - #endif - #define FIX_HW_BRN_33920 - #else #if SGX_CORE_REV == 122 - #define FIX_HW_BRN_29954 - #define FIX_HW_BRN_29997 - #define FIX_HW_BRN_30954 - #define FIX_HW_BRN_31093 - #define FIX_HW_BRN_31195 - #define FIX_HW_BRN_31272 - #define FIX_HW_BRN_31278 + #define FIX_HW_BRN_29954/* turns off regbank split feature */ + #define FIX_HW_BRN_29997/* workaround in services */ + #define FIX_HW_BRN_30954/* workaround in services */ + #define FIX_HW_BRN_31093/* workaround in services */ + #define FIX_HW_BRN_31195/* workaround in services */ + #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ + #define FIX_HW_BRN_31278/* disabled prefetching in MMU */ #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 + #define FIX_HW_BRN_31559/* workaround in services and uKernel */ #endif - #define FIX_HW_BRN_31620 - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_31542 - #define FIX_HW_BRN_32044 - #define FIX_HW_BRN_32085 + #define FIX_HW_BRN_31620/* workaround in services */ + #define FIX_HW_BRN_31780/* workaround in uKernel */ + #define FIX_HW_BRN_31542/* workaround in uKernel and Services */ + #define FIX_HW_BRN_32044 /* workaround in uKernel, services and client drivers */ + #define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */ #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif - #define FIX_HW_BRN_33920 - + #define FIX_HW_BRN_33920/* workaround in ukernel */ + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ + /* add BRNs here */ #else #if SGX_CORE_REV == 1221 - #define FIX_HW_BRN_29954 - #define FIX_HW_BRN_31195 - #define FIX_HW_BRN_31272 - #define FIX_HW_BRN_31278 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #define FIX_HW_BRN_31542 - #define FIX_HW_BRN_31671 - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_32044 - #define FIX_HW_BRN_32085 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 - #endif - #define FIX_HW_BRN_33920 - - #else - #if SGX_CORE_REV == 140 - #define FIX_HW_BRN_29954 - #define FIX_HW_BRN_30954 - #define FIX_HW_BRN_31093 - #define FIX_HW_BRN_31195 - #define FIX_HW_BRN_31272 - #define FIX_HW_BRN_31278 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #define FIX_HW_BRN_31620 - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_31542 - #define FIX_HW_BRN_32044 - #define FIX_HW_BRN_32085 - #define FIX_HW_BRN_33920 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 - #endif - - #else - #if SGX_CORE_REV == 1401 - #define FIX_HW_BRN_29954 - #define FIX_HW_BRN_30954 - #define FIX_HW_BRN_31195 - #define FIX_HW_BRN_31272 - #define FIX_HW_BRN_31278 + #define FIX_HW_BRN_29954/* turns off regbank split feature */ + #define FIX_HW_BRN_31195/* workaround in services */ + #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ + #define FIX_HW_BRN_31278/* disabled prefetching in MMU */ #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 + #define FIX_HW_BRN_31559/* workaround in services and uKernel */ #endif - #define FIX_HW_BRN_31620 - #define FIX_HW_BRN_31542 - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_32044 - #define FIX_HW_BRN_32085 - #define FIX_HW_BRN_33920 + #define FIX_HW_BRN_31542/* workaround in uKernel and Services */ + #define FIX_HW_BRN_31671/* workaround in uKernel */ + #define FIX_HW_BRN_31780/* workaround in uKernel */ + #define FIX_HW_BRN_32044/* workaround in uKernel, services and client drivers */ + #define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */ #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif - + #define FIX_HW_BRN_33920/* workaround in ukernel */ + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ + /* add BRNs here */ #else #if SGX_CORE_REV == 141 - #define FIX_HW_BRN_29954 + #define FIX_HW_BRN_29954/* turns off regbank split feature */ #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 + #define FIX_HW_BRN_31559/* workaround in services and uKernel */ #endif - #define FIX_HW_BRN_31671 - #define FIX_HW_BRN_31780 + #define FIX_HW_BRN_31671 /* workaround in uKernel */ + #define FIX_HW_BRN_31780/* workaround in uKernel */ #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif - + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ + /* add BRNs here */ #else #if SGX_CORE_REV == 142 - #define FIX_HW_BRN_29954 + #define FIX_HW_BRN_29954/* turns off regbank split feature */ #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 + #define FIX_HW_BRN_31559/* workaround in services and uKernel */ #endif - #define FIX_HW_BRN_31671 - #define FIX_HW_BRN_31780 + #define FIX_HW_BRN_31671 /* workaround in uKernel */ + #define FIX_HW_BRN_31780/* workaround in uKernel */ #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif - - #else - #if SGX_CORE_REV == 211 - #define FIX_HW_BRN_31093 - #define FIX_HW_BRN_31195 - #define FIX_HW_BRN_31272 - #define FIX_HW_BRN_31278 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #define FIX_HW_BRN_31620 - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_31542 - #define FIX_HW_BRN_32044 - #define FIX_HW_BRN_32085 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 - #endif - #define FIX_HW_BRN_33920 - + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ + /* add BRNs here */ #else #if SGX_CORE_REV == 2111 - #define FIX_HW_BRN_30982 - #define FIX_HW_BRN_31093 - #define FIX_HW_BRN_31195 - #define FIX_HW_BRN_31272 - #define FIX_HW_BRN_31278 + #define FIX_HW_BRN_30982 /* workaround in uKernel and services */ + #define FIX_HW_BRN_31093/* workaround in services */ + #define FIX_HW_BRN_31195/* workaround in services */ + #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ + #define FIX_HW_BRN_31278/* disabled prefetching in MMU */ #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 + #define FIX_HW_BRN_31559/* workaround in services and uKernel */ #endif - #define FIX_HW_BRN_31620 - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_31542 - #define FIX_HW_BRN_32044 - #define FIX_HW_BRN_32085 + #define FIX_HW_BRN_31620/* workaround in services */ + #define FIX_HW_BRN_31780/* workaround in uKernel */ + #define FIX_HW_BRN_31542/* workaround in uKernel and Services */ + #define FIX_HW_BRN_32044 /* workaround in uKernel, services and client drivers */ + #define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */ #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif - #define FIX_HW_BRN_33920 - + #define FIX_HW_BRN_33920/* workaround in ukernel */ + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ + /* add BRNs here */ #else #if SGX_CORE_REV == 213 - #define FIX_HW_BRN_31272 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 + #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ + #if defined(SGX_FEATURE_MP) + #define FIX_HW_BRN_31559/* workaround in services and uKernel */ #endif - #define FIX_HW_BRN_31671 - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_32085 + #define FIX_HW_BRN_31671 /* workaround in uKernel */ + #define FIX_HW_BRN_31780/* workaround in uKernel */ + #define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */ #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif - #define FIX_HW_BRN_33920 - + #define FIX_HW_BRN_33920/* workaround in ukernel */ + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ + /* add BRNs here */ #else #if SGX_CORE_REV == 216 #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ #else #if SGX_CORE_REV == 302 #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif +// FIXME #define FIX_HW_BRN_36513 /* workaround in uKernel and Services : incomplete for CS and MP1 */ #else #if SGX_CORE_REV == 303 #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif +// FIXME #define FIX_HW_BRN_36513 /* workaround in uKernel and Services : incomplete for CS and MP1 */ #else #if SGX_CORE_REV == SGX_CORE_REV_HEAD #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif #else #error "sgxerrata.h: SGX543 Core Revision unspecified" @@ -468,124 +355,84 @@ #endif #endif #endif - #endif - #endif - #endif - #endif - + /* signal that the Core Version has a valid definition */ #define SGX_CORE_DEFINED #endif #if defined(SGX544) && !defined(SGX_CORE_DEFINED) - + /* define the _current_ SGX544 RTL head revision */ #define SGX_CORE_REV_HEAD 0 #if defined(USE_SGX_CORE_REV_HEAD) - + /* build config selects Core Revision to be the Head */ #define SGX_CORE_REV SGX_CORE_REV_HEAD #endif - #if SGX_CORE_REV == 100 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #else - #if SGX_CORE_REV == 102 - #define FIX_HW_BRN_29954 - #define FIX_HW_BRN_31272 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_32085 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 - #endif - #define FIX_HW_BRN_33920 - #else - #if SGX_CORE_REV == 103 - #define FIX_HW_BRN_29954 - #define FIX_HW_BRN_31272 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_32085 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 - #endif - #define FIX_HW_BRN_33920 - #else #if SGX_CORE_REV == 104 - #define FIX_HW_BRN_29954 - #define FIX_HW_BRN_31093 - #define FIX_HW_BRN_31195 - #define FIX_HW_BRN_31272 - #define FIX_HW_BRN_31278 + #define FIX_HW_BRN_29954/* turns off regbank split feature */ + #define FIX_HW_BRN_31093/* workaround in services */ + #define FIX_HW_BRN_31195/* workaround in services */ + #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ + #define FIX_HW_BRN_31278/* disabled prefetching in MMU */ #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 + #define FIX_HW_BRN_31559/* workaround in services and uKernel */ #endif - #define FIX_HW_BRN_31542 - #define FIX_HW_BRN_31620 - #define FIX_HW_BRN_31671 - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_32044 - #define FIX_HW_BRN_32085 + #define FIX_HW_BRN_31542 /* workaround in uKernel and Services */ + #define FIX_HW_BRN_31620/* workaround in services */ + #define FIX_HW_BRN_31671 /* workaround in uKernel */ + #define FIX_HW_BRN_31780/* workaround in uKernel */ + #define FIX_HW_BRN_32044 /* workaround in uKernel, services and client drivers */ + #define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */ #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif - #define FIX_HW_BRN_33920 + #define FIX_HW_BRN_33920/* workaround in ukernel */ + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ #else #if SGX_CORE_REV == 105 #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 + #define FIX_HW_BRN_31559/* workaround in services and uKernel */ #endif - #define FIX_HW_BRN_31780 + #define FIX_HW_BRN_31780/* workaround in uKernel */ #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif - #define FIX_HW_BRN_33920 - #else - #if SGX_CORE_REV == 106 - #define FIX_HW_BRN_31272 - #define FIX_HW_BRN_31780 - #define FIX_HW_BRN_33920 - #else - #if SGX_CORE_REV == 110 - #define FIX_HW_BRN_31272 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #define FIX_HW_BRN_31780 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 - #endif - #define FIX_HW_BRN_33920 + #define FIX_HW_BRN_33920/* workaround in ukernel */ + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ #else #if SGX_CORE_REV == 112 - #define FIX_HW_BRN_31272 - #define FIX_HW_BRN_33920 + #define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */ + #define FIX_HW_BRN_33920/* workaround in ukernel */ +// FIXME #define FIX_HW_BRN_36513 /* workaround in uKernel and Services : incomplete for CS and MP1 */ #else #if SGX_CORE_REV == 114 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #define FIX_HW_BRN_31780 + #define FIX_HW_BRN_31780/* workaround in uKernel */ #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif +// FIXME #define FIX_HW_BRN_36513 /* workaround in uKernel and Services : incomplete for CS and MP1 */ #else #if SGX_CORE_REV == 115 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #define FIX_HW_BRN_31780 + #define FIX_HW_BRN_31780/* workaround in uKernel */ + #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) + #define FIX_HW_BRN_33657/* workaround in ukernel*/ + #endif +// FIXME BRN_36513 incomplete for CS and MP1 */ + #if defined(SGX_FEATURE_MP) + #if SGX_FEATURE_MP_CORE_COUNT > 1 + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services : incomplete for CS and MP1 */ + #endif + #endif + #else + #if SGX_CORE_REV == 116 #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel */ #endif + #define FIX_HW_BRN_33809/* workaround in kernel (enable burst combiner) */ + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ #else #if SGX_CORE_REV == SGX_CORE_REV_HEAD #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif #else #error "sgxerrata.h: SGX544 Core Revision unspecified" @@ -596,39 +443,22 @@ #endif #endif #endif - #endif - #endif - #endif - #endif - + /* signal that the Core Version has a valid definition */ #define SGX_CORE_DEFINED #endif #if defined(SGX545) && !defined(SGX_CORE_DEFINED) - + /* define the _current_ SGX545 RTL head revision */ #define SGX_CORE_REV_HEAD 0 #if defined(USE_SGX_CORE_REV_HEAD) - + /* build config selects Core Revision to be the Head */ #define SGX_CORE_REV SGX_CORE_REV_HEAD #endif - #if SGX_CORE_REV == 100 - #define FIX_HW_BRN_26620 - #define FIX_HW_BRN_27266 - #define FIX_HW_BRN_27456 - #define FIX_HW_BRN_29702 - #define FIX_HW_BRN_29823 - #else #if SGX_CORE_REV == 109 - #define FIX_HW_BRN_29702 - #define FIX_HW_BRN_29823 - #define FIX_HW_BRN_31939 - #else - #if SGX_CORE_REV == 1012 - #define FIX_HW_BRN_31939 - #else - #if SGX_CORE_REV == 1013 - #define FIX_HW_BRN_31939 + #define FIX_HW_BRN_29702/* Workaround in services */ + #define FIX_HW_BRN_29823/* Workaround in services */ + #define FIX_HW_BRN_31939/* workaround in uKernel */ #else #if SGX_CORE_REV == 10131 #else @@ -637,7 +467,7 @@ #if SGX_CORE_REV == 10141 #else #if SGX_CORE_REV == SGX_CORE_REV_HEAD - + /* RTL head - no BRNs to apply */ #else #error "sgxerrata.h: SGX545 Core Revision unspecified" #endif @@ -645,36 +475,34 @@ #endif #endif #endif - #endif - #endif - #endif - + /* signal that the Core Version has a valid definition */ #define SGX_CORE_DEFINED #endif #if defined(SGX554) && !defined(SGX_CORE_DEFINED) - + /* define the _current_ SGX554 RTL head revision */ #define SGX_CORE_REV_HEAD 0 #if defined(USE_SGX_CORE_REV_HEAD) - + /* build config selects Core Revision to be the Head */ #define SGX_CORE_REV SGX_CORE_REV_HEAD #endif #if SGX_CORE_REV == 1251 #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif - + #define FIX_HW_BRN_36513 /* workaround in uKernel and Services */ + /* add BRNs here */ #else #if SGX_CORE_REV == SGX_CORE_REV_HEAD #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 + #define FIX_HW_BRN_33657/* workaround in ukernel*/ #endif #else #error "sgxerrata.h: SGX554 Core Revision unspecified" #endif #endif - + /* signal that the Core Version has a valid definition */ #define SGX_CORE_DEFINED #endif @@ -686,5 +514,11 @@ #endif #endif -#endif +/* restore warning */ +/* PRQA S 3115 -- */ + +#endif /* _SGXERRATA_KM_H_ */ +/****************************************************************************** + End of file (sgxerrata.h) +******************************************************************************/ diff --git a/sgx/services4/srvkm/hwdefs/sgxfeaturedefs.h b/sgx/services4/srvkm/hwdefs/sgxfeaturedefs.h index 6427e7e..cefa154 100644 --- a/sgx/services4/srvkm/hwdefs/sgxfeaturedefs.h +++ b/sgx/services4/srvkm/hwdefs/sgxfeaturedefs.h @@ -1,29 +1,44 @@ -/********************************************************************** - * - * Copyright (C) Imagination Technologies Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful but, except - * as otherwise stated in writing, without any warranty; without even the - * implied warranty of merchantability or fitness for a particular purpose. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - * Contact Information: - * Imagination Technologies Ltd. <gpl-support@imgtec.com> - * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK - * - ******************************************************************************/ +/*************************************************************************/ /*! +@Title SGX fexture definitions +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@License Dual MIT/GPLv2 +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ /**************************************************************************/ #if defined(SGX520) #define SGX_CORE_FRIENDLY_NAME "SGX520" #define SGX_CORE_ID SGX_CORE_ID_520 @@ -105,13 +120,18 @@ #define SGX_FEATURE_AUTOCLOCKGATING #define SGX_FEATURE_MONOLITHIC_UKERNEL #define SGX_FEATURE_MULTI_EVENT_KICK +// #define SGX_FEATURE_DATA_BREAKPOINTS +// #define SGX_FEATURE_PERPIPE_BKPT_REGS +// #define SGX_FEATURE_PERPIPE_BKPT_REGS_NUMPIPES (2) +// #define SGX_FEATURE_2D_HARDWARE +// #define SGX_FEATURE_PTLA #define SGX_FEATURE_EXTENDED_PERF_COUNTERS #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) #if defined(SGX_FEATURE_MP) #define SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH - #endif #define SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH + #endif #define SGX_FEATURE_SW_ISP_CONTEXT_SWITCH #endif #else @@ -136,8 +156,8 @@ #define SGX_FEATURE_MAX_TA_RENDER_TARGETS (512) #define SGX_FEATURE_SECONDARY_REQUIRES_USE_KICK #define SGX_FEATURE_WRITEBACK_DCU - - + //FIXME: this is defined in the build config for now + //#define SGX_FEATURE_36BIT_MMU #define SGX_FEATURE_BIF_WIDE_TILING_AND_4K_ADDRESS #define SGX_FEATURE_MULTI_EVENT_KICK #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE @@ -157,6 +177,9 @@ #define SGX_FEATURE_AUTOCLOCKGATING #define SGX_FEATURE_MONOLITHIC_UKERNEL #define SGX_FEATURE_MULTI_EVENT_KICK +// #define SGX_FEATURE_DATA_BREAKPOINTS +// #define SGX_FEATURE_PERPIPE_BKPT_REGS +// #define SGX_FEATURE_PERPIPE_BKPT_REGS_NUMPIPES (2) #define SGX_FEATURE_2D_HARDWARE #define SGX_FEATURE_PTLA #define SGX_FEATURE_EXTENDED_PERF_COUNTERS @@ -180,21 +203,18 @@ #if defined(SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH) \ || defined(SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH) +/* Enable the define so common code for HW VDMCS code is compiled */ #define SGX_FEATURE_VDM_CONTEXT_SWITCH #endif -#if defined(FIX_HW_BRN_22693) -#undef SGX_FEATURE_AUTOCLOCKGATING -#endif +/* + 'switch-off' features if defined BRNs affect the feature +*/ #if defined(FIX_HW_BRN_27266) #undef SGX_FEATURE_36BIT_MMU #endif -#if defined(FIX_HW_BRN_27456) -#undef SGX_FEATURE_BIF_WIDE_TILING_AND_4K_ADDRESS -#endif - #if defined(FIX_HW_BRN_22934) \ || defined(FIX_HW_BRN_25499) #undef SGX_FEATURE_MULTI_EVENT_KICK @@ -218,11 +238,16 @@ #undef SGX_FEATURE_BIF_NUM_DIRLISTS #endif +/* + Derive other definitions: +*/ + +/* define default MP core count */ #if defined(SGX_FEATURE_MP) #if defined(SGX_FEATURE_MP_CORE_COUNT_TA) && defined(SGX_FEATURE_MP_CORE_COUNT_3D) #if (SGX_FEATURE_MP_CORE_COUNT_TA > SGX_FEATURE_MP_CORE_COUNT_3D) #error Number of TA cores larger than number of 3D cores not supported in current driver -#endif +#endif /* (SGX_FEATURE_MP_CORE_COUNT_TA > SGX_FEATURE_MP_CORE_COUNT_3D) */ #else #if defined(SGX_FEATURE_MP_CORE_COUNT) #define SGX_FEATURE_MP_CORE_COUNT_TA (SGX_FEATURE_MP_CORE_COUNT) @@ -231,13 +256,13 @@ #error Either SGX_FEATURE_MP_CORE_COUNT or \ both SGX_FEATURE_MP_CORE_COUNT_TA and SGX_FEATURE_MP_CORE_COUNT_3D \ must be defined when SGX_FEATURE_MP is defined -#endif -#endif +#endif /* SGX_FEATURE_MP_CORE_COUNT */ +#endif /* defined(SGX_FEATURE_MP_CORE_COUNT_TA) && defined(SGX_FEATURE_MP_CORE_COUNT_3D) */ #else #define SGX_FEATURE_MP_CORE_COUNT (1) #define SGX_FEATURE_MP_CORE_COUNT_TA (1) #define SGX_FEATURE_MP_CORE_COUNT_3D (1) -#endif +#endif /* SGX_FEATURE_MP */ #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && !defined(SUPPORT_SGX_PRIORITY_SCHEDULING) #define SUPPORT_SGX_PRIORITY_SCHEDULING @@ -245,3 +270,6 @@ must be defined when SGX_FEATURE_MP is defined #include "img_types.h" +/****************************************************************************** + End of file (sgxfeaturedefs.h) +******************************************************************************/ diff --git a/sgx/services4/srvkm/hwdefs/sgxmmu.h b/sgx/services4/srvkm/hwdefs/sgxmmu.h index 1b265f1..509fa5a 100644 --- a/sgx/services4/srvkm/hwdefs/sgxmmu.h +++ b/sgx/services4/srvkm/hwdefs/sgxmmu.h @@ -1,40 +1,62 @@ -/********************************************************************** - * - * Copyright (C) Imagination Technologies Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful but, except - * as otherwise stated in writing, without any warranty; without even the - * implied warranty of merchantability or fitness for a particular purpose. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - * Contact Information: - * Imagination Technologies Ltd. <gpl-support@imgtec.com> - * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK - * - ******************************************************************************/ +/*************************************************************************/ /*! +@Title SGX MMU defines +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@Description Provides SGX MMU declarations and macros +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ /**************************************************************************/ #if !defined(__SGXMMU_KM_H__) #define __SGXMMU_KM_H__ +/* to be implemented */ + +/* SGX MMU maps 4Kb pages */ #define SGX_MMU_PAGE_SHIFT (12) #define SGX_MMU_PAGE_SIZE (1U<<SGX_MMU_PAGE_SHIFT) #define SGX_MMU_PAGE_MASK (SGX_MMU_PAGE_SIZE - 1U) +/* PD details */ #define SGX_MMU_PD_SHIFT (10) #define SGX_MMU_PD_SIZE (1U<<SGX_MMU_PD_SHIFT) #define SGX_MMU_PD_MASK (0xFFC00000U) +/* PD Entry details */ #if defined(SGX_FEATURE_36BIT_MMU) #define SGX_MMU_PDE_ADDR_MASK (0xFFFFFF00U) #define SGX_MMU_PDE_ADDR_ALIGNSHIFT (4) @@ -43,6 +65,7 @@ #define SGX_MMU_PDE_ADDR_ALIGNSHIFT (0) #endif #define SGX_MMU_PDE_VALID (0x00000001U) +/* variable page size control field */ #define SGX_MMU_PDE_PAGE_SIZE_4K (0x00000000U) #define SGX_MMU_PDE_PAGE_SIZE_16K (0x00000002U) #define SGX_MMU_PDE_PAGE_SIZE_64K (0x00000004U) @@ -51,10 +74,12 @@ #define SGX_MMU_PDE_PAGE_SIZE_4M (0x0000000AU) #define SGX_MMU_PDE_PAGE_SIZE_MASK (0x0000000EU) +/* PT details */ #define SGX_MMU_PT_SHIFT (10) #define SGX_MMU_PT_SIZE (1U<<SGX_MMU_PT_SHIFT) #define SGX_MMU_PT_MASK (0x003FF000U) +/* PT Entry details */ #if defined(SGX_FEATURE_36BIT_MMU) #define SGX_MMU_PTE_ADDR_MASK (0xFFFFFF00U) #define SGX_MMU_PTE_ADDR_ALIGNSHIFT (4) @@ -68,5 +93,8 @@ #define SGX_MMU_PTE_CACHECONSISTENT (0x00000008U) #define SGX_MMU_PTE_EDMPROTECT (0x00000010U) -#endif +#endif /* __SGXMMU_KM_H__ */ +/***************************************************************************** + End of file (sgxmmu.h) +*****************************************************************************/ diff --git a/sgx/services4/srvkm/hwdefs/sgxmpdefs.h b/sgx/services4/srvkm/hwdefs/sgxmpdefs.h index e34561a..4186731 100644 --- a/sgx/services4/srvkm/hwdefs/sgxmpdefs.h +++ b/sgx/services4/srvkm/hwdefs/sgxmpdefs.h @@ -1,32 +1,49 @@ -/********************************************************************** - * - * Copyright (C) Imagination Technologies Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful but, except - * as otherwise stated in writing, without any warranty; without even the - * implied warranty of merchantability or fitness for a particular purpose. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - * Contact Information: - * Imagination Technologies Ltd. <gpl-support@imgtec.com> - * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK - * - ******************************************************************************/ +/*************************************************************************/ /*! +@Title Hardware defs for SGXMP. +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@License Dual MIT/GPLv2 -#ifndef _SGXMPDEFS_H_ -#define _SGXMPDEFS_H_ +The contents of this file are subject to the MIT license as set out below. +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ /**************************************************************************/ + +#ifndef _SGXMPDEFS_KM_H_ +#define _SGXMPDEFS_KM_H_ + +/* Register EUR_CR_MASTER_BIF_CTRL */ #define EUR_CR_MASTER_BIF_CTRL 0x4C00 #define EUR_CR_MASTER_BIF_CTRL_NOREORDER_MASK 0x00000001U #define EUR_CR_MASTER_BIF_CTRL_NOREORDER_SHIFT 0 @@ -49,6 +66,7 @@ #define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U #define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19 #define EUR_CR_MASTER_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0 +/* Register EUR_CR_MASTER_BIF_CTRL_INVAL */ #define EUR_CR_MASTER_BIF_CTRL_INVAL 0x4C34 #define EUR_CR_MASTER_BIF_CTRL_INVAL_PTE_MASK 0x00000004U #define EUR_CR_MASTER_BIF_CTRL_INVAL_PTE_SHIFT 2 @@ -56,6 +74,7 @@ #define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_MASK 0x00000008U #define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_SHIFT 3 #define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_SIGNED 0 +/* Register EUR_CR_MASTER_BIF_MMU_CTRL */ #define EUR_CR_MASTER_BIF_MMU_CTRL 0x4CD0 #define EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U #define EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0 @@ -66,6 +85,7 @@ #define EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U #define EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4 #define EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0 +/* Register EUR_CR_MASTER_SLC_CTRL */ #define EUR_CR_MASTER_SLC_CTRL 0x4D00 #define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK 0x00800000U #define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_SHIFT 23 @@ -97,6 +117,7 @@ #define EUR_CR_MASTER_SLC_CTRL_PAUSE_MASK 0x00000100U #define EUR_CR_MASTER_SLC_CTRL_PAUSE_SHIFT 8 #define EUR_CR_MASTER_SLC_CTRL_PAUSE_SIGNED 0 +/* Register EUR_CR_MASTER_SLC_CTRL_BYPASS */ #define EUR_CR_MASTER_SLC_CTRL_BYPASS 0x4D04 #define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_N_MASK 0x08000000U #define EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_N_SHIFT 27 @@ -182,10 +203,12 @@ #define EUR_CR_MASTER_SLC_CTRL_BYPASS_ALL_MASK 0x00000001U #define EUR_CR_MASTER_SLC_CTRL_BYPASS_ALL_SHIFT 0 #define EUR_CR_MASTER_SLC_CTRL_BYPASS_ALL_SIGNED 0 +/* Register EUR_CR_MASTER_SLC_CTRL_USSE_INVAL */ #define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL 0x4D08 #define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_ADDR_MASK 0xFFFFFFFFU #define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_ADDR_SHIFT 0 #define EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_ADDR_SIGNED 0 +/* Register EUR_CR_MASTER_SLC_CTRL_INVAL */ #define EUR_CR_MASTER_SLC_CTRL_INVAL 0x4D28 #define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_EVENT_MASK 0x00000008U #define EUR_CR_MASTER_SLC_CTRL_INVAL_DM_EVENT_SHIFT 3 @@ -199,6 +222,7 @@ #define EUR_CR_MASTER_SLC_CTRL_INVAL_ALL_MASK 0x00000001U #define EUR_CR_MASTER_SLC_CTRL_INVAL_ALL_SHIFT 0 #define EUR_CR_MASTER_SLC_CTRL_INVAL_ALL_SIGNED 0 +/* Register EUR_CR_MASTER_SLC_CTRL_FLUSH */ #define EUR_CR_MASTER_SLC_CTRL_FLUSH 0x4D2C #define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_EVENT_MASK 0x00000080U #define EUR_CR_MASTER_SLC_CTRL_FLUSH_DM_EVENT_SHIFT 7 @@ -212,6 +236,7 @@ #define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_MASK 0x00000010U #define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_SHIFT 4 #define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_SIGNED 0 +/* Register EUR_CR_MASTER_SLC_CTRL_FLUSH_INV */ #define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV 0x4D34 #define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_EVENT_MASK 0x00000080U #define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_EVENT_SHIFT 7 @@ -225,10 +250,12 @@ #define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_ALL_MASK 0x00000010U #define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_ALL_SHIFT 4 #define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_ALL_SIGNED 0 +/* Register EUR_CR_MASTER_BREAKPOINT_READ */ #define EUR_CR_MASTER_BREAKPOINT_READ 0x4F18 #define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_SHIFT 4 #define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_SIGNED 0 +/* Register EUR_CR_MASTER_BREAKPOINT_TRAP */ #define EUR_CR_MASTER_BREAKPOINT_TRAP 0x4F1C #define EUR_CR_MASTER_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U #define EUR_CR_MASTER_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 @@ -236,6 +263,7 @@ #define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U #define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 #define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 +/* Register EUR_CR_MASTER_BREAKPOINT */ #define EUR_CR_MASTER_BREAKPOINT 0x4F20 #define EUR_CR_MASTER_BREAKPOINT_ID_MASK 0x00000030U #define EUR_CR_MASTER_BREAKPOINT_ID_SHIFT 4 @@ -246,10 +274,12 @@ #define EUR_CR_MASTER_BREAKPOINT_TRAPPED_MASK 0x00000004U #define EUR_CR_MASTER_BREAKPOINT_TRAPPED_SHIFT 2 #define EUR_CR_MASTER_BREAKPOINT_TRAPPED_SIGNED 0 +/* Register EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0 */ #define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0 0x4F24 #define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 #define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 +/* Register EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1 */ #define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1 0x4F28 #define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U #define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 @@ -266,10 +296,12 @@ #define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U #define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 #define EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 +/* Register EUR_CR_MASTER_CORE */ #define EUR_CR_MASTER_CORE 0x4000 #define EUR_CR_MASTER_CORE_ENABLE_MASK 0x00000003U #define EUR_CR_MASTER_CORE_ENABLE_SHIFT 0 #define EUR_CR_MASTER_CORE_ENABLE_SIGNED 0 +/* Register EUR_CR_MASTER_CORE_ID */ #define EUR_CR_MASTER_CORE_ID 0x4010 #define EUR_CR_MASTER_CORE_ID_CONFIG_MULTI_MASK 0x00000001U #define EUR_CR_MASTER_CORE_ID_CONFIG_MULTI_SHIFT 0 @@ -289,6 +321,7 @@ #define EUR_CR_MASTER_CORE_ID_ID_MASK 0xFFFF0000U #define EUR_CR_MASTER_CORE_ID_ID_SHIFT 16 #define EUR_CR_MASTER_CORE_ID_ID_SIGNED 0 +/* Register EUR_CR_MASTER_CORE_REVISION */ #define EUR_CR_MASTER_CORE_REVISION 0x4014 #define EUR_CR_MASTER_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU #define EUR_CR_MASTER_CORE_REVISION_MAINTENANCE_SHIFT 0 @@ -302,6 +335,7 @@ #define EUR_CR_MASTER_CORE_REVISION_DESIGNER_MASK 0xFF000000U #define EUR_CR_MASTER_CORE_REVISION_DESIGNER_SHIFT 24 #define EUR_CR_MASTER_CORE_REVISION_DESIGNER_SIGNED 0 +/* Register EUR_CR_MASTER_SOFT_RESET */ #define EUR_CR_MASTER_SOFT_RESET 0x4080 #define EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(i) (0x00000001U << (0 + ((i) * 1))) #define EUR_CR_MASTER_SOFT_RESET_CORE_RESET_SHIFT(i) (0 + ((i) * 1)) @@ -328,5 +362,5 @@ #define EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_SHIFT 10 #define EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_SIGNED 0 -#endif +#endif /* _SGXMPDEFS_KM_H_ */ |