diff options
Diffstat (limited to 'sgx/services4/srvkm/hwdefs/sgx544defs.h')
| -rw-r--r-- | sgx/services4/srvkm/hwdefs/sgx544defs.h | 173 |
1 files changed, 147 insertions, 26 deletions
diff --git a/sgx/services4/srvkm/hwdefs/sgx544defs.h b/sgx/services4/srvkm/hwdefs/sgx544defs.h index c18b8ad..c35a259 100644 --- a/sgx/services4/srvkm/hwdefs/sgx544defs.h +++ b/sgx/services4/srvkm/hwdefs/sgx544defs.h @@ -1,32 +1,49 @@ -/********************************************************************** - * - * Copyright (C) Imagination Technologies Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful but, except - * as otherwise stated in writing, without any warranty; without even the - * implied warranty of merchantability or fitness for a particular purpose. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - * Contact Information: - * Imagination Technologies Ltd. <gpl-support@imgtec.com> - * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK - * - ******************************************************************************/ +/*************************************************************************/ /*! +@Title Hardware defs for SGX544. +@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved +@License Dual MIT/GPLv2 + +The contents of this file are subject to the MIT license as set out below. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +Alternatively, the contents of this file may be used under the terms of +the GNU General Public License Version 2 ("GPL") in which case the provisions +of GPL are applicable instead of those above. + +If you wish to allow use of your version of this file only under the terms of +GPL, and not to allow others to use your version of this file under the terms +of the MIT license, indicate your decision by deleting the provisions above +and replace them with the notice and other provisions required by GPL as set +out in the file called "GPL-COPYING" included in this distribution. If you do +not delete the provisions above, a recipient may use your version of this file +under the terms of either the MIT license or GPL. + +This License is also included in this distribution in the file called +"MIT-COPYING". + +EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS +PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ /**************************************************************************/ #ifndef _SGX544DEFS_KM_H_ #define _SGX544DEFS_KM_H_ +/* Register EUR_CR_CLKGATECTL */ #define EUR_CR_CLKGATECTL 0x0000 #define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U #define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0 @@ -67,6 +84,7 @@ #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28 #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SIGNED 0 +/* Register EUR_CR_CLKGATECTL2 */ #define EUR_CR_CLKGATECTL2 0x0004 #define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U #define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0 @@ -104,6 +122,7 @@ #define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_MASK 0x0C000000U #define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SHIFT 26 #define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SIGNED 0 +/* Register EUR_CR_CLKGATESTATUS */ #define EUR_CR_CLKGATESTATUS 0x0008 #define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U #define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0 @@ -174,6 +193,7 @@ #define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_MASK 0x01000000U #define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SHIFT 24 #define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SIGNED 0 +/* Register EUR_CR_CLKGATECTLOVR */ #define EUR_CR_CLKGATECTLOVR 0x000C #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 @@ -208,10 +228,12 @@ #define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_MASK 0x00300000U #define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SHIFT 20 #define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SIGNED 0 +/* Register EUR_CR_POWER */ #define EUR_CR_POWER 0x001C #define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U #define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0 #define EUR_CR_POWER_PIPE_DISABLE_SIGNED 0 +/* Register EUR_CR_CORE_ID */ #define EUR_CR_CORE_ID 0x0020 #define EUR_CR_CORE_ID_CONFIG_MULTI_MASK 0x00000001U #define EUR_CR_CORE_ID_CONFIG_MULTI_SHIFT 0 @@ -231,6 +253,7 @@ #define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U #define EUR_CR_CORE_ID_ID_SHIFT 16 #define EUR_CR_CORE_ID_ID_SIGNED 0 +/* Register EUR_CR_CORE_REVISION */ #define EUR_CR_CORE_REVISION 0x0024 #define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU #define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 @@ -244,14 +267,17 @@ #define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U #define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 #define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0 +/* Register EUR_CR_DESIGNER_REV_FIELD1 */ #define EUR_CR_DESIGNER_REV_FIELD1 0x0028 #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0 +/* Register EUR_CR_DESIGNER_REV_FIELD2 */ #define EUR_CR_DESIGNER_REV_FIELD2 0x002C #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0 +/* Register EUR_CR_SOFT_RESET */ #define EUR_CR_SOFT_RESET 0x0080 #define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U #define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 @@ -310,6 +336,7 @@ #define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK 0x00080000U #define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SHIFT 19 #define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SIGNED 0 +/* Register EUR_CR_EVENT_HOST_ENABLE2 */ #define EUR_CR_EVENT_HOST_ENABLE2 0x0110 #define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U #define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 @@ -347,6 +374,7 @@ #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0 +/* Register EUR_CR_EVENT_HOST_CLEAR2 */ #define EUR_CR_EVENT_HOST_CLEAR2 0x0114 #define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U #define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 @@ -384,6 +412,7 @@ #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0 +/* Register EUR_CR_EVENT_STATUS2 */ #define EUR_CR_EVENT_STATUS2 0x0118 #define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U #define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 @@ -421,6 +450,7 @@ #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0 +/* Register EUR_CR_EVENT_STATUS */ #define EUR_CR_EVENT_STATUS 0x012C #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 @@ -506,6 +536,7 @@ #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0 +/* Register EUR_CR_EVENT_HOST_ENABLE */ #define EUR_CR_EVENT_HOST_ENABLE 0x0130 #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 @@ -591,6 +622,7 @@ #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0 +/* Register EUR_CR_EVENT_HOST_CLEAR */ #define EUR_CR_EVENT_HOST_CLEAR 0x0134 #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 @@ -676,26 +708,32 @@ #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0 +/* Register EUR_CR_TIMER */ #define EUR_CR_TIMER 0x0144 #define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU #define EUR_CR_TIMER_VALUE_SHIFT 0 #define EUR_CR_TIMER_VALUE_SIGNED 0 +/* Register EUR_CR_EVENT_KICK1 */ #define EUR_CR_EVENT_KICK1 0x0AB0 #define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU #define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 #define EUR_CR_EVENT_KICK1_NOW_SIGNED 0 +/* Register EUR_CR_EVENT_KICK2 */ #define EUR_CR_EVENT_KICK2 0x0AC0 #define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U #define EUR_CR_EVENT_KICK2_NOW_SHIFT 0 #define EUR_CR_EVENT_KICK2_NOW_SIGNED 0 +/* Register EUR_CR_EVENT_KICKER */ #define EUR_CR_EVENT_KICKER 0x0AC4 #define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 #define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0 +/* Register EUR_CR_EVENT_KICK */ #define EUR_CR_EVENT_KICK 0x0AC8 #define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U #define EUR_CR_EVENT_KICK_NOW_SHIFT 0 #define EUR_CR_EVENT_KICK_NOW_SIGNED 0 +/* Register EUR_CR_EVENT_TIMER */ #define EUR_CR_EVENT_TIMER 0x0ACC #define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U #define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 @@ -703,26 +741,32 @@ #define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU #define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 #define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0 +/* Register EUR_CR_PDS_INV0 */ #define EUR_CR_PDS_INV0 0x0AD0 #define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV0_DSC_SHIFT 0 #define EUR_CR_PDS_INV0_DSC_SIGNED 0 +/* Register EUR_CR_PDS_INV1 */ #define EUR_CR_PDS_INV1 0x0AD4 #define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV1_DSC_SHIFT 0 #define EUR_CR_PDS_INV1_DSC_SIGNED 0 +/* Register EUR_CR_EVENT_KICK3 */ #define EUR_CR_EVENT_KICK3 0x0AD8 #define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U #define EUR_CR_EVENT_KICK3_NOW_SHIFT 0 #define EUR_CR_EVENT_KICK3_NOW_SIGNED 0 +/* Register EUR_CR_PDS_INV3 */ #define EUR_CR_PDS_INV3 0x0ADC #define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U #define EUR_CR_PDS_INV3_DSC_SHIFT 0 #define EUR_CR_PDS_INV3_DSC_SIGNED 0 +/* Register EUR_CR_PDS_INV_CSC */ #define EUR_CR_PDS_INV_CSC 0x0AE0 #define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U #define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 #define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0 +/* Register EUR_CR_BIF_CTRL */ #define EUR_CR_BIF_CTRL 0x0C00 #define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U #define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 @@ -763,6 +807,7 @@ #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19 #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0 +/* Register EUR_CR_BIF_INT_STAT */ #define EUR_CR_BIF_INT_STAT 0x0C04 #define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x00003FFFU #define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0 @@ -773,6 +818,7 @@ #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19 #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0 +/* Register EUR_CR_BIF_FAULT */ #define EUR_CR_BIF_FAULT 0x0C08 #define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU #define EUR_CR_BIF_FAULT_CID_SHIFT 0 @@ -783,6 +829,7 @@ #define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 #define EUR_CR_BIF_FAULT_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_TILE0 */ #define EUR_CR_BIF_TILE0 0x0C0C #define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0 @@ -793,6 +840,7 @@ #define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE0_CFG_SHIFT 24 #define EUR_CR_BIF_TILE0_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE1 */ #define EUR_CR_BIF_TILE1 0x0C10 #define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0 @@ -803,6 +851,7 @@ #define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE1_CFG_SHIFT 24 #define EUR_CR_BIF_TILE1_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE2 */ #define EUR_CR_BIF_TILE2 0x0C14 #define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0 @@ -813,6 +862,7 @@ #define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE2_CFG_SHIFT 24 #define EUR_CR_BIF_TILE2_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE3 */ #define EUR_CR_BIF_TILE3 0x0C18 #define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0 @@ -823,6 +873,7 @@ #define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE3_CFG_SHIFT 24 #define EUR_CR_BIF_TILE3_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE4 */ #define EUR_CR_BIF_TILE4 0x0C1C #define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0 @@ -833,6 +884,7 @@ #define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE4_CFG_SHIFT 24 #define EUR_CR_BIF_TILE4_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE5 */ #define EUR_CR_BIF_TILE5 0x0C20 #define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0 @@ -843,6 +895,7 @@ #define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE5_CFG_SHIFT 24 #define EUR_CR_BIF_TILE5_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE6 */ #define EUR_CR_BIF_TILE6 0x0C24 #define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0 @@ -853,6 +906,7 @@ #define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE6_CFG_SHIFT 24 #define EUR_CR_BIF_TILE6_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE7 */ #define EUR_CR_BIF_TILE7 0x0C28 #define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0 @@ -863,6 +917,7 @@ #define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE7_CFG_SHIFT 24 #define EUR_CR_BIF_TILE7_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE8 */ #define EUR_CR_BIF_TILE8 0x0C2C #define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0 @@ -873,6 +928,7 @@ #define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE8_CFG_SHIFT 24 #define EUR_CR_BIF_TILE8_CFG_SIGNED 0 +/* Register EUR_CR_BIF_TILE9 */ #define EUR_CR_BIF_TILE9 0x0C30 #define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU #define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0 @@ -883,6 +939,7 @@ #define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U #define EUR_CR_BIF_TILE9_CFG_SHIFT 24 #define EUR_CR_BIF_TILE9_CFG_SIGNED 0 +/* Register EUR_CR_BIF_CTRL_INVAL */ #define EUR_CR_BIF_CTRL_INVAL 0x0C34 #define EUR_CR_BIF_CTRL_INVAL_PTE_MASK 0x00000004U #define EUR_CR_BIF_CTRL_INVAL_PTE_SHIFT 2 @@ -890,34 +947,42 @@ #define EUR_CR_BIF_CTRL_INVAL_ALL_MASK 0x00000008U #define EUR_CR_BIF_CTRL_INVAL_ALL_SHIFT 3 #define EUR_CR_BIF_CTRL_INVAL_ALL_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE1 */ #define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38 #define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE2 */ #define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C #define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE3 */ #define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40 #define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE4 */ #define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44 #define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE5 */ #define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48 #define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE6 */ #define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C #define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE7 */ #define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50 #define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_BANK_SET */ #define EUR_CR_BIF_BANK_SET 0x0C74 #define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U #define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0 @@ -937,6 +1002,7 @@ #define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U #define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9 #define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0 +/* Register EUR_CR_BIF_BANK0 */ #define EUR_CR_BIF_BANK0 0x0C78 #define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU #define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0 @@ -950,6 +1016,7 @@ #define EUR_CR_BIF_BANK0_INDEX_PTLA_MASK 0x000F0000U #define EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT 16 #define EUR_CR_BIF_BANK0_INDEX_PTLA_SIGNED 0 +/* Register EUR_CR_BIF_BANK1 */ #define EUR_CR_BIF_BANK1 0x0C7C #define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU #define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0 @@ -960,26 +1027,32 @@ #define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U #define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12 #define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0 +/* Register EUR_CR_BIF_DIR_LIST_BASE0 */ #define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_TA_REQ_BASE */ #define EUR_CR_BIF_TA_REQ_BASE 0x0C90 #define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U #define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 #define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_MEM_REQ_STAT */ #define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 #define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU #define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 #define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0 +/* Register EUR_CR_BIF_3D_REQ_BASE */ #define EUR_CR_BIF_3D_REQ_BASE 0x0CAC #define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U #define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 #define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_ZLS_REQ_BASE */ #define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0 +/* Register EUR_CR_BIF_BANK_STATUS */ #define EUR_CR_BIF_BANK_STATUS 0x0CB4 #define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U #define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0 @@ -987,6 +1060,7 @@ #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0 +/* Register EUR_CR_BIF_MMU_CTRL */ #define EUR_CR_BIF_MMU_CTRL 0x0CD0 #define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U #define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0 @@ -1003,6 +1077,7 @@ #define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_MASK 0x00000020U #define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SHIFT 5 #define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SIGNED 0 +/* Register EUR_CR_2D_BLIT_STATUS */ #define EUR_CR_2D_BLIT_STATUS 0x0E04 #define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU #define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 @@ -1010,6 +1085,7 @@ #define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U #define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 #define EUR_CR_2D_BLIT_STATUS_BUSY_SIGNED 0 +/* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ #define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 @@ -1023,6 +1099,7 @@ #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SIGNED 0 +/* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ #define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 @@ -1033,14 +1110,17 @@ #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SIGNED 0 +/* Register EUR_CR_BREAKPOINT0_START */ #define EUR_CR_BREAKPOINT0_START 0x0F44 #define EUR_CR_BREAKPOINT0_START_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT0_START_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT0_START_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT0_END */ #define EUR_CR_BREAKPOINT0_END 0x0F48 #define EUR_CR_BREAKPOINT0_END_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT0_END_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT0_END_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT0 */ #define EUR_CR_BREAKPOINT0 0x0F4C #define EUR_CR_BREAKPOINT0_MASK_DM_MASK 0x00000038U #define EUR_CR_BREAKPOINT0_MASK_DM_SHIFT 3 @@ -1054,14 +1134,17 @@ #define EUR_CR_BREAKPOINT0_CTRL_RENABLE_MASK 0x00000001U #define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SHIFT 0 #define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SIGNED 0 +/* Register EUR_CR_BREAKPOINT1_START */ #define EUR_CR_BREAKPOINT1_START 0x0F50 #define EUR_CR_BREAKPOINT1_START_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT1_START_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT1_START_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT1_END */ #define EUR_CR_BREAKPOINT1_END 0x0F54 #define EUR_CR_BREAKPOINT1_END_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT1_END_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT1_END_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT1 */ #define EUR_CR_BREAKPOINT1 0x0F58 #define EUR_CR_BREAKPOINT1_MASK_DM_MASK 0x00000038U #define EUR_CR_BREAKPOINT1_MASK_DM_SHIFT 3 @@ -1075,14 +1158,17 @@ #define EUR_CR_BREAKPOINT1_CTRL_RENABLE_MASK 0x00000001U #define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SHIFT 0 #define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SIGNED 0 +/* Register EUR_CR_BREAKPOINT2_START */ #define EUR_CR_BREAKPOINT2_START 0x0F5C #define EUR_CR_BREAKPOINT2_START_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT2_START_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT2_START_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT2_END */ #define EUR_CR_BREAKPOINT2_END 0x0F60 #define EUR_CR_BREAKPOINT2_END_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT2_END_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT2_END_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT2 */ #define EUR_CR_BREAKPOINT2 0x0F64 #define EUR_CR_BREAKPOINT2_MASK_DM_MASK 0x00000038U #define EUR_CR_BREAKPOINT2_MASK_DM_SHIFT 3 @@ -1096,14 +1182,17 @@ #define EUR_CR_BREAKPOINT2_CTRL_RENABLE_MASK 0x00000001U #define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SHIFT 0 #define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SIGNED 0 +/* Register EUR_CR_BREAKPOINT3_START */ #define EUR_CR_BREAKPOINT3_START 0x0F68 #define EUR_CR_BREAKPOINT3_START_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT3_START_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT3_START_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT3_END */ #define EUR_CR_BREAKPOINT3_END 0x0F6C #define EUR_CR_BREAKPOINT3_END_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT3_END_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT3_END_ADDRESS_SIGNED 0 +/* Register EUR_CR_BREAKPOINT3 */ #define EUR_CR_BREAKPOINT3 0x0F70 #define EUR_CR_BREAKPOINT3_MASK_DM_MASK 0x00000038U #define EUR_CR_BREAKPOINT3_MASK_DM_SHIFT 3 @@ -1117,10 +1206,12 @@ #define EUR_CR_BREAKPOINT3_CTRL_RENABLE_MASK 0x00000001U #define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SHIFT 0 #define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SIGNED 0 +/* Register EUR_CR_BREAKPOINT_READ */ #define EUR_CR_BREAKPOINT_READ 0x0F74 #define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4 #define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0 +/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP */ #define EUR_CR_PARTITION_BREAKPOINT_TRAP 0x0F78 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U #define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 @@ -1128,6 +1219,7 @@ #define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U #define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 +/* Register EUR_CR_PARTITION_BREAKPOINT */ #define EUR_CR_PARTITION_BREAKPOINT 0x0F7C #define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_MASK 0x000003C0U #define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SHIFT 6 @@ -1141,10 +1233,12 @@ #define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_MASK 0x00000004U #define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SHIFT 2 #define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SIGNED 0 +/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 */ #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 0x0F80 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 +/* Register EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 */ #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 0x0F84 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 @@ -1161,6 +1255,7 @@ #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_0 */ #define EUR_CR_USE_CODE_BASE_0 0x0A0C #define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0 @@ -1168,6 +1263,7 @@ #define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_1 */ #define EUR_CR_USE_CODE_BASE_1 0x0A10 #define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0 @@ -1175,6 +1271,7 @@ #define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_2 */ #define EUR_CR_USE_CODE_BASE_2 0x0A14 #define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0 @@ -1182,6 +1279,7 @@ #define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_3 */ #define EUR_CR_USE_CODE_BASE_3 0x0A18 #define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0 @@ -1189,6 +1287,7 @@ #define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_4 */ #define EUR_CR_USE_CODE_BASE_4 0x0A1C #define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0 @@ -1196,6 +1295,7 @@ #define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_5 */ #define EUR_CR_USE_CODE_BASE_5 0x0A20 #define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0 @@ -1203,6 +1303,7 @@ #define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_6 */ #define EUR_CR_USE_CODE_BASE_6 0x0A24 #define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0 @@ -1210,6 +1311,7 @@ #define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_7 */ #define EUR_CR_USE_CODE_BASE_7 0x0A28 #define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0 @@ -1217,6 +1319,7 @@ #define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_8 */ #define EUR_CR_USE_CODE_BASE_8 0x0A2C #define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0 @@ -1224,6 +1327,7 @@ #define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_9 */ #define EUR_CR_USE_CODE_BASE_9 0x0A30 #define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0 @@ -1231,6 +1335,7 @@ #define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_10 */ #define EUR_CR_USE_CODE_BASE_10 0x0A34 #define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0 @@ -1238,6 +1343,7 @@ #define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_11 */ #define EUR_CR_USE_CODE_BASE_11 0x0A38 #define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0 @@ -1245,6 +1351,7 @@ #define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_12 */ #define EUR_CR_USE_CODE_BASE_12 0x0A3C #define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0 @@ -1252,6 +1359,7 @@ #define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_13 */ #define EUR_CR_USE_CODE_BASE_13 0x0A40 #define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0 @@ -1259,6 +1367,7 @@ #define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_14 */ #define EUR_CR_USE_CODE_BASE_14 0x0A44 #define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0 @@ -1266,6 +1375,7 @@ #define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0 +/* Register EUR_CR_USE_CODE_BASE_15 */ #define EUR_CR_USE_CODE_BASE_15 0x0A48 #define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0 @@ -1273,6 +1383,7 @@ #define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0 +/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP */ #define EUR_CR_PIPE0_BREAKPOINT_TRAP 0x0F88 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U #define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 @@ -1280,6 +1391,7 @@ #define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U #define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 +/* Register EUR_CR_PIPE0_BREAKPOINT */ #define EUR_CR_PIPE0_BREAKPOINT 0x0F8C #define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_MASK 0x000003C0U #define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SHIFT 6 @@ -1293,10 +1405,12 @@ #define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_MASK 0x00000004U #define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SHIFT 2 #define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SIGNED 0 +/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 */ #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 0x0F90 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 +/* Register EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 */ #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 0x0F94 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 @@ -1313,6 +1427,7 @@ #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 +/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP */ #define EUR_CR_PIPE1_BREAKPOINT_TRAP 0x0F98 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U #define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 @@ -1320,6 +1435,7 @@ #define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U #define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 +/* Register EUR_CR_PIPE1_BREAKPOINT */ #define EUR_CR_PIPE1_BREAKPOINT 0x0F9C #define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_MASK 0x000003C0U #define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SHIFT 6 @@ -1333,10 +1449,12 @@ #define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_MASK 0x00000004U #define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SHIFT 2 #define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SIGNED 0 +/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 */ #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 0x0FA0 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 +/* Register EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 */ #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 0x0FA4 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 @@ -1353,6 +1471,8 @@ #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 +/* Table EUR_CR_USE_CODE_BASE */ +/* Register EUR_CR_USE_CODE_BASE */ #define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) #define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 @@ -1360,8 +1480,9 @@ #define EUR_CR_USE_CODE_BASE_DM_MASK 0x0C000000U #define EUR_CR_USE_CODE_BASE_DM_SHIFT 26 #define EUR_CR_USE_CODE_BASE_DM_SIGNED 0 +/* Number of entries in table EUR_CR_USE_CODE_BASE */ #define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 #define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 -#endif +#endif /* _SGX544DEFS_KM_H_ */ |