From 89f5905ad0bf8a4a1524f455b225b9bebe3a94b7 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Mon, 8 Oct 2012 13:53:37 -0600 Subject: move v8 dst from linaro/boot-wrapper to linaro/dts Signed-off-by: John Rigby --- debian/rules.d/2-binary-arch.mk | 1 + linaro/boot-wrapper/model-v8.dts | 192 --------------------------------------- linaro/dts/model-v8.dts | 192 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 193 insertions(+), 192 deletions(-) delete mode 100644 linaro/boot-wrapper/model-v8.dts create mode 100644 linaro/dts/model-v8.dts diff --git a/debian/rules.d/2-binary-arch.mk b/debian/rules.d/2-binary-arch.mk index 399371b69ec..b808418291d 100644 --- a/debian/rules.d/2-binary-arch.mk +++ b/debian/rules.d/2-binary-arch.mk @@ -46,6 +46,7 @@ $(stampdir)/stamp-build-%: $(stampdir)/stamp-prepare-% if [ -d linaro/boot-wrapper ] ; then \ cp -a linaro/boot-wrapper/ $(builddir); \ cp -a arch/arm64/boot/dts/* $(builddir)/boot-wrapper; \ + cp -a linaro/dts/* $(builddir)/boot-wrapper; \ cp -a $(builddir)/build-$*/arch/arm64/boot/Image $(builddir)/boot-wrapper; \ (cd $(builddir)/boot-wrapper; make CROSS_COMPILE=$(CROSS_COMPILE) FDT_SRC=model-v8.dts BOOTARGS='"console=ttyAMA0 root=/dev/vda2 earlyprintk consolelog=9 rw mem=2048M"'); \ fi diff --git a/linaro/boot-wrapper/model-v8.dts b/linaro/boot-wrapper/model-v8.dts deleted file mode 100644 index a7fed8ffe70..00000000000 --- a/linaro/boot-wrapper/model-v8.dts +++ /dev/null @@ -1,192 +0,0 @@ -/* - * ARM Ltd. - * - * RTSM v8 platform (model) - * - * A very stripped down Versatile Express inspired platform - * - */ - -/dts-v1/; - -/ { - #address-cells = <2>; - #size-cells = <1>; - model = "V2P-AARCH64"; - compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress"; - interrupt-parent = <&gic>; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = < 0x00000000 0x80000000 0x80000000 - 0x00000008 0x80000000 0x80000000 >; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0x2c001000 0x1000>, - <0x0 0x2c002000 0x100>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 60 4 0 61 4 0 62 4 0 63 4>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 14 0xff01>; - clock-frequency = <100000000>; - }; - - motherboard { - compatible = "simple-bus"; - arm,v2m-memory-map = "rs1"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - - ranges = <2 0 0x0 0x18000000 0x04000000>, - <3 0 0x0 0x1c000000 0x04000000>; - - ethernet@2,02000000 { - compatible = "smsc,lan91c111"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - }; - - iofpga@3,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - sysreg@010000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - }; - - v2m_serial0: uart@090000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - }; - - v2m_serial1: uart@0a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - }; - - v2m_serial2: uart@0b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - }; - - v2m_serial3: uart@0c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - }; - - virtio_block@0130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x1000>; - interrupts = <42>; - }; - }; - }; - - /* chosen */ -}; - diff --git a/linaro/dts/model-v8.dts b/linaro/dts/model-v8.dts new file mode 100644 index 00000000000..a7fed8ffe70 --- /dev/null +++ b/linaro/dts/model-v8.dts @@ -0,0 +1,192 @@ +/* + * ARM Ltd. + * + * RTSM v8 platform (model) + * + * A very stripped down Versatile Express inspired platform + * + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "V2P-AARCH64"; + compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress"; + interrupt-parent = <&gic>; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = < 0x00000000 0x80000000 0x80000000 + 0x00000008 0x80000000 0x80000000 >; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2c001000 0x1000>, + <0x0 0x2c002000 0x100>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4 0 61 4 0 62 4 0 63 4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 14 0xff01>; + clock-frequency = <100000000>; + }; + + motherboard { + compatible = "simple-bus"; + arm,v2m-memory-map = "rs1"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + ranges = <2 0 0x0 0x18000000 0x04000000>, + <3 0 0x0 0x1c000000 0x04000000>; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + }; + + virtio_block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x1000>; + interrupts = <42>; + }; + }; + }; + + /* chosen */ +}; + -- cgit v1.2.3