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AgeCommit message (Expand)Author
2018-11-12[llvm-mca] Correctly update the resource strategy for processor resources wit...Andrea Di Biagio
2018-11-10[X86][BdVer2] Fix loads/stores throughput for Piledriver (PR39465)Roman Lebedev
2018-11-10[NFC][MCA][BdVer2] Add bdver2 runline into register-file-statistics.s testRoman Lebedev
2018-11-09[X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX.Clement Courbet
2018-11-08[NFC][BdVer2] Load and store throughput tests: also check sched stats (PR39465)Roman Lebedev
2018-11-08[NFC][BdVer2] Tests for load and store throughput (PR39465)Roman Lebedev
2018-11-01[llvm-mca] Add extra counters for move elimination in view RegisterFileStatis...Andrea Di Biagio
2018-10-27AMD BdVer2 (Piledriver) Initial Scheduler modelRoman Lebedev
2018-10-27[NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler modelRoman Lebedev
2018-10-24[MC] Separate masm integer literal lexer support from inline asmReid Kleckner
2018-10-24[llvm-mca] [llvm-mca] Improved error handling and error reporting from class ...Andrea Di Biagio
2018-10-16[X86] Fix Skylake ReadAfterLd for PADDrm etc.Simon Pilgrim
2018-10-12[tblgen][llvm-mca] Add the ability to describe move elimination candidates vi...Andrea Di Biagio
2018-10-11[llvm-mca][BtVer2] Add tests for optimizable GPR register moves. NFCAndrea Di Biagio
2018-10-10[llvm-mca][BtVer2] Add two more move-elimination tests. NFCAndrea Di Biagio
2018-10-05[X86] Move ReadAfterLd functionality into X86FoldableSchedWrite (PR36957)Simon Pilgrim
2018-10-04[llvm-mca][x86] Add PR36951 ReadAfterLd test caseSimon Pilgrim
2018-10-04[utils] Ensure that update_mca_test_checks.py writes prefixes in alphabetical...Greg Bedwell
2018-10-04[llvm-mca][x86] Add tests demonstrating ReadAfterLd delaySimon Pilgrim
2018-10-03[X86][Btver2] Fix MMX PSHUFB scheduleSimon Pilgrim
2018-10-03[llvm-mca] Add support for move elimination in class RegisterFile.Andrea Di Biagio
2018-10-03[X86][Btver2] Most RMW instructions don't require an additional uopSimon Pilgrim
2018-10-03[X86] ALU/ADC RMW instructions should use the WriteRMW sequence classSimon Pilgrim
2018-10-02[X86][Btver2] Fix BLENDV and AESDEC schedulesSimon Pilgrim
2018-10-01[X86][Btver2] Fix BT(C|R|S)mr & BT(C|R|S)mi schedule latency + uop countsSimon Pilgrim
2018-10-01[X86][Btver2] Fix BTmr schedule uop countsSimon Pilgrim
2018-10-01[X86][Btver2] Fix masked load scheduleSimon Pilgrim
2018-10-01[X86][BtVer2] Teach how to identify zero-idiom VPERM2F128rr instructions.Andrea Di Biagio
2018-10-01[X86][Sched] Update scheduling information for VZEROALL on HWS, BDW, SKX, SNB.Clement Courbet
2018-09-30[X86] Fix scheduler class for BTmi instructionsSimon Pilgrim
2018-09-30[LLVM-MCA][X86] Add missing VCMPESTR/VCMPESTR testsSimon Pilgrim
2018-09-30[LLVM-MCA][X86] Add some AVX512 testsSimon Pilgrim
2018-09-30[X86][Btver2] Fix PCmpIStrI/PCmpIStrM schedulesSimon Pilgrim
2018-09-28[llvm-mca] Add a test for zero-idiom VPERM2F128rr. NFCAndrea Di Biagio
2018-09-28[utils] Stricter checking from update_mca_test_checks.pyGreg Bedwell
2018-09-28[utils] Allow better identification of matching blocks in update_mca_test_che...Greg Bedwell
2018-09-28[X86][Btver2] PSUBS/PSUBUS instructions are zero-idiomsSimon Pilgrim
2018-09-28[X86][Btver2] Add zero-idiom tests for PSUBS/PSUBUS instructionsSimon Pilgrim
2018-09-28[X86][Btver2] CVTSS2I/CVTSD2I - add missing JFPU0 pipeSimon Pilgrim
2018-09-28[X86][Btver2] Fix BSF/BSR scheduleSimon Pilgrim
2018-09-28[X86][BtVer2] Fix PHMINPOS schedule resources typoSimon Pilgrim
2018-09-27[X86][Btver2] (V)MPSADBW instructions take 3uops not 1Simon Pilgrim
2018-09-27[X86][Btver2] BTC/BTR/BTS instructions take 2uops not 1Simon Pilgrim
2018-09-27[X86][Btver2] BLSI/BLSMSK/BLSR instructions take 2uops not 1 (same as TZCNT)Simon Pilgrim
2018-09-27[X86][Btver2] TZCNT instructions take 2uops not 1Simon Pilgrim
2018-09-25Revert rL342916: [X86] Remove shift/rotate by CL memory (RMW) overridesSimon Pilgrim
2018-09-24[X86] Remove shift/rotate by CL memory (RMW) overridesSimon Pilgrim
2018-09-24[X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)Simon Pilgrim
2018-09-23[X86] ROR*mCL instruction models should match ROL*mCL etc.Simon Pilgrim
2018-09-23[X86] Added missing RCL/RCR schedule overrides to the generic SNB modelSimon Pilgrim
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