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2017-06-27[mips] Add instruction aliases for ds(r|l)l.Simon Dardis
Add the instruction aliases for ds(r|l)l for the two operand alias of ds(r|l)lv and the aliases ds(r|l)l with the three register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306405 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-23Reland r306095: [mips] Fix reg positions in the aui/daui instructionsPetar Jovanovic
After fixing (r306173) a failing test in the lld test suite (r306173), reland r306095. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aui/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306174 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-23Revert r306095: [mips] Fix reg positions in the aui/daui instructionsPetar Jovanovic
ELF/mips-plt-r6.s in lld-test is failing. Reverting the change. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aut/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306099 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-23[mips] Fix register positions in the aui/daui instructionsPetar Jovanovic
Swapped the position of the rt and rs register in the aut/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D33988 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306095 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-22[mips] seb, seh instruction aliasesSimon Dardis
Add the single operand form. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D26961 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287681 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-16[mips] not instruction aliasSimon Dardis
This patch adds the single operand form of the not alias to microMIPS and MIPS along with additional tests. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287097 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-14[mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis
For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284218 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-13[mips] Add IAS support for dvp, evpSimon Dardis
These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284115 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-05Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis
Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283334 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-05Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis
This reverts commit r282485 which contain two patches instead of one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283327 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-27[mips] Add rsqrt, recip for MIPSSimon Dardis
Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282485 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"Simon Dardis
This reverts r281724. Still need dsanders to accept this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281726 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16[mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis
For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281724 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-22[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix ↵Hrvoje Varga
disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279429 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-17[mips] Add l.[sd] and s.[sd] instruction aliasesSimon Dardis
Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23121 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278930 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-27[mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders
Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276867 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-26[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliasesSimon Dardis
Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276736 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-11[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and ↵Zlatko Buljan
SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275050 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-27[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV ↵Hrvoje Varga
instructions Differential Revision: http://reviews.llvm.org/D16625 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273850 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31[mips] Remove tests which should have been deleted.Simon Dardis
The two xfail tests for mis32r6 & mips64r6 were supposed to be removed in r271301. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271306 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31[mips] Enforce compact branch register restrictionsSimon Dardis
Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271301 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-27[mips] Weaken asm predicate for memory offsetsSimon Dardis
The isMemWithSimmOffset predicate rejects relocations which is incorrect behaviour. Linkers and other tools should handle|warn|error when the field overflows. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D20727 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270995 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-18[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add ↵Zlatko Buljan
CodeGen support Differential Revision: http://reviews.llvm.org/D15418 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269883 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"Hrvoje Varga
This reverts commit r269176 as it caused test-suite failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269287 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-11[mips][microMIPS] Implement CFC*, CTC* and LDC* instructionsHrvoje Varga
Differential Revision: http://reviews.llvm.org/D19713 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269176 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-03[mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations.Daniel Sanders
Summary: This is much closer to the way MIPS relocation expressions work (%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the various bodges in MipsAsmParser::evaluateRelocExpr(). Removing those bodges ensures that the constant stored in MCValue is the full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used to correct the %hi/%lo matching needed to sort the relocation table correctly. As part of this: * Gave MCExpr::print() the ability to omit parenthesis when emitting a symbol reference inside a MipsMCExpr operator like %hi(X). Without this we print things like %lo(($L1)). * %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of the related special cases have been removed or moved to MipsMCExpr. We can remove the rest as we gain support for the less common relocations when they are not part of this specific combination. * Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_'). * fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical and merged into fixup_Mips_GOT. * MO_GOT16 and MO_GOT turned out to be identical and have been merged into MO_GOT. * VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they have been merged into MEK_GOT Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19716 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268379 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22[mips][microMIPS] Revert commit r266861.Zoran Jovanovic
Commit r266861 was the reason for failing tests in LLVM test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267166 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-20[mips][microMIPS]Implement CFC*, CTC* and LDC* instructionsHrvoje Varga
Differential Revision: http://reviews.llvm.org/D18640 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266861 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-14Summary:Simon Dardis
Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. This patch was previous committed as r266055 as seemed to have caused some spurious test failures. They did not reappear after further local testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266301 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12Revert "[mips] MIPSR6 Compact branch aliases"Simon Dardis
This reverts commit r266055. ps4-buildslave2 is highlighting a failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266061 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12[mips] MIPSR6 Compact branch aliasesSimon Dardis
Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D18856 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266055 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-01[MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISASagar Thakur
Summary: The assembler was picking the wrong JR variant because the pre-R6 one was still enabled at R6. Author: nitesh.jain Reviewers: vkalintiris, dsanders Subscribers: dsanders, llvm-commits, mohit.bhakkad, sagar, bhushan, jaydeep Differential: D18387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265134 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-31[mips] Range check simm16Daniel Sanders
Summary: There are too many instructions to exhaustively test so addiu and lwc2 are used as representative examples. It should be noted that many memory instructions that should have simm16 range checking do not because it is also necessary to support the macro of the same name which accepts simm32. The range checks for these occur in the macro expansion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18437 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265019 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-31[mips] Range check simm9 and fix a bug this revealed.Daniel Sanders
Summary: The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a 12-bit offset when it is only 9-bit. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265010 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11[mips] Invalid tests for MTC0, MTC2, MFC0, MFC2, DMTC0, DMFC0 MIPS instructionsHrvoje Varga
Differential Revision: http://reviews.llvm.org/D18037 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263203 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-29[mips] Range check uimm20 and fixed a bug this revealed.Daniel Sanders
Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262231 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-11[mips] Never select JAL for calls to an absolute immediate address.Daniel Sanders
Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257339 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-18[mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV ↵Zlatko Buljan
and WRDSP instructions Differential Revision: http://reviews.llvm.org/D14429 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255991 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-09[mips][ias] Range check uimm10 operandsDaniel Sanders
Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15229 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255112 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-09Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions"Zlatko Buljan
Commited patch was intended to implement LH, LHE, LHU and LHUE instructions. After commit test-suite failed with error message in the form of: fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32 For that reason I decided to revert commit r254897 and make new patch which besides implementation and standard regression tests will also have dedicated tests (CodeGen) for the above error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255109 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-07[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructionsZlatko Buljan
Differential Revision: http://reviews.llvm.org/D9824 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254897 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-26[mips][ias] Range check uimm5 operands and fix several bugs this revealed.Daniel Sanders
Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254164 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-06[mips][ias] Range check uimm3 operands.Daniel Sanders
Summary: Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14016 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252296 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-06[mips][ias] Range check uimm2 operands and fix a bug this revealed.Daniel Sanders
Summary: The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA (unlike the MSA version) failed to account for the off-by-one encoding of the immediate. The range is actually 1..4 rather than 0..3. Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14015 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252295 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16[mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and ↵Zoran Jovanovic
SWE instructions Differential Revision: http://reviews.llvm.org/D9189 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247780 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15[mips] Add support for branch-likely pseudo-instructionsZoran Jovanovic
Differential Revision: http://reviews.llvm.org/D10537 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247697 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15[mips] Added support for various EVA ASE instructions.Daniel Sanders
Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247669 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-11[mips] Remap move as or.Vasileios Kalintiris
Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244579 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20[mips] Added support for the ERETNC instruction.Vasileios Kalintiris
Summary: This required adding the instruction predicate HasMips32r5. Patch by Scott Egerton. Reviewers: dsanders, vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11136 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242666 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-27[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.Daniel Sanders
Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240883 91177308-0d34-0410-b5e6-96231b3b80d8
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