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2018-10-26Add pass to mark cold and non-hot functions for size optimization.linaro-local/peter.smith/rebased-pgoPeter Smith
The MarkCold pass marks functions that the ProfileSummaryInfo has identified as having all cold basic block to be optimized for code size. The pass can be run before inlining with -fprofile-opt-cold-for-size-early or after with -fprofile-opt-cold-for-size. When -fprofile-sample-accurate is on then when using a sample profile then no profile information will imply cold in callgraph. When -fmark-neutral-cold is on then we will mark functions that are neither hot or cold as OptimizeForSize and cold functions as MinimalSize.
2018-10-26[PM] Add profile instruction lowering pass for -fprofile-instr-generatePeter Smith
When -fprofile-instr-generate is used with the new pass manager the pass to lower the profile instructions is not added resulting in an assertion failure. This is a somewhat simplistic fix for PR33773.
2018-10-26[CodeGen] Remove out operands from PATCHABLE_OPFrancis Visoiu Mistrih
The current model requires 1 out operand, but it is not used nor created. This fixed an x86 machine verifier issue. Part of PR27481. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345384 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[llvm-ar] Access ADDLIB in llvm-ar via command lineOwen Reynolds
ADDLIB is called to add the contents of an archive to another archive. Previously this was only accessible through the use of an MRI script. With the use of a new "L" modifier, archive files can treated in the manner above when using quick append. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345383 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[AMDGPU] Add a pass to promote bitcast callsScott Linder
AMDGPU currently only supports direct calls, but at lower optimisation levels it fails to lower statically direct calls which appear indirect due to a bitcast. Add a pass to visit all CallSites and use CallPromotionUtils to "devirtualize" calls. Differential Revision: https://reviews.llvm.org/D52741 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345382 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26Regenerate testSimon Pilgrim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345379 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[llvm-mca] Fix -wreorder and -Wunused-private-field after r345376. NFCSam McCall
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345378 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[Codegen] - Implement basic .debug_loclists section emission (DWARF5).George Rimar
.debug_loclists is the DWARF 5 version of the .debug_loc. With that patch, it will be emitted when DWARF 5 is used. Differential revision: https://reviews.llvm.org/D53365 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345377 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[llvm-mca] Removed dependency on mca::SourcMgr in some Views. NFCAndrea Di Biagio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345376 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[SimpleLoopUnswitch] Make all checks before actual non-trivial unswitchMax Kazantsev
We should be able to make all relevant checks before we actually start the non-trivial unswitching, so that we could guarantee that once we have started the transform, it will always succeed. Reviewed By: chandlerc Differential Revision: https://reviews.llvm.org/D53747 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345375 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[SystemZ] Fix -Wcovered-switch-default as coding standard regulatesFangrui Song
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345369 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[NFC] Add periods to CREDITS.txt (testing git-llvm)Kristina Brooks
NFC commit to test git-llvm bridge for current GitHub monorepo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345368 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[llvm-nm] Simplify. NFCFangrui Song
Change a \t to spaces Change some zero-filling memcpy to aggregate initialization Delete redundant ArchiveName.clear() after declaration git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345367 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[PowerPC] Fix some missed optimization opportunities in combineSetCCLi Jia He
For both operands are bool, short, int, long, long long, add the following optimization. 1. 0-x == y --> x+y ==0 2. 0-x != y --> x+y != 0 Review: nemanjai Differential Revision: https://reviews.llvm.org/D53360 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345366 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[PowerPC][NFC] Add tests for some missed optimization opportunities in ↵Li Jia He
combineSetCC For both operands are bool, short, int, long, long long, add the following optimization test case. 1. 0-x == y --> x+y ==0 2. 0-x != y --> x+y != 0 Review: nemanjai Differential Revision: https://reviews.llvm.org/D53358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345365 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26This reverts commit r345357, It is wrong to create a new directory and put ↵Li Jia He
the test file into it. I am sorry for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345364 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[NFC] Fix the regular expression for BE PPC in update_llc_test_checks.pyNemanja Ivanovic
Currently, the regular expression that matches the lines of assembly for PPC LE (ELFv2) does not work for the assembly for BE (ELFv1). This patch fixes it. Differential revision: https://reviews.llvm.org/D53059 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345363 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[PowerPC] Keep vector int to fp conversions in vector domainNemanja Ivanovic
At present a v2i16 -> v2f64 convert is implemented by extracts to scalar, scalar converts, and merge back into a vector. Use vector converts instead, with the int data permuted into the proper position and extended if necessary. Patch by RolandF. Differential revision: https://reviews.llvm.org/D53346 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345361 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[Pipeliner] Mark swp-art-deps-rec.ll as REQUIRES: asserts after rL345319Fangrui Song
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345359 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26Add dependency from SystemZAsmParser to SystemZAsmPrinter after rL345349Fangrui Song
This fixes -DBUILD_SHARED_LIBS=on build. The dependency is similar to that of X86's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345358 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[PowerPC][NFC] Add tests for some missed optimization opportunities in ↵Li Jia He
combineSetCC For both operands are bool, short, int, long, long long, add the following optimization test case. 1. 0-x == y --> x+y ==0 2. 0-x != y --> x+y != 0 Review: nemanjai Differential Revision: https://reviews.llvm.org/D53358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345357 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26Revert "[AArch64] Create proper memoperand for multi-vector stores"Vlad Tsyrklevich
This reverts commit r345315, it was causing test failures on sanitizer-x86_64-linux-fast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345356 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26add myself to the CREDITS.TXTLi Jia He
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345355 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26Teach the DominatorTree fallback to recalculation when applying updates to ↵Chijun Sima
speedup JT (PR37929) Summary: This patch makes the dominatortree recalculate when applying updates with the size of the update vector larger than a threshold. Directly applying updates is usually slower than recalculating the whole domtree in this case. This patch fixes an issue which causes JT running slowly on some inputs. In bug 37929, the dominator tree is trying to apply 19,000+ updates several times, which takes several minutes. After this patch, the time used by DT.applyUpdates: | Input | Before (s) | After (s) | Speedup | | the 2nd Reproducer in 37929 | 297 | 0.15 | 1980x | | clang-5.0.0.0.bc | 9.7 | 4.3 | 2.26x | | clang-5.0.0.4.bc | 11.6 | 2.6 | 4.46x | Reviewers: kuhar, brzycki, trentxintong, davide, dmgreen, grosser Reviewed By: kuhar, brzycki Subscribers: kristina, llvm-commits Differential Revision: https://reviews.llvm.org/D53245 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345353 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[SystemZ] Implement SystemZOperand::print()Jonas Paulsson
SystemZAsmParser can now handle -debug by printing the operands neatly to the output stream. Before this patch this lead to an llvm_unreachable(). It seems that now '-mllvm -debug' does not cause any crashes anywhere (at least not on SPEC). Review: Ulrich Weigand https://reviews.llvm.org/D53328 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345349 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26Dump public symbol records in pdb2yaml modeZachary Turner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345348 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-26[SystemZ] Pass the DAG pointer from SystemZAddressingMode::dump().Jonas Paulsson
In order to print the IR slot number for the memory operand, the DAG pointer must be passed to SDNode::dump(). The isel-debug.ll test updated to also check for the IR Value reference being printed correctly. Review: Ulrich Weigand https://reviews.llvm.org/D53333 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345347 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25Reland "[WebAssembly] LSDA info generation"Heejin Ahn
Summary: This adds support for LSDA (exception table) generation for wasm EH. Wasm EH mostly follows the structure of Itanium-style exception tables, with one exception: a call site table entry in wasm EH corresponds to not a call site but a landing pad. In wasm EH, the VM is responsible for stack unwinding. After an exception occurs and the stack is unwound, the control flow is transferred to wasm 'catch' instruction by the VM, after which the personality function is called from the compiler-generated code. (Refer to WasmEHPrepare pass for more information on this part.) This patch: - Changes wasm.landingpad.index intrinsic to take a token argument, to make this 1:1 match with a catchpad instruction - Stores landingpad index info and catch type info MachineFunction in before instruction selection - Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an exception table - Adds WasmException class with overridden methods for table generation - Adds support for LSDA section in Wasm object writer Reviewers: dschuff, sbc100, rnk Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52748 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345345 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[WebAssembly] Support EH instructions in InstPrinterHeejin Ahn
Summary: This adds support for exception handling instructions to InstPrinter. Reviewers: dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53634 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345343 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25Fix in MachineOperand::printIRValueReference().Jonas Paulsson
Handle the case where getCurrentFunction() returns nullptr by passing -1 to printIRSlotNumber(). This will result in <badref> being printed instead of an assertion failure. Review: Francis Visoiu Mistrih https://reviews.llvm.org/D53333 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345342 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[AArch64] Implement FP16FML intrinsicsBryan Chan
Add LLVM intrinsics for the ARMv8.2-A FP16FML vector-form instructions. Add a DAG pattern to define the indexed-form intrinsics in terms of the vector-form ones, similarly to how the Dot Product intrinsics were implemented. Based on a patch by Gao Yiling. Differential Revision: https://reviews.llvm.org/D53632 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345337 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25Delete test case. Assertions can't be tested.Heejin Ahn
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345336 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25Tidy up test caseHeejin Ahn
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345335 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25Address commentsHeejin Ahn
- Add llvm-mc test case (and delete the old one) - Change report_fatal_error to assertions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345334 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[WebAssembly] Error out when block/loop markers mismatchHeejin Ahn
Summary: Currently InstPrinter ignores if there are mismatches between block/loop and end markers by skipping the case if ControlFlowStack is empty. I guess it is better to explicitly error out in this case, because this signals invalid input. Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53620 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345333 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[SystemZ] NFC reformatting in SystemZTargetTransformInfo.cppJonas Paulsson
Some lines more than 80 characters long reformatted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345331 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[SystemZ] Improve getMemoryOpCost() to find foldable loads that are converted.Jonas Paulsson
The SystemZ backend can do arithmetic of memory by loading and then extending one of the operands. Similarly, a load + truncate can be folded into an operand. This patch improves the SystemZ TTI cost function to recognize this. Review: Ulrich Weigand https://reviews.llvm.org/D52692 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345327 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25DebugInfo: Explain why DW_LLE_(GNU_)startx_length is usedDavid Blaikie
This isn't the most object-size efficient encoding, but it's the only one GDB supports for the pre-standard fission format. I've written fixes for this twice now... - so perhaps this comment will help me remember why neither of these have been committed and why I shouldn't try to write a third fix another year from now... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345326 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[x86] add tests for missed load folding; NFCSanjay Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345325 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[SystemZ] Improve handling and cost estimates of vector integer div/remJonas Paulsson
Enable the DAG optimization that converts vector div/rem with constants into multiply+shifts sequences by expanding them early. This is needed since ISD::SMUL_LOHI is 'Custom' lowered on SystemZ, and will therefore not be available to BuildSDIV after legalization. Better cost values for these instructions based on how they will be implemented (a constant divisor is cheaper). Review: Ulrich Weigand https://reviews.llvm.org/D53196 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345321 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25llvm-dwarfdump: loclists: Don't expect an (albeit empty) expression for ↵David Blaikie
LLE_base_address git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345320 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[Pipeliner] Ignore Artificial dependences while computing recurrences.Sumanth Gundapaneni
The artificial dependencies are not real dependencies. In some cases, they form circuits with bigger MII. However, they are used to schedule instructions better. Differential Revision: https://reviews.llvm.org/D53450 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345319 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[Pipeliner] Remove the unneeded include header(NFC).Sumanth Gundapaneni
Differential Revision: https://reviews.llvm.org/D53451 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345318 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[X86] Change X86 backend to look for 'min-legal-vector-width' attribute ↵Craig Topper
instead of 'required-vector-width' when determining whether 512-bit vectors should be legal. The required-vector-width attribute was only used for backend testing and has never been generated by clang. I believe clang is now generating min-legal-vector-width for vector uses in user code. With this I believe passing -mprefer-vector-width=256 to clang should prevent use of zmm registers in the generated assembly unless the user used a 512-bit intrinsic in their source code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345317 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[CodeGen] Remove operands from FENTRY_CALLFrancis Visoiu Mistrih
FENTRY_CALL is actually not taking any input / output operands. The machine verifier complains now because the target description says that: * It needs 1 unknown output * It needs 1 or more variable inputs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345316 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[AArch64] Create proper memoperand for multi-vector storesDavid Greene
Include all of the store's source vector operands when creating the MachineMemOperand. Previously, we were missing the first operand, making the store size seem smaller than it really is. Differential Revision: https://reviews.llvm.org/D52816 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345315 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[AArch64][GlobalISel] Simplify a legalizer test. NFC.Volkan Keles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345307 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[WebAssembly] Use target-independent saturating addThomas Lively
Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53721 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345299 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[X86] Add some non-AVX512VL command lines to the *vl-vec-test-testn.ll tests.Craig Topper
This will expose some regressions in the WIP and/or/xor promotion removal patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345297 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25[FPEnv] Last BinaryOperator::isFNeg(...) to m_FNeg(...) changesCameron McInally
Replacing BinaryOperator::isFNeg(...) to avoid regressions when we separate FNeg from the FSub IR instruction. Differential Revision: https://reviews.llvm.org/D53650 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345295 91177308-0d34-0410-b5e6-96231b3b80d8
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