diff options
author | Craig Topper <craig.topper@intel.com> | 2018-11-04 02:10:18 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2018-11-04 02:10:18 +0000 |
commit | 3ba729d27046f3f82af374ceebb5e8de3ee6a8e4 (patch) | |
tree | 55486f3a8227f698457d93eb6f89cc00636fa013 /unittests | |
parent | ad3c2dda979bc6d822b0db03845ff27b54480a12 (diff) |
[SelectionDAG] Remove special methods for creating *_EXTEND_VECTOR_INREG nodes. Move asserts into getNode.
These methods were just wrappers around getNode with additional asserts (identical and repeated 3 times). But getNode already has a switch that can be used to hold these asserts that allows them to be shared for all 3 opcodes. This also enables checking on the places that create these nodes without using the wrappers.
The rest of the patch is just changing all callers to use getNode directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346087 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'unittests')
-rw-r--r-- | unittests/CodeGen/AArch64SelectionDAGTest.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/unittests/CodeGen/AArch64SelectionDAGTest.cpp b/unittests/CodeGen/AArch64SelectionDAGTest.cpp index 620dfc8d234..dc2d1f9a357 100644 --- a/unittests/CodeGen/AArch64SelectionDAGTest.cpp +++ b/unittests/CodeGen/AArch64SelectionDAGTest.cpp @@ -86,7 +86,7 @@ TEST_F(AArch64SelectionDAGTest, computeKnownBits_ZERO_EXTEND_VECTOR_INREG) { auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4); auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2); auto InVec = DAG->getConstant(0, Loc, InVecVT); - auto Op = DAG->getZeroExtendVectorInReg(InVec, Loc, OutVecVT); + auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); auto DemandedElts = APInt(4, 15); KnownBits Known; DAG->computeKnownBits(Op, Known, DemandedElts); @@ -118,7 +118,7 @@ TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_SIGN_EXTEND_VECTOR_INREG) { auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4); auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2); auto InVec = DAG->getConstant(1, Loc, InVecVT); - auto Op = DAG->getSignExtendVectorInReg(InVec, Loc, OutVecVT); + auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); auto DemandedElts = APInt(4, 15); EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 15u); } |