diff options
author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-08-15 22:11:05 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-08-15 22:11:05 +0000 |
commit | 61d7ed2067753f6e7c44dff84d74d698ba875dda (patch) | |
tree | 2194208eebf3cc07b6afa689d85e98af2843c7fd /tools/llvm-mca | |
parent | c4dcd354354d106eca242ed82682d4f6d8d6c150 (diff) |
[llvm-mca] Minor style changes. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339823 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'tools/llvm-mca')
-rw-r--r-- | tools/llvm-mca/DispatchStage.h | 8 | ||||
-rw-r--r-- | tools/llvm-mca/ExecuteStage.h | 15 | ||||
-rw-r--r-- | tools/llvm-mca/FetchStage.h | 15 | ||||
-rw-r--r-- | tools/llvm-mca/RetireStage.h | 17 |
4 files changed, 28 insertions, 27 deletions
diff --git a/tools/llvm-mca/DispatchStage.h b/tools/llvm-mca/DispatchStage.h index 496c8f5fc2f..06619a83133 100644 --- a/tools/llvm-mca/DispatchStage.h +++ b/tools/llvm-mca/DispatchStage.h @@ -49,7 +49,7 @@ class Scheduler; // // If the number of micro opcodes exceedes DispatchWidth, then the instruction // is dispatched in multiple cycles. -class DispatchStage : public Stage { +class DispatchStage final : public Stage { unsigned DispatchWidth; unsigned AvailableEntries; unsigned CarryOver; @@ -92,9 +92,9 @@ public: // We can always try to dispatch, so returning false is okay in this case. // The retire stage, which controls the RCU, might have items to complete but // RetireStage::hasWorkToComplete will check for that case. - virtual bool hasWorkToComplete() const override final { return false; } - virtual void cycleStart() override final; - virtual Status execute(InstRef &IR) override final; + bool hasWorkToComplete() const override { return false; } + void cycleStart() override; + Status execute(InstRef &IR) override; void notifyDispatchStall(const InstRef &IR, unsigned EventType); #ifndef NDEBUG diff --git a/tools/llvm-mca/ExecuteStage.h b/tools/llvm-mca/ExecuteStage.h index 785d30382c0..d40057a5689 100644 --- a/tools/llvm-mca/ExecuteStage.h +++ b/tools/llvm-mca/ExecuteStage.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// /// \file /// -/// This file defines the execution stage of an instruction pipeline. +/// This file defines the execution stage of a default instruction pipeline. /// /// The ExecuteStage is responsible for managing the hardware scheduler /// and issuing notifications that an instruction has been executed. @@ -26,7 +26,7 @@ namespace mca { -class ExecuteStage : public Stage { +class ExecuteStage final : public Stage { // Owner will go away when we move listeners/eventing to the stages. RetireControlUnit &RCU; Scheduler &HWS; @@ -36,17 +36,18 @@ class ExecuteStage : public Stage { void updateSchedulerQueues(); void issueReadyInstructions(); -public: - ExecuteStage(RetireControlUnit &R, Scheduler &S) : Stage(), RCU(R), HWS(S) {} ExecuteStage(const ExecuteStage &Other) = delete; ExecuteStage &operator=(const ExecuteStage &Other) = delete; +public: + ExecuteStage(RetireControlUnit &R, Scheduler &S) : Stage(), RCU(R), HWS(S) {} + // The ExecuteStage will always complete all of its work per call to // execute(), so it is never left in a 'to-be-processed' state. - virtual bool hasWorkToComplete() const override final { return false; } + bool hasWorkToComplete() const override { return false; } - virtual void cycleStart() override final; - virtual Status execute(InstRef &IR) override final; + void cycleStart() override; + Status execute(InstRef &IR) override; void notifyInstructionIssued(const InstRef &IR, diff --git a/tools/llvm-mca/FetchStage.h b/tools/llvm-mca/FetchStage.h index ab9668e81f2..447ec3bf7c0 100644 --- a/tools/llvm-mca/FetchStage.h +++ b/tools/llvm-mca/FetchStage.h @@ -23,21 +23,22 @@ namespace mca { -class FetchStage : public Stage { +class FetchStage final : public Stage { using InstMap = std::map<unsigned, std::unique_ptr<Instruction>>; InstMap Instructions; InstrBuilder &IB; SourceMgr &SM; -public: - FetchStage(InstrBuilder &IB, SourceMgr &SM) : IB(IB), SM(SM) {} FetchStage(const FetchStage &Other) = delete; FetchStage &operator=(const FetchStage &Other) = delete; - bool hasWorkToComplete() const override final; - Status execute(InstRef &IR) override final; - void postExecute() override final; - void cycleEnd() override final; +public: + FetchStage(InstrBuilder &IB, SourceMgr &SM) : IB(IB), SM(SM) {} + + bool hasWorkToComplete() const override; + Status execute(InstRef &IR) override; + void postExecute() override; + void cycleEnd() override; }; } // namespace mca diff --git a/tools/llvm-mca/RetireStage.h b/tools/llvm-mca/RetireStage.h index fc5f79ee79b..f10188d1e6e 100644 --- a/tools/llvm-mca/RetireStage.h +++ b/tools/llvm-mca/RetireStage.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// /// \file /// -/// This file defines the retire stage of an instruction pipeline. +/// This file defines the retire stage of a default instruction pipeline. /// The RetireStage represents the process logic that interacts with the /// simulated RetireControlUnit hardware. // @@ -23,22 +23,21 @@ namespace mca { -class RetireStage : public Stage { +class RetireStage final : public Stage { // Owner will go away when we move listeners/eventing to the stages. RetireControlUnit &RCU; RegisterFile &PRF; + RetireStage(const RetireStage &Other) = delete; + RetireStage &operator=(const RetireStage &Other) = delete; + public: RetireStage(RetireControlUnit &R, RegisterFile &F) : Stage(), RCU(R), PRF(F) {} - RetireStage(const RetireStage &Other) = delete; - RetireStage &operator=(const RetireStage &Other) = delete; - virtual bool hasWorkToComplete() const override final { - return !RCU.isEmpty(); - } - virtual void cycleStart() override final; - virtual Status execute(InstRef &IR) override final { return Stage::Continue; } + bool hasWorkToComplete() const override { return !RCU.isEmpty(); } + void cycleStart() override; + Status execute(InstRef &IR) override { return Stage::Continue; } void notifyInstructionRetired(const InstRef &IR); void onInstructionExecuted(unsigned TokenID); }; |