diff options
author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-06-27 11:17:07 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-06-27 11:17:07 +0000 |
commit | 0093dbb5fc2cad6d3964f0c75296d637af846c7b (patch) | |
tree | 7b28ccb1970748b4a4f187550241f4b95dc4ea61 /tools/llvm-mca | |
parent | a62a0a383555d999fef5deeac39984f4830f9895 (diff) |
[llvm-mca] Avoid calling method update() on instructions that are already in the IS_READY state. NFCI
When promoting instructions from the wait queue to the ready queue, we should
check if an instruction has already reached the IS_READY state before
calling method update().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335722 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'tools/llvm-mca')
-rw-r--r-- | tools/llvm-mca/Instruction.cpp | 21 | ||||
-rw-r--r-- | tools/llvm-mca/Instruction.h | 16 | ||||
-rw-r--r-- | tools/llvm-mca/Scheduler.cpp | 3 |
3 files changed, 25 insertions, 15 deletions
diff --git a/tools/llvm-mca/Instruction.cpp b/tools/llvm-mca/Instruction.cpp index 3abf30c5055..f84c7811138 100644 --- a/tools/llvm-mca/Instruction.cpp +++ b/tools/llvm-mca/Instruction.cpp @@ -32,8 +32,10 @@ void ReadState::writeStartEvent(unsigned Cycles) { --DependentWrites; TotalCycles = std::max(TotalCycles, Cycles); - if (!DependentWrites) + if (!DependentWrites) { CyclesLeft = TotalCycles; + IsReady = !CyclesLeft; + } } void WriteState::onInstructionIssued() { @@ -83,8 +85,10 @@ void ReadState::cycleEvent() { if (CyclesLeft == UNKNOWN_CYCLES) return; - if (CyclesLeft) + if (CyclesLeft) { --CyclesLeft; + IsReady = !CyclesLeft; + } } #ifndef NDEBUG @@ -119,9 +123,7 @@ void Instruction::execute() { } void Instruction::update() { - if (!isDispatched()) - return; - + assert(isDispatched() && "Unexpected instruction stage found!"); if (llvm::all_of(Uses, [](const UniqueUse &Use) { return Use->isReady(); })) Stage = IS_READY; } @@ -131,9 +133,14 @@ void Instruction::cycleEvent() { return; if (isDispatched()) { - for (UniqueUse &Use : Uses) + bool IsReady = true; + for (UniqueUse &Use : Uses) { Use->cycleEvent(); - update(); + IsReady &= Use->isReady(); + } + + if (IsReady) + Stage = IS_READY; return; } diff --git a/tools/llvm-mca/Instruction.h b/tools/llvm-mca/Instruction.h index 880d57b31a3..32246cebaa5 100644 --- a/tools/llvm-mca/Instruction.h +++ b/tools/llvm-mca/Instruction.h @@ -162,17 +162,16 @@ class ReadState { // dependent writes (i.e. field DependentWrite) is zero, this value is // propagated to field CyclesLeft. unsigned TotalCycles; + // This field is set to true only if there are no dependent writes, and + // there are no `CyclesLeft' to wait. + bool IsReady; public: - bool isReady() const { - if (DependentWrites) - return false; - return (CyclesLeft == UNKNOWN_CYCLES || CyclesLeft == 0); - } + bool isReady() const { return IsReady; } ReadState(const ReadDescriptor &Desc, unsigned RegID) : RD(Desc), RegisterID(RegID), DependentWrites(0), - CyclesLeft(UNKNOWN_CYCLES), TotalCycles(0) {} + CyclesLeft(UNKNOWN_CYCLES), TotalCycles(0), IsReady(true) {} ReadState(const ReadState &Other) = delete; ReadState &operator=(const ReadState &Other) = delete; @@ -182,7 +181,10 @@ public: void cycleEvent(); void writeStartEvent(unsigned Cycles); - void setDependentWrites(unsigned Writes) { DependentWrites = Writes; } + void setDependentWrites(unsigned Writes) { + DependentWrites = Writes; + IsReady = !Writes; + } }; /// A sequence of cycles. diff --git a/tools/llvm-mca/Scheduler.cpp b/tools/llvm-mca/Scheduler.cpp index f79eda7a545..deefb461638 100644 --- a/tools/llvm-mca/Scheduler.cpp +++ b/tools/llvm-mca/Scheduler.cpp @@ -293,7 +293,8 @@ void Scheduler::promoteToReadyQueue(SmallVectorImpl<InstRef> &Ready) { // Check if this instruction is now ready. In case, force // a transition in state using method 'update()'. - IS->update(); + if (!IS->isReady()) + IS->update(); const InstrDesc &Desc = IS->getDesc(); bool IsMemOp = Desc.MayLoad || Desc.MayStore; |