[llvm-exegesis] Rename InstructionInstance into InstructionBuilder.

Summary: Non functional change.

Subscribers: tschuett, courbet, llvm-commits

Differential Revision: https://reviews.llvm.org/D50176

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338701 91177308-0d34-0410-b5e6-96231b3b80d8

9 files changed, 82 insertions, 82 deletions

diff --git a/tools/llvm-exegesis/lib/BenchmarkRunner.cpp b/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
index e03da817990..f740489dd76 100644
--- a/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
+++ b/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
@@ -131,12 +131,12 @@ BenchmarkRunner::generateConfigurations(unsigned Opcode) const {
     // TODO: Generate as many configurations as needed here.
     BenchmarkConfiguration Configuration;
     Configuration.Info = Prototype.Explanation;
-    for (InstructionInstance &II : Prototype.Snippet) {
-      II.randomizeUnsetVariables(
+    for (InstructionBuilder &IB : Prototype.Snippet) {
+      IB.randomizeUnsetVariables(
           Prototype.ScratchSpaceReg
               ? RATC.getRegister(Prototype.ScratchSpaceReg).aliasedBits()
               : RATC.emptyRegisters());
-      Configuration.Snippet.push_back(II.build());
+      Configuration.Snippet.push_back(IB.build());
     }
     if (Prototype.ScratchSpaceReg)
       Configuration.SnippetSetup.LiveIns.push_back(Prototype.ScratchSpaceReg);
@@ -147,27 +147,27 @@ BenchmarkRunner::generateConfigurations(unsigned Opcode) const {
 }
 
 std::vector<unsigned> BenchmarkRunner::computeRegsToDef(
-    const std::vector<InstructionInstance> &Snippet) const {
+    const std::vector<InstructionBuilder> &Snippet) const {
   // Collect all register uses and create an assignment for each of them.
   // Ignore memory operands which are handled separately.
   // Loop invariant: DefinedRegs[i] is true iif it has been set at least once
   // before the current instruction.
   llvm::BitVector DefinedRegs = RATC.emptyRegisters();
   std::vector<unsigned> RegsToDef;
-  for (const InstructionInstance &II : Snippet) {
+  for (const InstructionBuilder &IB : Snippet) {
     // Returns the register that this Operand sets or uses, or 0 if this is not
     // a register.
-    const auto GetOpReg = [&II](const Operand &Op) -> unsigned {
+    const auto GetOpReg = [&IB](const Operand &Op) -> unsigned {
       if (Op.IsMem)
         return 0;
       if (Op.ImplicitReg)
         return *Op.ImplicitReg;
-      if (Op.IsExplicit && II.getValueFor(Op).isReg())
-        return II.getValueFor(Op).getReg();
+      if (Op.IsExplicit && IB.getValueFor(Op).isReg())
+        return IB.getValueFor(Op).getReg();
       return 0;
     };
     // Collect used registers that have never been def'ed.
-    for (const Operand &Op : II.Instr.Operands) {
+    for (const Operand &Op : IB.Instr.Operands) {
       if (!Op.IsDef) {
         const unsigned Reg = GetOpReg(Op);
         if (Reg > 0 && !DefinedRegs.test(Reg)) {
@@ -177,7 +177,7 @@ std::vector<unsigned> BenchmarkRunner::computeRegsToDef(
       }
     }
     // Mark defs as having been def'ed.
-    for (const Operand &Op : II.Instr.Operands) {
+    for (const Operand &Op : IB.Instr.Operands) {
       if (Op.IsDef) {
         const unsigned Reg = GetOpReg(Op);
         if (Reg > 0)
@@ -209,17 +209,17 @@ BenchmarkRunner::generateSelfAliasingPrototype(const Instruction &Instr) const {
     return llvm::make_error<BenchmarkFailure>("empty self aliasing");
   }
   SnippetPrototype Prototype;
-  InstructionInstance II(Instr);
+  InstructionBuilder IB(Instr);
   if (SelfAliasing.hasImplicitAliasing()) {
     Prototype.Explanation = "implicit Self cycles, picking random values.";
   } else {
     Prototype.Explanation =
         "explicit self cycles, selecting one aliasing Conf.";
     // This is a self aliasing instruction so defs and uses are from the same
-    // instance, hence twice II in the following call.
-    setRandomAliasing(SelfAliasing, II, II);
+    // instance, hence twice IB in the following call.
+    setRandomAliasing(SelfAliasing, IB, IB);
   }
-  Prototype.Snippet.push_back(std::move(II));
+  Prototype.Snippet.push_back(std::move(IB));
   return std::move(Prototype);
 }
 
diff --git a/tools/llvm-exegesis/lib/BenchmarkRunner.h b/tools/llvm-exegesis/lib/BenchmarkRunner.h
index 845755ce97d..af3968f8944 100644
--- a/tools/llvm-exegesis/lib/BenchmarkRunner.h
+++ b/tools/llvm-exegesis/lib/BenchmarkRunner.h
@@ -67,7 +67,7 @@ public:
 
   // Given a snippet, computes which registers the setup code needs to define.
   std::vector<unsigned>
-  computeRegsToDef(const std::vector<InstructionInstance> &Snippet) const;
+  computeRegsToDef(const std::vector<InstructionBuilder> &Snippet) const;
 
   // Scratch space to run instructions that touch memory.
   struct ScratchSpace {
diff --git a/tools/llvm-exegesis/lib/Latency.cpp b/tools/llvm-exegesis/lib/Latency.cpp
index 731efbf5515..12bc8cd32b0 100644
--- a/tools/llvm-exegesis/lib/Latency.cpp
+++ b/tools/llvm-exegesis/lib/Latency.cpp
@@ -62,18 +62,18 @@ LatencyBenchmarkRunner::generateTwoInstructionPrototype(
     const AliasingConfigurations Back(OtherInstr, Instr);
     if (Forward.empty() || Back.empty())
       continue;
-    InstructionInstance ThisII(Instr);
-    InstructionInstance OtherII(OtherInstr);
+    InstructionBuilder ThisIB(Instr);
+    InstructionBuilder OtherIB(OtherInstr);
     if (!Forward.hasImplicitAliasing())
-      setRandomAliasing(Forward, ThisII, OtherII);
+      setRandomAliasing(Forward, ThisIB, OtherIB);
     if (!Back.hasImplicitAliasing())
-      setRandomAliasing(Back, OtherII, ThisII);
+      setRandomAliasing(Back, OtherIB, ThisIB);
     SnippetPrototype Prototype;
     Prototype.Explanation =
         llvm::formatv("creating cycle through {0}.",
                       State.getInstrInfo().getName(OtherOpcode));
-    Prototype.Snippet.push_back(std::move(ThisII));
-    Prototype.Snippet.push_back(std::move(OtherII));
+    Prototype.Snippet.push_back(std::move(ThisIB));
+    Prototype.Snippet.push_back(std::move(OtherIB));
     return std::move(Prototype);
   }
   return llvm::make_error<BenchmarkFailure>(
diff --git a/tools/llvm-exegesis/lib/MCInstrDescView.cpp b/tools/llvm-exegesis/lib/MCInstrDescView.cpp
index 00283cb2003..39cb921d360 100644
--- a/tools/llvm-exegesis/lib/MCInstrDescView.cpp
+++ b/tools/llvm-exegesis/lib/MCInstrDescView.cpp
@@ -89,39 +89,39 @@ bool Instruction::hasMemoryOperands() const {
                      [](const Operand &Op) { return Op.IsMem; });
 }
 
-InstructionInstance::InstructionInstance(const Instruction &Instr)
+InstructionBuilder::InstructionBuilder(const Instruction &Instr)
     : Instr(Instr), VariableValues(Instr.Variables.size()) {}
 
-InstructionInstance::InstructionInstance(InstructionInstance &&) = default;
+InstructionBuilder::InstructionBuilder(InstructionBuilder &&) = default;
 
-InstructionInstance &InstructionInstance::
-operator=(InstructionInstance &&) = default;
+InstructionBuilder &InstructionBuilder::
+operator=(InstructionBuilder &&) = default;
 
-InstructionInstance::InstructionInstance(const InstructionInstance &) = default;
+InstructionBuilder::InstructionBuilder(const InstructionBuilder &) = default;
 
-InstructionInstance &InstructionInstance::
-operator=(const InstructionInstance &) = default;
+InstructionBuilder &InstructionBuilder::
+operator=(const InstructionBuilder &) = default;
 
-unsigned InstructionInstance::getOpcode() const {
+unsigned InstructionBuilder::getOpcode() const {
   return Instr.Description->getOpcode();
 }
 
-llvm::MCOperand &InstructionInstance::getValueFor(const Variable &Var) {
+llvm::MCOperand &InstructionBuilder::getValueFor(const Variable &Var) {
   return VariableValues[Var.Index];
 }
 
 const llvm::MCOperand &
-InstructionInstance::getValueFor(const Variable &Var) const {
+InstructionBuilder::getValueFor(const Variable &Var) const {
   return VariableValues[Var.Index];
 }
 
-llvm::MCOperand &InstructionInstance::getValueFor(const Operand &Op) {
+llvm::MCOperand &InstructionBuilder::getValueFor(const Operand &Op) {
   assert(Op.VariableIndex >= 0);
   return getValueFor(Instr.Variables[Op.VariableIndex]);
 }
 
 const llvm::MCOperand &
-InstructionInstance::getValueFor(const Operand &Op) const {
+InstructionBuilder::getValueFor(const Operand &Op) const {
   assert(Op.VariableIndex >= 0);
   return getValueFor(Instr.Variables[Op.VariableIndex]);
 }
@@ -131,7 +131,7 @@ static void randomize(const Instruction &Instr, const Variable &Var,
                       llvm::MCOperand &AssignedValue,
                       const llvm::BitVector &ForbiddenRegs);
 
-bool InstructionInstance::hasImmediateVariables() const {
+bool InstructionBuilder::hasImmediateVariables() const {
   return llvm::any_of(Instr.Variables, [this](const Variable &Var) {
     assert(!Var.TiedOperands.empty());
     const unsigned OpIndex = Var.TiedOperands[0];
@@ -141,7 +141,7 @@ bool InstructionInstance::hasImmediateVariables() const {
   });
 }
 
-void InstructionInstance::randomizeUnsetVariables(
+void InstructionBuilder::randomizeUnsetVariables(
     const llvm::BitVector &ForbiddenRegs) {
   for (const Variable &Var : Instr.Variables) {
     llvm::MCOperand &AssignedValue = getValueFor(Var);
@@ -150,7 +150,7 @@ void InstructionInstance::randomizeUnsetVariables(
   }
 }
 
-llvm::MCInst InstructionInstance::build() const {
+llvm::MCInst InstructionBuilder::build() const {
   llvm::MCInst Result;
   Result.setOpcode(Instr.Description->Opcode);
   for (const auto &Op : Instr.Operands)
@@ -261,10 +261,10 @@ static void randomize(const Instruction &Instr, const Variable &Var,
 }
 
 static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
-                                    InstructionInstance &II) {
+                                    InstructionBuilder &IB) {
   assert(ROV.Op);
   if (ROV.Op->IsExplicit) {
-    auto &AssignedValue = II.getValueFor(*ROV.Op);
+    auto &AssignedValue = IB.getValueFor(*ROV.Op);
     if (AssignedValue.isValid()) {
       assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
       return;
@@ -285,12 +285,12 @@ size_t randomBit(const llvm::BitVector &Vector) {
 }
 
 void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
-                       InstructionInstance &DefII, InstructionInstance &UseII) {
+                       InstructionBuilder &DefIB, InstructionBuilder &UseIB) {
   assert(!AliasingConfigurations.empty());
   assert(!AliasingConfigurations.hasImplicitAliasing());
   const auto &RandomConf = randomElement(AliasingConfigurations.Configurations);
-  setRegisterOperandValue(randomElement(RandomConf.Defs), DefII);
-  setRegisterOperandValue(randomElement(RandomConf.Uses), UseII);
+  setRegisterOperandValue(randomElement(RandomConf.Defs), DefIB);
+  setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB);
 }
 
 void DumpMCOperand(const llvm::MCRegisterInfo &MCRegisterInfo,
diff --git a/tools/llvm-exegesis/lib/MCInstrDescView.h b/tools/llvm-exegesis/lib/MCInstrDescView.h
index f390330fd76..823c9e6b0fe 100644
--- a/tools/llvm-exegesis/lib/MCInstrDescView.h
+++ b/tools/llvm-exegesis/lib/MCInstrDescView.h
@@ -39,7 +39,7 @@ struct Variable {
   llvm::SmallVector<unsigned, 2> TiedOperands;
   llvm::MCOperand AssignedValue;
   // The index of this Variable in Instruction.Variables and its associated
-  // Value in InstructionInstance.VariableValues.
+  // Value in InstructionBuilder.VariableValues.
   unsigned Index = -1;
 };
 
@@ -82,14 +82,14 @@ struct Instruction {
   llvm::BitVector UseRegisters; // The union of the aliased use registers.
 };
 
-// An instance of an Instruction holding values for each of its Variables.
-struct InstructionInstance {
-  InstructionInstance(const Instruction &Instr);
+// A builder for an Instruction holding values for each of its Variables.
+struct InstructionBuilder {
+  InstructionBuilder(const Instruction &Instr);
 
-  InstructionInstance(const InstructionInstance &);
-  InstructionInstance &operator=(const InstructionInstance &);
-  InstructionInstance(InstructionInstance &&);
-  InstructionInstance &operator=(InstructionInstance &&);
+  InstructionBuilder(const InstructionBuilder &);
+  InstructionBuilder &operator=(const InstructionBuilder &);
+  InstructionBuilder(InstructionBuilder &&);
+  InstructionBuilder &operator=(InstructionBuilder &&);
 
   unsigned getOpcode() const;
   llvm::MCOperand &getValueFor(const Variable &Var);
@@ -102,7 +102,7 @@ struct InstructionInstance {
   // Do not use any of the registers in `ForbiddenRegs`.
   void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs);
 
-  // Returns the instance as an llvm::MCInst. The InstructionInstance must be
+  // Returns the instance as an llvm::MCInst. The InstructionBuilder must be
   // fully allocated (no invalid variables).
   llvm::MCInst build() const;
 
@@ -129,7 +129,7 @@ struct SnippetPrototype {
   // If the prototype uses the provided scratch memory, the register in which
   // the pointer to this memory is passed in to the function.
   unsigned ScratchSpaceReg = 0;
-  std::vector<InstructionInstance> Snippet;
+  std::vector<InstructionBuilder> Snippet;
 };
 
 // Represents the assignment of a Register to an Operand.
@@ -186,7 +186,7 @@ size_t randomBit(const llvm::BitVector &Vector);
 // Picks a random configuration, then selects a random def and a random use from
 // it and finally set the selected values in the provided InstructionInstances.
 void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
-                       InstructionInstance &DefII, InstructionInstance &UseII);
+                       InstructionBuilder &DefIB, InstructionBuilder &UseIB);
 
 // Writes MCInst to OS.
 // This is not assembly but the internal LLVM's name for instructions and
diff --git a/tools/llvm-exegesis/lib/Target.h b/tools/llvm-exegesis/lib/Target.h
index ba25b1a3388..9f8fbc3cd91 100644
--- a/tools/llvm-exegesis/lib/Target.h
+++ b/tools/llvm-exegesis/lib/Target.h
@@ -48,7 +48,7 @@ public:
   }
 
   // Fills memory operands with references to the address at [Reg] + Offset.
-  virtual void fillMemoryOperands(InstructionInstance &II, unsigned Reg,
+  virtual void fillMemoryOperands(InstructionBuilder &IB, unsigned Reg,
                                   unsigned Offset) const {
     llvm_unreachable(
         "fillMemoryOperands() requires getScratchMemoryRegister() > 0");
diff --git a/tools/llvm-exegesis/lib/Uops.cpp b/tools/llvm-exegesis/lib/Uops.cpp
index 729b4847dbc..3089a98ac48 100644
--- a/tools/llvm-exegesis/lib/Uops.cpp
+++ b/tools/llvm-exegesis/lib/Uops.cpp
@@ -126,23 +126,23 @@ UopsBenchmarkRunner::~UopsBenchmarkRunner() = default;
 
 void UopsBenchmarkRunner::instantiateMemoryOperands(
     const unsigned ScratchSpaceReg,
-    std::vector<InstructionInstance> &Snippet) const {
+    std::vector<InstructionBuilder> &Snippet) const {
   if (ScratchSpaceReg == 0)
-    return;  // no memory operands.
+    return; // no memory operands.
   const auto &ET = State.getExegesisTarget();
   const unsigned MemStep = ET.getMaxMemoryAccessSize();
   const size_t OriginalSnippetSize = Snippet.size();
   size_t I = 0;
-  for (InstructionInstance &II : Snippet) {
-    ET.fillMemoryOperands(II, ScratchSpaceReg, I * MemStep);
+  for (InstructionBuilder &IB : Snippet) {
+    ET.fillMemoryOperands(IB, ScratchSpaceReg, I * MemStep);
     ++I;
   }
 
   while (Snippet.size() < kMinNumDifferentAddresses) {
-    InstructionInstance II = Snippet[I % OriginalSnippetSize];
-    ET.fillMemoryOperands(II, ScratchSpaceReg, I * MemStep);
+    InstructionBuilder IB = Snippet[I % OriginalSnippetSize];
+    ET.fillMemoryOperands(IB, ScratchSpaceReg, I * MemStep);
     ++I;
-    Snippet.push_back(std::move(II));
+    Snippet.push_back(std::move(IB));
   }
   assert(I * MemStep < ScratchSpace::kSize && "not enough scratch space");
 }
@@ -176,16 +176,16 @@ UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
   }
 
   const AliasingConfigurations SelfAliasing(Instr, Instr);
-  InstructionInstance II(Instr);
+  InstructionBuilder IB(Instr);
   if (SelfAliasing.empty()) {
     Prototype.Explanation = "instruction is parallel, repeating a random one.";
-    Prototype.Snippet.push_back(std::move(II));
+    Prototype.Snippet.push_back(std::move(IB));
     instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
     return std::move(Prototype);
   }
   if (SelfAliasing.hasImplicitAliasing()) {
     Prototype.Explanation = "instruction is serial, repeating a random one.";
-    Prototype.Snippet.push_back(std::move(II));
+    Prototype.Snippet.push_back(std::move(IB));
     instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
     return std::move(Prototype);
   }
@@ -205,9 +205,9 @@ UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
     for (const llvm::MCPhysReg Reg : Op.Tracker->sourceBits().set_bits()) {
       if (ScratchSpaceAliasedRegs && ScratchSpaceAliasedRegs->test(Reg))
         continue; // Do not use the scratch memory address register.
-      InstructionInstance TmpII = II;
-      TmpII.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
-      Prototype.Snippet.push_back(std::move(TmpII));
+      InstructionBuilder TmpIB = IB;
+      TmpIB.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
+      Prototype.Snippet.push_back(std::move(TmpIB));
     }
     instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
     return std::move(Prototype);
@@ -224,7 +224,7 @@ UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
       assert(PossibleRegisters.any() && "No register left to choose from");
       const auto RandomReg = randomBit(PossibleRegisters);
       Defs.set(RandomReg);
-      II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
+      IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
     }
   }
   // And pick random use values that are not reserved and don't alias with defs.
@@ -239,12 +239,12 @@ UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
       remove(PossibleRegisters, DefAliases);
       assert(PossibleRegisters.any() && "No register left to choose from");
       const auto RandomReg = randomBit(PossibleRegisters);
-      II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
+      IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
     }
   }
   Prototype.Explanation =
       "instruction has no tied variables picking Uses different from defs";
-  Prototype.Snippet.push_back(std::move(II));
+  Prototype.Snippet.push_back(std::move(IB));
   instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
   return std::move(Prototype);
 }
diff --git a/tools/llvm-exegesis/lib/Uops.h b/tools/llvm-exegesis/lib/Uops.h
index 103c1783975..58c1d347d81 100644
--- a/tools/llvm-exegesis/lib/Uops.h
+++ b/tools/llvm-exegesis/lib/Uops.h
@@ -62,7 +62,7 @@ private:
   //   mov eax, [rdi + 256]
   void
   instantiateMemoryOperands(unsigned ScratchSpaceReg,
-                            std::vector<InstructionInstance> &Snippet) const;
+                            std::vector<InstructionBuilder> &Snippet) const;
 };
 
 } // namespace exegesis
diff --git a/tools/llvm-exegesis/lib/X86/Target.cpp b/tools/llvm-exegesis/lib/X86/Target.cpp
index bdfa5a753b2..f958c8d99e7 100644
--- a/tools/llvm-exegesis/lib/X86/Target.cpp
+++ b/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -120,32 +120,32 @@ class ExegesisX86Target : public ExegesisTarget {
 
   unsigned getMaxMemoryAccessSize() const override { return 64; }
 
-  void fillMemoryOperands(InstructionInstance &II, unsigned Reg,
+  void fillMemoryOperands(InstructionBuilder &IB, unsigned Reg,
                           unsigned Offset) const override {
     // FIXME: For instructions that read AND write to memory, we use the same
     // value for input and output.
-    for (size_t I = 0, E = II.Instr.Operands.size(); I < E; ++I) {
-      const Operand *Op = &II.Instr.Operands[I];
+    for (size_t I = 0, E = IB.Instr.Operands.size(); I < E; ++I) {
+      const Operand *Op = &IB.Instr.Operands[I];
       if (Op->IsExplicit && Op->IsMem) {
         // Case 1: 5-op memory.
         assert((I + 5 <= E) && "x86 memory references are always 5 ops");
-        II.getValueFor(*Op) = llvm::MCOperand::createReg(Reg); // BaseReg
-        Op = &II.Instr.Operands[++I];
+        IB.getValueFor(*Op) = llvm::MCOperand::createReg(Reg); // BaseReg
+        Op = &IB.Instr.Operands[++I];
         assert(Op->IsMem);
         assert(Op->IsExplicit);
-        II.getValueFor(*Op) = llvm::MCOperand::createImm(1); // ScaleAmt
-        Op = &II.Instr.Operands[++I];
+        IB.getValueFor(*Op) = llvm::MCOperand::createImm(1); // ScaleAmt
+        Op = &IB.Instr.Operands[++I];
         assert(Op->IsMem);
         assert(Op->IsExplicit);
-        II.getValueFor(*Op) = llvm::MCOperand::createReg(0); // IndexReg
-        Op = &II.Instr.Operands[++I];
+        IB.getValueFor(*Op) = llvm::MCOperand::createReg(0); // IndexReg
+        Op = &IB.Instr.Operands[++I];
         assert(Op->IsMem);
         assert(Op->IsExplicit);
-        II.getValueFor(*Op) = llvm::MCOperand::createImm(Offset); // Disp
-        Op = &II.Instr.Operands[++I];
+        IB.getValueFor(*Op) = llvm::MCOperand::createImm(Offset); // Disp
+        Op = &IB.Instr.Operands[++I];
         assert(Op->IsMem);
         assert(Op->IsExplicit);
-        II.getValueFor(*Op) = llvm::MCOperand::createReg(0); // Segment
+        IB.getValueFor(*Op) = llvm::MCOperand::createReg(0); // Segment
         // Case2: segment:index addressing. We assume that ES is 0.
       }
     }