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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-09-15 15:06:26 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-09-15 15:06:26 +0000 |
| commit | 8a2b719477e2ea1b3553ee8960d31048369a027b (patch) | |
| tree | 25ab81f627e4141067a6270497aca7fefa782a93 /test/MC/Mips/mips64r6 | |
| parent | 1be5e0b1695a12534b8f8c64e83d5c2017201d5a (diff) | |
[mips] Add support for branch-likely pseudo-instructions
Differential Revision: http://reviews.llvm.org/D10537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247697 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Mips/mips64r6')
| -rw-r--r-- | test/MC/Mips/mips64r6/invalid.s | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/test/MC/Mips/mips64r6/invalid.s b/test/MC/Mips/mips64r6/invalid.s index ae980347f30..24a766727a1 100644 --- a/test/MC/Mips/mips64r6/invalid.s +++ b/test/MC/Mips/mips64r6/invalid.s @@ -2,15 +2,25 @@ # the assembler (e.g. invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text +local_label: .set noreorder .set noat - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved + bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled |