diff options
| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2016-04-22 16:53:15 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2016-04-22 16:53:15 +0000 |
| commit | 762ad970897c097161caec1484363ed6a11f1a7e (patch) | |
| tree | b8fed3a917bd8f065b1db4c2c5e20147d8fa7c47 /test/MC/Mips/mips64r6 | |
| parent | db55335b2e47f5c4340ee23f70728b221bc692bb (diff) | |
[mips][microMIPS] Revert commit r266861.
Commit r266861 was the reason for failing tests in LLVM test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267166 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Mips/mips64r6')
| -rw-r--r-- | test/MC/Mips/mips64r6/invalid.s | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/test/MC/Mips/mips64r6/invalid.s b/test/MC/Mips/mips64r6/invalid.s index d1b31376f21..a28b234ac15 100644 --- a/test/MC/Mips/mips64r6/invalid.s +++ b/test/MC/Mips/mips64r6/invalid.s @@ -12,6 +12,7 @@ local_label: align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate @@ -38,8 +39,6 @@ local_label: drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different - ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - ldc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate |