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2017-08-16Merge branches/gcc-6-branch rev 251111.Yvan Roux
Change-Id: I53b64fff4b70d6e8910ec081aab6060963fc16a0
2017-07-07Merge branches/gcc-6-branch rev 250045.Yvan Roux
Change-Id: Ib476af153a46d43eb0d966f8cee4eeaacce673b6
2017-06-13Merge branches/gcc-6-branch rev 249140.Yvan Roux
Change-Id: I6b73a3960133b7cfc1a59998d7411d8a247b84e0
2017-05-12Merge branches/gcc-6-branch rev 247789.Yvan Roux
Change-Id: Ib5fcddc79d6b7cab079df944d9b5317f37821ad9
2017-03-14 libgcc/Yvan Roux
Backport from trunk r245508. 2017-02-16 Andrew Pinski <apinski@cavium.com> * config/aarch64/value-unwind.h: New file. * config.host (aarch64*-*-*): Add aarch64/value-unwind.h to tm_file. Change-Id: I8dfb73e83ab9811f95f4dc76cbc0b74d206c33aa
2017-01-30 libgcc/Christophe Lyon
Backport from trunk r238215. 2016-07-11 Hale Wang <hale.wang@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/arm/lib1funcs.S: Add new wrapper. Change-Id: I46326f9f5e5db3bda9c87a514e8b987883d8fede
2017-01-11 gcc/Christophe Lyon
Backport from trunk r240504. 2016-09-26 Thomas Preud'homme <thomas.preudhomme@arm.com> * tree.h (memmodel_from_int, memmodel_base, is_mm_relaxed, is_mm_consume, is_mm_acquire, is_mm_release, is_mm_acq_rel, is_mm_seq_cst, is_mm_sync): Move to ... * memmodel.h: This. New file. * builtins.c: Include memmodel.h. * optabs.c: Likewise. * tsan.c: Likewise. * config/aarch64/aarch64.c: Likewise. * config/alpha/alpha.c: Likewise. * config/arm/arm.c: Likewise. * config/i386/i386.c: Likewise. * config/ia64/ia64.c: Likewise. * config/mips/mips.c: Likewise. * config/rs6000/rs6000.c: Likewise. * config/sparc/sparc.c: Likewise. * genconditions.c: Include memmodel.h in generated file. * genemit.c: Likewise. * genoutput.c: Likewise. * genpeep.c: Likewise. * genpreds.c: Likewise. * genrecog.c: Likewise. gcc/c-family/ Backport from trunk r240504. 2016-09-26 Thomas Preud'homme <thomas.preudhomme@arm.com> * c-common.c: Include memmodel.h. gcc/ Backport from trunk r241507. 2016-10-25 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/constraints.md (Q constraint): Document its use for Thumb-1. (Pf constraint): New constraint for relaxed, consume or relaxed memory models. * config/arm/sync.md (atomic_load<mode>): Add new ARMv8-M Baseline only alternatives to allow any register when memory model matches Pf and thus lda is used, but only low registers otherwise. Use unpredicated output template for Thumb-1 targets. (atomic_store<mode>): Likewise for stl. (arm_load_exclusive<mode>): Add new ARMv8-M Baseline only alternative whose output template does not have predication. (arm_load_acquire_exclusive<mode>): Likewise. (arm_load_exclusivesi): Likewise. (arm_load_acquire_exclusivesi): Likewise. (arm_store_release_exclusive<mode>): Likewise. (arm_store_exclusive<mode>): Use unpredicated output template for Thumb-1 targets. gcc/ Backport from trunk r241577. 2016-10-26 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (arm_expand_compare_and_swap): Add new bdst local variable. Add the new parameter to the insn generator. Set that parameter to be CC flag for 32-bit targets, bval otherwise. Set the return value from the negation of that parameter for Thumb-1, keeping the logic unchanged otherwise except for using bdst as the destination register of the compare_and_swap insn. (arm_split_compare_and_swap): Add explanation about how is the value returned to the function comment. Rename scratch variable to neg_bval. Adapt initialization of variables holding operands to the new operand numbers. Use return register to hold result of store exclusive for Thumb-1, scratch register otherwise. Construct the appropriate cbranch for Thumb-1 targets, keeping the logic unchanged for 32-bit targets. Guard Z flag setting to restrict to 32bit targets. Use gen_cbranchsi4 rather than hand-written conditional branch to loop for strongly ordered compare_and_swap. * config/arm/predicates.md (cc_register_operand): New predicate. * config/arm/sync.md (atomic_compare_and_swap<mode>_1): Use a match_operand with the new predicate to accept either the CC flag or a destination register for the boolean return value, restricting it to CC flag only via constraint. Adapt operand numbers accordingly. gcc/ Backport from trunk r241578. 2016-10-26 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/sync.md (atomic_compare_and_swap<mode>_1): Add new ARMv8-M Baseline only alternatives to (i) hold store atomic success value in a return register rather than a scratch register, (ii) use a low register for it and to (iii) ensure the cbranchsi insn generated by the split respect the constraints of Thumb-1 cbranchsi4_insn and cbranchsi4_scratch. * config/arm/thumb1.md (cbranchsi4_insn): Add comment to indicate constraints must match those in atomic_compare_and_swap. (cbranchsi4_scratch): Likewise. gcc/ Backport from trunk r241614. 2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (arm_split_atomic_op): Add function comment. Add logic to to decide whether to copy over old value to register for new value. * config/arm/sync.md: Add comments explaning why mode and code attribute are not defined in iterators.md (thumb1_atomic_op_str): New code attribute. (thumb1_atomic_newop_str): Likewise. (thumb1_atomic_fetch_op_str): Likewise. (thumb1_atomic_fetch_newop_str): Likewise. (thumb1_atomic_fetch_oldop_str): Likewise. (atomic_exchange<mode>): Add new ARMv8-M Baseline only alternatives to mirror the more restrictive constraints of the Thumb-1 insns after split compared to Thumb-2 counterpart insns. (atomic_<sync_optab><mode>): Likewise. Add comment to keep constraints in sync with non atomic version. (atomic_nand<mode>): Likewise. (atomic_fetch_<sync_optab><mode>): Likewise. (atomic_fetch_nand<mode>): Likewise. (atomic_<sync_optab>_fetch<mode>): Likewise. (atomic_nand_fetch<mode>): Likewise. * config/arm/thumb1.md (thumb1_addsi3): Add comment to keep contraint in sync with atomic version. (thumb1_subsi3_insn): Likewise. (thumb1_andsi3_insn): Likewise. (thumb1_iorsi3_insn): Likewise. (thumb1_xorsi3_insn): Likewise. gcc/ Backport from trunk r241615. 2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline. (TARGET_HAVE_LDREXBH): Likewise. (TARGET_HAVE_LDACQ): Likewise. gcc/testsuite/ Backport from trunk r241615. 2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test. * gcc.target/arm/atomic-op-acq_rel-3.c: Likewise. * gcc.target/arm/atomic-op-acquire-3.c: Likewise. * gcc.target/arm/atomic-op-char-3.c: Likewise. * gcc.target/arm/atomic-op-consume-3.c: Likewise. * gcc.target/arm/atomic-op-int-3.c: Likewise. * gcc.target/arm/atomic-op-relaxed-3.c: Likewise. * gcc.target/arm/atomic-op-release-3.c: Likewise. * gcc.target/arm/atomic-op-seq_cst-3.c: Likewise. * gcc.target/arm/atomic-op-short-3.c: Likewise. gcc/ Backport from trunk r241848. 2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm-arches.def (armv8-m.base): Set Cortex-M23 as representative core for this architecture. * config/arm/arm-cores.def (cortex-m23): Define new processor. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * config/arm/arm.c (arm_v6m_tune): Add Cortex-M23 to the list of cores this tuning parameters apply to in the comment. * config/arm/bpabi.h (BE8_LINK_SPEC): Add Cortex-M23 to the list of valid -mcpu options. * doc/invoke.texi (ARM Options): Document new Cortex-M23 processor. gcc/ Backport from trunk r241849. 2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm-arches.def (armv8-m.main+dsp): Set Cortex-M33 as representative core for this architecture. * config/arm/arm-cores.def (cortex-m33): Define new processor. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * config/arm/bpabi.h (BE8_LINK_SPEC): Add Cortex-M33 to the list of valid -mcpu options. * doc/invoke.texi (ARM Options): Document new Cortex-M33 processor. gcc/ Backport from trunk r242596. 2016-11-18 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm-protos.h (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32, FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E, FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM, FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV, FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT, FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST): Reindent comment, add final dot when missing and make value unsigned. (arm_feature_set): Use unsigned entries instead of unsigned long. gcc/ Backport from trunk r242597. 2016-11-18 Terry Guo <terry.guo@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * common/config/arm/arm-common.c (arm_target_thumb_only): New function. * config/arm/arm-opts.h: Include arm-flags.h. (struct arm_arch_core_flag): Define. (arm_arch_core_flags): Define. * config/arm/arm-protos.h: Include arm-flags.h (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32, FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E, FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM, FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV, FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT, FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST, FL_TUNE, FL_FOR_ARCH2, FL_FOR_ARCH3, FL_FOR_ARCH3M, FL_FOR_ARCH4, FL_FOR_ARCH4T, FL_FOR_ARCH5, FL_FOR_ARCH5T, FL_FOR_ARCH5E, FL_FOR_ARCH5TE, FL_FOR_ARCH5TEJ, FL_FOR_ARCH6, FL_FOR_ARCH6J, FL_FOR_ARCH6K, FL_FOR_ARCH6Z, FL_FOR_ARCH6ZK, FL_FOR_ARCH6KZ, FL_FOR_ARCH6T2, FL_FOR_ARCH6M, FL_FOR_ARCH7, FL_FOR_ARCH7A, FL_FOR_ARCH7VE, FL_FOR_ARCH7R, FL_FOR_ARCH7M, FL_FOR_ARCH7EM, FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A, FL2_FOR_ARCH8_2A, FL_FOR_ARCH8M_BASE, FL_FOR_ARCH8M_MAIN, arm_feature_set, ARM_FSET_MAKE, ARM_FSET_MAKE_CPU1, ARM_FSET_MAKE_CPU2, ARM_FSET_CPU1, ARM_FSET_CPU2, ARM_FSET_EMPTY, ARM_FSET_ANY, ARM_FSET_HAS_CPU1, ARM_FSET_HAS_CPU2, ARM_FSET_HAS_CPU, ARM_FSET_ADD_CPU1, ARM_FSET_ADD_CPU2, ARM_FSET_DEL_CPU1, ARM_FSET_DEL_CPU2, ARM_FSET_UNION, ARM_FSET_INTER, ARM_FSET_XOR, ARM_FSET_EXCLUDE, ARM_FSET_IS_EMPTY, ARM_FSET_CPU_SUBSET): Move to ... * config/arm/arm-flags.h: This new file. * config/arm/arm.h (TARGET_MODE_SPEC_FUNCTIONS): Define. (EXTRA_SPEC_FUNCTIONS): Add TARGET_MODE_SPEC_FUNCTIONS to its value. (TARGET_MODE_SPECS): Define. (DRIVER_SELF_SPECS): Add TARGET_MODE_SPECS to its value. gcc/testsuite/ Backport from trunk r242597. 2016-11-18 Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/optional_thumb-1.c: New test. * gcc.target/arm/optional_thumb-2.c: New test. * gcc.target/arm/optional_thumb-3.c: New test. gcc/ Backport from trunk r242696. 2016-11-22 Thomas Preud'homme <thomas.preudhomme@arm.com> * config.gcc: Allow new rmprofile value for configure option --with-multilib-list. * config/arm/t-rmprofile: New file. * doc/install.texi (--with-multilib-list): Document new rmprofile value for ARM. gcc/testsuite/ Backport from trunk r243013. 2016-11-30 Thomas Preud'homme <thomas.preudhomme@arm.com> * lib/target-supports.exp (add_options_for_arm_arch_v6m): Add -mfloat-abi=soft option. (add_options_for_arm_arch_v8m_base): Likewise. Reindent containing foreach loop. gcc/ Backport from trunk r243015. 2016-11-30 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/t-rmprofile: Add mappings for Cortex-M23 and Cortex-M33. gcc/ Backport from trunk r243187. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config.gcc (extra_headers): Added arm_cmse.h. * config/arm/arm-arches.def (ARM_ARCH): (armv8-m): Add FL2_CMSE. (armv8-m.main): Likewise. (armv8-m.main+dsp): Likewise. * config/arm/arm-c.c (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro. * config/arm/arm-flags.h: Define FL2_CMSE. * config/arm.c (arm_arch_cmse): New. (arm_option_override): New error for unsupported cmse target. * config/arm/arm.h (arm_arch_cmse): New. * config/arm/arm.opt (mcmse): New. * config/arm/arm_cmse.h: New file. * doc/invoke.texi (ARM Options): Add -mcmse. * doc/sourcebuild.texi (arm_cmse_ok): Add new effective target. * doc/extend.texi: Add ARMv8-M Security Extensions entry. gcc/testsuite/ Backport from trunk r243187. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/cmse.exp: New. * gcc.target/arm/cmse/cmse-1.c: New. * gcc.target/arm/cmse/cmse-12.c: New. * lib/target-supports.exp (check_effective_target_arm_cmse_ok): New. libgcc/ Backport from trunk r243187. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/t-arm (HAVE_CMSE): New. * config/arm/cmse.c: New. gcc/ Backport from trunk r243188. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (arm_handle_cmse_nonsecure_entry): New. (arm_attribute_table): Added cmse_nonsecure_entry (arm_compute_func_type): Handle cmse_nonsecure_entry. (cmse_func_args_or_return_in_stack): New. (arm_handle_cmse_nonsecure_entry): New. * config/arm/arm.h (ARM_FT_CMSE_ENTRY): New macro define. (IS_CMSE_ENTRY): Likewise. * doc/extend.texi (ARM ARMv8-M Security Extensions): New attribute. gcc/testsuite/ Backport from trunk r243188. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/cmse-3.c: New. gcc/ Backport from trunk r243189. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (use_return_insn): Change to return with bxns when cmse_nonsecure_entry. (output_return_instruction): Likewise. (arm_output_function_prologue): Likewise. (thumb_pop): Likewise. (thumb_exit): Likewise. (thumb2_expand_return): Assert that entry functions always have simple returns. (arm_expand_epilogue): Handle entry functions. (arm_function_ok_for_sibcall): Disable sibcall for entry functions. (arm_asm_declare_function_name): New. * config/arm/arm-protos.h (arm_asm_declare_function_name): New. * config/arm/elf.h (ASM_DECLARE_FUNCTION_NAME): Redefine to use arm_asm_declare_function_name. gcc/testsuite/ Backport from trunk r243189. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/cmse-4.c: New. * gcc.target/arm/cmse/cmse-9.c: New. * gcc.target/arm/cmse/cmse-10.c: New. gcc/ Backport from trunk r243190. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (output_return_instruction): Clear registers. (thumb2_expand_return): Likewise. (thumb1_expand_epilogue): Likewise. (thumb_exit): Likewise. (arm_expand_epilogue): Likewise. (cmse_nonsecure_entry_clear_before_return): New. (comp_not_to_clear_mask_str_un): New. (compute_not_to_clear_mask): New. * config/arm/thumb1.md (*epilogue_insns): Change length attribute. * config/arm/thumb2.md (*thumb2_return): Disable for cmse_nonsecure_entry functions. (*thumb2_cmse_entry_return): Duplicate thumb2_return pattern for cmse_nonsecure_entry functions. gcc/testsuite/ Backport from trunk r243190. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/cmse.exp: Test different multilibs separate. * gcc.target/arm/cmse/struct-1.c: New. * gcc.target/arm/cmse/bitfield-1.c: New. * gcc.target/arm/cmse/bitfield-2.c: New. * gcc.target/arm/cmse/bitfield-3.c: New. * gcc.target/arm/cmse/baseline/cmse-2.c: New. * gcc.target/arm/cmse/baseline/softfp.c: New. * gcc.target/arm/cmse/mainline/soft/cmse-5.c: New. * gcc.target/arm/cmse/mainline/hard/cmse-5.c: New. * gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New. * gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New. * gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New. gcc/ Backport from trunk r243191. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (gimplify.h): New include. (arm_handle_cmse_nonsecure_call): New. (arm_attribute_table): Added cmse_nonsecure_call. (arm_comp_type_attributes): Deny compatibility of function types with without the cmse_nonsecure_call attribute. * doc/extend.texi (ARM ARMv8-M Security Extensions): New attribute. gcc/testsuite/ Backport from trunk r243191. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/cmse-3.c: Add tests. * gcc.target/arm/cmse/cmse-4.c: Add tests. * gcc.target/arm/cmse/cmse-15.c: New. gcc/ Backport from trunk r243192. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (detect_cmse_nonsecure_call): New. (cmse_nonsecure_call_clear_caller_saved): New. (arm_reorg): Use cmse_nonsecure_call_clear_caller_saved. (arm_function_ok_for_sibcall): Disable sibcalls for cmse_nonsecure_call. * config/arm/arm-protos.h (detect_cmse_nonsecure_call): New. * config/arm/arm.md (call): Handle cmse_nonsecure_entry. (call_value): Likewise. (nonsecure_call_internal): New. (nonsecure_call_value_internal): New. * config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New. (*nonsecure_call_value_reg_thumb1_v5): New. * config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New. (*nonsecure_call_value_reg_thumb2): New. * config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New. gcc/testsuite/ Backport from trunk r243192. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/cmse.exp: Run tests in mainline dir. * gcc.target/arm/cmse/cmse-9.c: Added some extra tests. * gcc.target/arm/cmse/cmse-14.c: New. * gcc.target/arm/cmse/baseline/bitfield-4.c: New. * gcc.target/arm/cmse/baseline/bitfield-5.c: New. * gcc.target/arm/cmse/baseline/bitfield-6.c: New. * gcc.target/arm/cmse/baseline/bitfield-7.c: New. * gcc.target/arm/cmse/baseline/bitfield-8.c: New. * gcc.target/arm/cmse/baseline/bitfield-9.c: New. * gcc.target/arm/cmse/baseline/bitfield-and-union-1.c: New. * gcc.target/arm/cmse/baseline/cmse-11.c: New. * gcc.target/arm/cmse/baseline/cmse-13.c: New. * gcc.target/arm/cmse/baseline/cmse-6.c: New. * gcc.target/arm/cmse/baseline/union-1.c: New. * gcc.target/arm/cmse/baseline/union-2.c: New. * gcc.target/arm/cmse/mainline/bitfield-4.c: New. * gcc.target/arm/cmse/mainline/bitfield-5.c: New. * gcc.target/arm/cmse/mainline/bitfield-6.c: New. * gcc.target/arm/cmse/mainline/bitfield-7.c: New. * gcc.target/arm/cmse/mainline/bitfield-8.c: New. * gcc.target/arm/cmse/mainline/bitfield-9.c: New. * gcc.target/arm/cmse/mainline/bitfield-and-union-1.c: New. * gcc.target/arm/cmse/mainline/union-1.c: New. * gcc.target/arm/cmse/mainline/union-2.c: New. * gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: New. * gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: New. * gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: New. * gcc.target/arm/cmse/mainline/hard/cmse-13.c: New. * gcc.target/arm/cmse/mainline/hard/cmse-7.c: New. * gcc.target/arm/cmse/mainline/hard/cmse-8.c: New. * gcc.target/arm/cmse/mainline/soft/cmse-13.c: New. * gcc.target/arm/cmse/mainline/soft/cmse-7.c: New. * gcc.target/arm/cmse/mainline/soft/cmse-8.c: New. * gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: New. * gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: New. * gcc.target/arm/cmse/mainline/softfp/cmse-13.c: New. * gcc.target/arm/cmse/mainline/softfp/cmse-7.c: New. * gcc.target/arm/cmse/mainline/softfp/cmse-8.c: New. libgcc/ Backport from trunk r243192. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/cmse_nonsecure_call.S: New. * config/arm/t-arm: Compile cmse_nonsecure_call.S gcc/ Backport from trunk r243193. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm-builtins.c (arm_builtins): Define ARM_BUILTIN_CMSE_NONSECURE_CALLER. (bdesc_2arg): Add line for cmse_nonsecure_caller. (arm_init_builtins): Handle cmse_nonsecure_caller. (arm_expand_builtin): Likewise. * config/arm/arm_cmse.h (cmse_nonsecure_caller): New. gcc/testsuite/ Backport from trunk r243193. 2016-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/cmse-1.c: Add test for cmse_nonsecure_caller. gcc/ Backport from trunk r243216. 2016-12-01 Jeff Law <law@redhat.com> * config/arm/arm.c (arm_handle_cmse_nonsecure_call): Remove unused variable main_variant. Change-Id: Ibe821b25c811c214c51d5cbaceb4ea960c619633
2017-01-09Merge branches/gcc-6-branch rev 244220.Yvan Roux
Change-Id: I9f2d907c75595859355f909019b9109011440154
2016-12-13Merge branches/gcc-6-branch rev 243594.Yvan Roux
Change-Id: I681a233c1e96ce184d241bab38b61cd8ac8f08a8
2016-10-14 gcc/Yvan Roux
Backport from trunk r238079. 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to decide whether to prevent some libgcc routines being included for some multilibs rather than __ARM_ARCH_6M__ and add comment to indicate the link between this condition and the one in libgcc/config/arm/lib1func.S. gcc/testsuite/ Backport from trunk r238079. 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> * lib/target-supports.exp (check_effective_target_arm_cortex_m): Use __ARM_ARCH_ISA_ARM to test for Cortex-M devices. libgcc/ Backport from trunk r238079. 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/bpabi-v6m.S: Clarify what architectures is the implementation suitable for. * config/arm/lib1funcs.S (__prefer_thumb__): Define among other cases for all Thumb-1 only targets. (NOT_ISA_TARGET_32BIT): Define for Thumb-1 only targets. (THUMB_LDIV0): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__. (EQUIV): Likewise. (ARM_FUNC_ALIAS): Likewise. (umodsi3): Add check to __ARM_ARCH_ISA_THUMB != 1 to guard the idiv version. (modsi3): Likewise. (clzsi2): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__. (clzdi2): Likewise. (ctzsi2): Likewise. (L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__ in guard for checking whether it is defined. (final includes): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__ and add comment to indicate the connection between this condition and the one in gcc/config/arm/elf.h. * config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__. * config/arm/t-softfp: Likewise. libgcc/ Backport from trunk r238080. 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/lib1funcs.S (HAVE_ARM_CLZ): Define for ARMv6* or later and ARMv5t* rather than for a fixed list of architectures. gcc/ Backport from trunk r238081. 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm-arches.def (armv8-m.base): Define new architecture. (armv8-m.main): Likewise. (armv8-m.main+dsp): Likewise. * config/arm/arm-protos.h (FL_FOR_ARCH8M_BASE): Define. (FL_FOR_ARCH8M_MAIN): Likewise. * config/arm/arm-tables.opt: Regenerate. * config/arm/bpabi.h: Add armv8-m.base, armv8-m.main and armv8-m.main+dsp to BE8_LINK_SPEC. * config/arm/arm.h (TARGET_HAVE_LDACQ): Exclude ARMv8-M. (enum base_architecture): Add BASE_ARCH_8M_BASE and BASE_ARCH_8M_MAIN. * config/arm/arm.c (arm_arch_name): Increase size to work with ARMv8-M Baseline and Mainline. (arm_option_override_internal): Also disable arm_restrict_it when !arm_arch_notm. Update comment for -munaligned-access to also cover ARMv8-M Baseline. (arm_file_start): Increase buffer size for printing architecture name. * doc/invoke.texi: Document architectures armv8-m.base, armv8-m.main and armv8-m.main+dsp. (mno-unaligned-access): Clarify that this is disabled by default for ARMv8-M Baseline architectures as well. gcc/testsuite/ Backport from trunk r238081. 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> * lib/target-supports.exp: Generate add_options_for_arm_arch_FUNC and check_effective_target_arm_arch_FUNC_multilib for ARMv8-M Baseline and ARMv8-M Mainline architectures. libgcc/ Backport from trunk r238081. 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/lib1funcs.S (__ARM_ARCH__): Define to 8 for ARMv8-M. gcc/ Backport from trunk r238082. 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm-protos.h: Reindent FL_FOR_* macro definitions. gcc/ Backport from trunk r238083. 2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.h (TARGET_USE_MOVT): Check MOVT/MOVW availability with TARGET_HAVE_MOVT. (TARGET_HAVE_MOVT): Define. * config/arm/arm.c (const_ok_for_op): Check MOVT/MOVW availability with TARGET_HAVE_MOVT. * config/arm/arm.md (arm_movt): Use TARGET_HAVE_MOVT to check MOVT availability. (addsi splitter): Use TARGET_THUMB && TARGET_HAVE_MOVT rather than TARGET_THUMB2. (symbol_refs movsi splitter): Remove TARGET_32BIT check. (arm_movtas_ze): Use TARGET_HAVE_MOVT to check MOVT availability. * config/arm/constraints.md (define_constraint "j"): Use TARGET_HAVE_MOVT to check MOVT availability. gcc/ Backport from trunk r238288. 2016-07-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.h (TARGET_HAVE_MOVT): Include ARMv8-M as having MOVT. * config/arm/arm.c (arm_arch_name): (const_ok_for_op): Check MOVT/MOVW availability with TARGET_HAVE_MOVT. (thumb_legitimate_constant_p): Strip the high part of a label_ref. (thumb1_rtx_costs): Also return 0 if setting a half word constant and MOVW is available and replace (unsigned HOST_WIDE_INT) INTVAL by UINTVAL. (thumb1_size_rtx_costs): Make set of half word constant also cost 1 extra instruction if MOVW is available. Use a cost variable incremented by COSTS_N_INSNS (1) when the condition match rather than returning an arithmetic expression based on COSTS_N_INSNS. Make constant with bottom half word zero cost 2 instruction if MOVW is available. * config/arm/arm.md (define_attr "arch"): Add v8mb. (define_attr "arch_enabled"): Set to yes if arch value is v8mb and target is ARMv8-M Baseline. (arm_movt): New unpredicable alternative for ARMv8-M Baseline. (arm_movtas_ze): Likewise. * config/arm/thumb1.md (thumb1_movdi_insn): Add ARMv8-M Baseline only alternative for constants satisfying j constraint. (thumb1_movsi_insn): Likewise. (movsi splitter for K alternative): Tighten condition to not trigger if movt is available and j constraint is satisfied. (Pe immediate splitter): Likewise. (thumb1_movhi_insn): Add ARMv8-M Baseline only alternative for constant fitting in an halfword to use MOVW. * doc/sourcebuild.texi (arm_thumb1_movt_ok): Document new ARM effective target. gcc/testsuite/ Backport from trunk r238288. 2016-07-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * lib/target-supports.exp (check_effective_target_arm_thumb1_movt_ok): Define effective target. * gcc.target/arm/pr42574.c: Require arm_thumb1_ok and !arm_thumb1_movt_ok to exclude ARMv8-M Baseline. * gcc.target/arm/movhi_movw.c: New test. * gcc.target/arm/movsi_movw.c: Likewise. * gcc.target/arm/movdi_movw.c: Likewise. gcc/ Backport from trunk r238289. 2016-07-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.h (TARGET_HAVE_CBZ): Define. (TARGET_IDIV): Set for all Thumb targets provided they have hardware divide feature. * config/arm/arm.md (divsi3): New unpredicable alternative for ARMv8-M Baseline. Make initial alternative TARGET_32BIT only. (udivsi3): Likewise. * config/arm/thumb1.md (thumb1_cbz): New define_insn. * doc/sourcebuild.texi (arm_thumb1_cbz_ok): Document new effective target. gcc/testsuite/ Backport from trunk r238289. 2016-07-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * lib/target-supports.exp (check_effective_target_arm_thumb1_cbz_ok): Add new arm_thumb1_cbz_ok effective target. * gcc.target/arm/cbz.c: New test. gcc/testsuite/ Backport from trunk r238331. 2016-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/pr42574.c: Add missing target keyword for the dg-do selector and enclose boolean expression in curly braces. gcc/ Backport from trunk r238348. 2016-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline. (TARGET_HAVE_LDACQD): New macro. * config/arm/sync.md (atomic_loaddi): Use TARGET_HAVE_LDACQD rather than TARGET_HAVE_LDACQ. (arm_load_acquire_exclusivedi): Likewise. (arm_store_release_exclusivedi): Likewise. gcc/testsuite/ Backport from trunk r238348. 2016-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/atomic-comp-swap-release-acquire.c: Rename into ... * gcc.target/arm/atomic-comp-swap-release-acquire-1.c: This. * gcc.target/arm/atomic-op-acq_rel.c: Rename into ... * gcc.target/arm/atomic-op-acq_rel-1.c: This. * gcc.target/arm/atomic-op-acquire.c: Rename into ... * gcc.target/arm/atomic-op-acquire-1.c: This. * gcc.target/arm/atomic-op-char.c: Rename into ... * gcc.target/arm/atomic-op-char-1.c: This. * gcc.target/arm/atomic-op-consume.c: Rename into ... * gcc.target/arm/atomic-op-consume-1.c: This. * gcc.target/arm/atomic-op-int.c: Rename into ... * gcc.target/arm/atomic-op-int-1.c: This. * gcc.target/arm/atomic-op-relaxed.c: Rename into ... * gcc.target/arm/atomic-op-relaxed-1.c: This. * gcc.target/arm/atomic-op-release.c: Rename into ... * gcc.target/arm/atomic-op-release-1.c: This. * gcc.target/arm/atomic-op-seq_cst.c: Rename into ... * gcc.target/arm/atomic-op-seq_cst-1.c: This. * gcc.target/arm/atomic-op-short.c: Rename into ... * gcc.target/arm/atomic-op-short-1.c: This. * gcc.target/arm/atomic-comp-swap-release-acquire-2.c: New test. * gcc.target/arm/atomic-op-acq_rel-2.c: Likewise. * gcc.target/arm/atomic-op-acquire-2.c: Likewise. * gcc.target/arm/atomic-op-char-2.c: Likewise. * gcc.target/arm/atomic-op-consume-2.c: Likewise. * gcc.target/arm/atomic-op-int-2.c: Likewise. * gcc.target/arm/atomic-op-relaxed-2.c: Likewise. * gcc.target/arm/atomic-op-release-2.c: Likewise. * gcc.target/arm/atomic-op-seq_cst-2.c: Likewise. * gcc.target/arm/atomic-op-short-2.c: Likewise. gcc/ Backport from trunk r239888. 2016-08-31 Eric Botcazou <ebotcazou@adacore.com> * config/arm/arm.c (thumb1_size_rtx_costs) <SET>: Add missing guard. gcc/testsuite/ Backport from trunk r241086. 2016-10-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/movhi_movw.c: Enable test for ARM mode. * gcc.target/arm/movsi_movw.c: Likewise. * gcc.target/arm/movdi_movw.c: Likewise and adapt scan-assembler directive to work on big endian targets. Change-Id: I9fea67c44aa10d639644c90a4b436d4f809da9fc
2016-09-07 libgcc/Yvan Roux
Backport from trunk r238584. 2016-07-21 Aurelien Jarno <aurelien@aurel32.net> PR target/59833 * config/arm/ieee754-df.S (extendsfdf2): Convert sNaN to qNaN. Change-Id: Ic9f475b0bc3bf1c5eb473b0cb9c05df69930ec72
2016-08-22Merge branches/gcc-6-branch rev 239654.Yvan Roux
Change-Id: I21e71f9dc10e3bedc0760cd5cc6b8d36234e3d41
2016-06-14 libgcc/Christophe Lyon
Backport from trunk r235291. 2016-04-20 Martin Galvan <martin.galvan@tallertechnologies.com> * config/arm/ieee754-df.S: Fix typos in comments. Change-Id: Ic13d425bda6728b0aba59509706a9baea5bbf629
2016-04-27Update ChangeLog and version files for releasegcc-6_1_0-releasegccadmin
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-6-branch@235473 138bc75d-0d04-0410-961f-82ee72b054a4
2016-03-29 * config/ft32/ft32.opt (mnodiv): New.jamesbowman
* config/ft32/ft32.md (*divsi3, *modsi3): Qualify with TARGET_NODIV. * doc/invoke.texi (FT32 Options -mnodiv): New. * libgcc/config/ft32/lib1funcs.S (*divsi3, *modsi3): New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@234516 138bc75d-0d04-0410-961f-82ee72b054a4
2016-03-222016-03-22 Michael Meissner <meissner@linux.vnet.ibm.com>meissner
PR libgcc/70363 * config/rs6000/extendkftf2-sw.c (__extendkftf2_sw): If libgcc was built with an assembler that does not support ISA 3.0 instructions, rename __extendkftf2_sw to __extendkftf2. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@234408 138bc75d-0d04-0410-961f-82ee72b054a4
2016-03-16Save call-clobbered registers in _mcount on 32-bit Solaris/x86 (PR target/38239)ro
PR target/38239 * config/sol2/gmon.c [__i386__] (_mcount): Save and restore call-clobbered registers. (internal_mcount): Remove __i386__ handling. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@234256 138bc75d-0d04-0410-961f-82ee72b054a4
2016-02-262016-02-26 Paul E. Murphy <murphyp@linux.vnet.ibm.com>wschmidt
Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/sfp-machine.h (_FP_DECL_EX): Declare _fpsr as a union of u64 and double. (FP_TRAPPING_EXCEPTIONS): Return a bitmask of trapping exceptions. (FP_INIT_ROUNDMODE): Read the fpscr instead of writing a mystery value. (FP_ROUNDMODE): Update the usage of _fpscr. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233756 138bc75d-0d04-0410-961f-82ee72b054a4
2016-02-17xtensa: fix libgcc build with --text-section-literalsjcmvbkbc
Functions __muldf3_aux, __divdf3_aux, __mulsf3_aux and __divsf3_aux don't start with leaf_entry, so they need explicit .literal_position, otherwise libgcc build fails in the presence of --text-section-literals. 2016-02-17 Max Filippov <jcmvbkbc@gmail.com> libgcc/ * config/xtensa/ieee754-df.S (__muldf3_aux, __divdf3_aux): Add .literal_position before the function. * config/xtensa/ieee754-sf.S (__mulsf3_aux, __divsf3_aux): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233505 138bc75d-0d04-0410-961f-82ee72b054a4
2016-02-15S/390: Add -fsplit-stack supportkrebbel
libgcc/ChangeLog: * config.host: Use t-stack and t-stack-s390 for s390*-*-linux. * config/s390/morestack.S: New file. * config/s390/t-stack-s390: New file. * generic-morestack.c (__splitstack_find): Add s390-specific code. gcc/ChangeLog: * common/config/s390/s390-common.c (s390_supports_split_stack): New function. (TARGET_SUPPORTS_SPLIT_STACK): New macro. * config/s390/s390-protos.h: Add s390_expand_split_stack_prologue. * config/s390/s390.c (struct machine_function): New field split_stack_varargs_pointer. (s390_register_info): Mark r12 as clobbered if it'll be used as temp in s390_emit_prologue. (s390_emit_prologue): Use r12 as temp if r1 is taken by split-stack vararg pointer. (morestack_ref): New global. (SPLIT_STACK_AVAILABLE): New macro. (s390_expand_split_stack_prologue): New function. (s390_live_on_entry): New function. (s390_va_start): Use split-stack vararg pointer if appropriate. (s390_asm_file_end): Emit the split-stack note sections. (TARGET_EXTRA_LIVE_ON_ENTRY): New macro. * config/s390/s390.md (UNSPEC_STACK_CHECK): New unspec. (UNSPECV_SPLIT_STACK_CALL): New unspec. (UNSPECV_SPLIT_STACK_DATA): New unspec. (split_stack_prologue): New expand. (split_stack_space_check): New expand. (split_stack_data): New insn. (split_stack_call): New expand. (split_stack_call_*): New insn. (split_stack_cond_call): New expand. (split_stack_cond_call_*): New insn. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233421 138bc75d-0d04-0410-961f-82ee72b054a4
2016-02-10 PR go/68562ian
* config/i386/morestack.S (__stack_split_initialize): Align stack. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233273 138bc75d-0d04-0410-961f-82ee72b054a4
2016-02-032016-02-03 Andreas Tobler <andreast@gcc.gnu.org>andreast
PR bootstrap/69611 * config/rs6000/sfp-machine.h: Guard __sfp_exceptions with __FLOAT128__ to compile only for __float128 capable targets. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233111 138bc75d-0d04-0410-961f-82ee72b054a4
2016-01-25 PR target/69444jakub
* config/rs6000/sfp-machine.h: Fix a typo in #ifndef - __NO_FPRS__ instead of ___NO_FPRS__. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232805 138bc75d-0d04-0410-961f-82ee72b054a4
2016-01-21Add missing filemeissner
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232695 138bc75d-0d04-0410-961f-82ee72b054a4
2016-01-212016-01-21 Michael Meissner <meissner@linux.vnet.ibm.com>meissner
Steven Munroe <munroesj@linux.vnet.ibm.com> Tulio Magno Quites Machado Filho <tulioqm@br.ibm.com> * config/rs6000/float128-sed: New files to convert TF names to KF names for PowerPC IEEE 128-bit floating point support. * config/rs6000/float128-sed-hw: Likewise. * config/rs6000/float128-hw.c: New file for ISA 3.0 IEEE 128-bit floating point hardware support. * config/rs6000/float128-ifunc.c: New file to pick either IEEE 128-bit floating point software emulation or use ISA 3.0 hardware support if it is available. * config/rs6000/quad-float128.h: New file to support IEEE 128-bit floating point. * config/rs6000/extendkftf2-sw.c: New file, convert IEEE 128-bit floating point to IBM extended double. * config/rs6000/trunctfkf2-sw.c: New file, convert IBM extended double to IEEE 128-bit floating point. * config/rs6000/t-float128: New Makefile fragments to enable building __float128 emulation support. * config/rs6000/t-float128-hw: Likewise. * config/rs6000/sfp-exceptions.c: New file to provide exception support for IEEE 128-bit floating point. * config/rs6000/floattikf.c: New files for converting between IEEE 128-bit floating point and signed/unsigned 128-bit integers. * config/rs6000/fixunskfti.c: Likewise. * config/rs6000/fixkfti.c: Likewise. * config/rs6000/floatuntikf.c: Likewise. * config/rs6000/sfp-machine.h (_FP_W_TYPE_SIZE): Use 64-bit types when building on 64-bit systems, or when VSX is enabled. (_FP_W_TYPE): Likewise. (_FP_WS_TYPE): Likewise. (_FP_I_TYPE): Likewise. (TItype): Define on 64-bit systems. (UTItype): Likewise. (TI_BITS): Likewise. (_FP_MUL_MEAT_D): Add support for using 64-bit types. (_FP_MUL_MEAT_Q): Likewise. (_FP_DIV_MEAT_D): Likewise. (_FP_DIV_MEAT_Q): Likewise. (_FP_NANFRAC_D): Likewise. (_FP_NANFRAC_Q): Likewise. (ISA_BIT): Add exception support if we are being compiled on a machine with hardware floating point support to build the IEEE 128-bit emulation functions. (FP_EX_INVALID): Likewise. (FP_EX_OVERFLOW): Likewise. (FP_EX_UNDERFLOW): Likewise. (FP_EX_DIVZERO): Likewise. (FP_EX_INEXACT): Likewise. (FP_EX_ALL): Likewise. (__sfp_handle_exceptions): Likewise. (FP_HANDLE_EXCEPTIONS): Likewise. (FP_RND_NEAREST): Likewise. (FP_RND_ZERO): Likewise. (FP_RND_PINF): Likewise. (FP_RND_MINF): Likewise. (FP_RND_MASK): Likewise. (_FP_DECL_EX): Likewise. (FP_INIT_ROUNDMODE): Likewise. (FP_ROUNDMODE): Likewise. * libgcc/config.host (powerpc*-*-linux*): If compiler can compile VSX code, enable IEEE 128-bit floating point. If the compiler can compile IEEE 128-bit floating point code with ISA 3.0 IEEE 128-bit floating point hardware instructions and it supports declaring functions with the ifunc attribute, enable ifunc functions to switch between software and hardware support. * configure.ac (powerpc*-*-linux*): Likewise. * configure: Regenerate. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232685 138bc75d-0d04-0410-961f-82ee72b054a4
2016-01-15 * config/msp430/t-msp430 (lib2_mul_none.o): Only use the firstnickc
dependency as the source file to be compiled. (lib2_mul_16bit.o, lib2hw_mul_16.o, lib2hw_mul_32.o) (lib2hw_mul_f5.o): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232402 138bc75d-0d04-0410-961f-82ee72b054a4
2016-01-14Revert 2016-01-13 change.meissner
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232392 138bc75d-0d04-0410-961f-82ee72b054a4
2016-01-13[gcc]meissner
2016-01-13 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000-builtin.def (BU_FLOAT128_2): Add support for pack/unpack functions for __ibm128. (PACK_IF): Likewise. (UNPACK_IF): Likewise. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add support for __ibm128 pack/unpack functions. (rs6000_invalid_builtin): Likewise. (rs6000_init_builtins): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.h (MASK_FLOAT128): Add short name. (RS6000_BTM_FLOAT128): Add support for __ibm128 pack/unpack functions (RS6000_BTM_COMMON): Likewise. * config/rs6000/rs6000.md (f128_vsx): New mode attribute. (unpack<mode>): Use FMOVE128_FPR iterator instead of FMOVE128, to disallow __builtin_{pack,unpack}_longdouble if long double is IEEE 128-bit floating point. Add support for the double values to be in Altivec registers for TF/IF packing and unpacking, but restrict TD packing sub-fields to be FPR registers. Don't allow overlapped register support for packing. Allow pack inputs to be memory locations. Don't build generator functions for unpack<mode>_dm and unpack<mode>_nodm. (unpack<mode>_dm): Likewise. (unpack<mode>_nodm): Likewise. (pack<mode>): Likewise. * config/rs6000/rs6000-builtin.def (__builtin_pack_ibm128): Add built-in functions to pack/unpack explicit __ibm128 values. (__builtin_unpack_ibm128): Likewise. * doc/extend.texi (PowerPC Built-in Functions): Document __builtin_pack_ibm128 and __builtin_unpack_ibm128. [libgcc] 2016-01-13 Michael Meissner <meissner@linux.vnet.ibm.com> Steven Munroe <munroesj@linux.vnet.ibm.com> Tulio Magno Quites Machado Filho <tulioqm@br.ibm.com> * config/rs6000/sfp-exceptions.c: New file to provide exception support for IEEE 128-bit floating point. * config/rs6000/float128-hw.c: New file for ISA 3.0 IEEE 128-bit floating point hardware support. * config/rs6000/floattikf.c: New files for IEEE 128-bit floating point conversions. * config/rs6000/fixunskfti.c: Likewise. * config/rs6000/fixkfti.c: Likewise. * config/rs6000/floatuntikf.c: Likewise. * config/rs6000/extendkftf2-sw.c: Likewise. * config/rs6000/trunctfkf2-sw.c: Likewise. * config/rs6000/float128-ifunc.c: New file to pick either IEEE 128-bit floating point software emulation or use ISA 3.0 hardware support if it is available. * config/rs6000/quad-float128.h: New file to support IEEE 128-bit floating point. * config/rs6000/t-float128: New Makefile fragments to enable building __float128 emulation support. * config/rs6000/t-float128-hw: Likewise. * config/rs6000/float128-sed: New file to convert TF names to KF names for PowerPC IEEE 128-bit floating point support. * config/rs6000/sfp-machine.h (_FP_W_TYPE_SIZE): Use 64-bit types when building on 64-bit systems, or when VSX is enabled. (_FP_W_TYPE): Likewise. (_FP_WS_TYPE): Likewise. (_FP_I_TYPE): Likewise. (TItype): Define on 64-bit systems. (UTItype): Likewise. (TI_BITS): Likewise. (_FP_MUL_MEAT_D): Add support for using 64-bit types. (_FP_MUL_MEAT_Q): Likewise. (_FP_DIV_MEAT_D): Likewise. (_FP_DIV_MEAT_Q): Likewise. (_FP_NANFRAC_D): Likewise. (_FP_NANFRAC_Q): Likewise. (ISA_BIT): Add exception support if we are being compiled on a machine with hardware floating point support to build the IEEE 128-bit emulation functions. (FP_EX_INVALID): Likewise. (FP_EX_OVERFLOW): Likewise. (FP_EX_UNDERFLOW): Likewise. (FP_EX_DIVZERO): Likewise. (FP_EX_INEXACT): Likewise. (FP_EX_ALL): Likewise. (__sfp_handle_exceptions): Likewise. (FP_HANDLE_EXCEPTIONS): Likewise. (FP_RND_NEAREST): Likewise. (FP_RND_ZERO): Likewise. (FP_RND_PINF): Likewise. (FP_RND_MINF): Likewise. (FP_RND_MASK): Likewise. (_FP_DECL_EX): Likewise. (FP_INIT_ROUNDMODE): Likewise. (FP_ROUNDMODE): Likewise. * configure.ac (powerpc*-*-linux*): Check whether the PowerPC compiler can do __float128. * configure: Regenerate. * libgcc/config.host (powerpc*-*-linux*): If compiler can compile VSX code, enable IEEE 128-bit floating point. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232346 138bc75d-0d04-0410-961f-82ee72b054a4
2016-01-052016-01-05 Olivier Hainque <hainque@adacore.com>hainque
* config/rs6000/aix-unwind.h (ucontext_for): Handle AIX 7.1 specificities. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232082 138bc75d-0d04-0410-961f-82ee72b054a4
2016-01-04 Update copyright years.jakub
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232055 138bc75d-0d04-0410-961f-82ee72b054a4
2015-12-10 * config/pa/fptr.c (__canonicalize_funcptr_for_compare): Remove codedanglin
to initialize call to __dl_fixup once. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231486 138bc75d-0d04-0410-961f-82ee72b054a4
2015-12-04gcc * config.gcc (extra_gcc_objs): Define for MSP430.nickc
* common/config/msp430/msp430-common.c (msp430_handle_option): Pass both -mmcu and -mcpu on to the back end if they are both defined. * config/msp430/msp430.c (hwmult_name): New function. (msp430_option_override): If an unrecognised MCU name is detected only warn if the user has not provided suitable -mhwmult and -mcpu options. Use msp430_warn_mcu to control warning messages. Generate warnings about conflicts between -mmcu and -mcpu and -mhwmult options. If neither -mcpu nor -mmcu have been specified but -mhwmult= f5series has the select the 430X isa. (msp430_no_hwmult): If -mmcu has not been specified and msp430_hwmult_type is AUTO then return true. * config/msp430/msp430.h (EXTRA_SPEC_FUNCTIONS): Define. (LIB_SPEC): Add hardware multiply library selection. * config/msp430/t-msp430: Delete hardware multiply multilibs. Add rule to build driver-msp430.o * config/msp430/driver-msp430.c: New file. * config/msp430/msp430.opt (warn-mcu): New option. * doc/invoke.texi: Update description of -mhwmult=auto. Document -mwarn-mcu option. tests * gcc.target/msp430/msp_abi_div_funcs.c: New test. * gcc.target/msp430/mul_main.h: New test support file. * gcc.target/msp430/mul_none.c: New test. * gcc.target/msp430/mul_16bit.c: New test. * gcc.target/msp430/mul_32bit.c: New test. * gcc.target/msp430/mul_f5.c: New test. libgcc * config/msp430/mpy.c (__mulhi3): Use a faster algorithm. Allow for the second argument being negative. * config.host (extra_parts): Define for MSP430. Create separate libraries for each of the hardware multiply formats. * config/msp430/lib2hw_mul.S: Build only the multiply routines that are needed. * config/msp430/lib2mul.c: Likewise. * config/msp430/t-msp430 (LIB2ADD): Remove lib2hw_mul.S. Add rules to build hardware multiply libraries. * config/msp430/lib2divSI.c: (__mspabi_divlu): Alias for __mspabi_divul function. (__mspabi_divllu): New stub function. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231286 138bc75d-0d04-0410-961f-82ee72b054a4
2015-12-01 * config/pa/fptr.c (__canonicalize_funcptr_for_compare): Initializedanglin
fixup values if saved GOT address doesn't match runtime address. (fixup_branch_offset): Reorder list. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231135 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-23[ARM] PR target/68059 libgcc should not use __write for printing fatal errornsz
libgcc/ PR target/68059 * config/arm/linux-atomic-64bit.c (__write): Rename to... (write): ...this and fix the return type. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230762 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-20* config/msp430/lib2hw_mul.S: Fix alignment.dj
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230633 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-18 gcc/nathan
* config/nvptx/nvptx.c (global_lock_var): New. (nvptx_global_lock_addr): New. (nvptx_lockless_update): Recomment and adjust for clarity. (nvptx_lockfull_update): New. (nvptx_reduction_update): New. (nvptx_goacc_reduction_fini): Call it. libgcc/ * config/nvptx/reduction.c: New. * config/nvptx/t-nvptx (LIB2ADD): Add it. libgomp/ * testsuite/libgomp.oacc-c-c++-common/reduction-cplx-flt.c: Add worker & gang cases. * testsuite/libgomp.oacc-c-c++-common/reduction-cplx-dbl.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230545 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-15 * config/rs6000/on_exit.c: New file.dje
* config/rs6000/t-aix-cxa (LIB2ADDEH): Build on_exit.c. * config/rs6000/libgcc-aix-cxa.ver (on_exit): Add symbol to exports. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230398 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-112015-11-11 Claudiu Zissulescu <claziss@synopsys.com>claziss
* config/arc/dp-hack.h: Add support for ARCHS. * config/arc/ieee-754/divdf3.S: Likewise. * config/arc/ieee-754/divsf3-stdmul.S: Likewise. * config/arc/ieee-754/muldf3.S: Likewise. * config/arc/ieee-754/mulsf3.S: Likewise * config/arc/lib1funcs.S: Likewise * config/arc/gmon/dcache_linesz.S: Don't read the build register for ARCv2 cores. * config/arc/gmon/profil.S (__profil, __profil_irq): Don't profile for ARCv2 cores. * config/arc/ieee-754/arc-ieee-754.h (MPYHU, MPYH): Define. * config/arc/t-arc700-uClibc: Remove hard selection for ARC 700 cores. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230151 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-09Support init priority on Solarisro
libgcc: * config/ia64/crtbegin.S: Check HAVE_INITFINI_ARRAY_SUPPORT value. * config/ia64/crtend.S: Likewise. gcc: * acinclude.m4 (gcc_AC_INITFINI_ARRAY): Allow for differences in assembler syntax. Support Solaris ld. Define HAVE_INITFINI_ARRAY_SUPPORT as 0/1. * config/sol2.h (SUPPORTS_INIT_PRIORITY): Define to HAVE_INITFINI_ARRAY_SUPPORT. * config/initfini-array.h: Check HAVE_INITFINI_ARRAY_SUPPORT value. * configure.ac (gcc_cv_as_sparc_nobits): Remove. * config/sparc/sparc.c (sparc_solaris_elf_asm_named_section): Don't check HAVE_AS_SPARC_NOBITS. Heed SECTION_NOTYPE. * configure: Regenerate. * config.in: Regenerate. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230013 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-07replace BITS_PER_UNIT with __CHAR_BIT__ in target libstbsaunde
libgcc/ChangeLog: 2015-11-07 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config/visium/lib2funcs.c (__set_trampoline_parity): Use __CHAR_BIT__ instead of BITS_PER_UNIT. * fixed-bit.h: Likewise. * fp-bit.h: Likewise. * libgcc2.c (__popcountSI2): Likewise. (__popcountDI2): Likewise. * libgcc2.h: Likewise. * libgcov.h: Likewise. libobjc/ChangeLog: 2015-11-07 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> PR libobjc/24775 * encoding.c (_darwin_rs6000_special_round_type_align): Use __CHAR_BIT__ instead of BITS_PER_UNIT. (objc_sizeof_type): Likewise. (objc_layout_structure): Likewise. (objc_layout_structure_next_member): Likewise. (objc_layout_finish_structure): Likewise. (objc_layout_structure_get_info): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229936 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-07* config/rs6000/atexit.c: New file.dje
* config/rs6000/t-aix-cxa (LIB2ADDEH): Build atexit.c. * config/rs6000/libgcc-aix-cxa.ver (atexit): Add symbol to exports. * config/rs6000/cxa_finalize.c (catomic_compare_and_exchange_bool_acq): Negate return value. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229932 138bc75d-0d04-0410-961f-82ee72b054a4
2015-10-30libgcc changes for AMD znver1.vekumar
2015-10-30 Venkataramanan Kumar <venkataramanan.kumar@amd.com> * config/i386/i386.c (get_builtin_code_for_version): Set priority for PROCESSOR_ZNVER1. (enum processor_model): Add M_AMDFAM17H_znver1. (struct arch_names_table): Likewise. * doc/extend.texi: ADD znver1. 2015-10-30 Venkataramanan Kumar <venkataramanan.kumar@amd.com> * config/i386/cpuinfo.c (enum processor_types): Add AMDFAM17H. (processor_subtypes): Add znver1. (get_amd_cpu): Detect znver1. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229575 138bc75d-0d04-0410-961f-82ee72b054a4
2015-10-23 PR libgcc/66883amylaar
* config/epiphany/udivsi3-float.c: Fix CONCISE test, and comment typo. N.B., this is not active code, just documenting a previous approach for this function in C. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229236 138bc75d-0d04-0410-961f-82ee72b054a4
2015-10-16* config/rl78/divmodqi.S: Return 0x00 by default for div by 0.dj
* config/rl78/divmodsi.S: Update return register to r8. * config/rl78/divmodhi.S: Update return register to r8,r9. Branch to main_loop_done_himode to pop registers before return. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228926 138bc75d-0d04-0410-961f-82ee72b054a4
2015-10-11Add bdver4 for multiversioning and fix AMD model detection.vekumar
2015-10-09 Venkataramanan kumar <venkataramanan.kumar@amd.com> * config/i386/cpuinfo.c (get_amd_cpu): Detect bdver4. (__cpu_indicator_init): Fix model selection for AMD CPUs. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228691 138bc75d-0d04-0410-961f-82ee72b054a4
2015-10-05libgcc/kyukhin
* config/i386/cpuinfo.c (get_intel_cpu): Detect "skylake-avx512". gcc/testsuite/ * gcc.target/i386/builtin_target.c: Add check for "skylake-avx512". git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228481 138bc75d-0d04-0410-961f-82ee72b054a4
2015-10-02AVX-512. Add missing features to cpuinfo.ckyukhin
gcc/ * config/i386/i386.c (processor_features): Add F_AVX512VBMI, F_AVX512IFMA. (isa_names_table): Handle F_AVX512VBMI and F_AVX512IFMA. libgcc/ * config/i386/cpuinfo.c (processor_features): Add FEATURE_AVX512VBMI and FEATURE_AVX512VBMI. testsuite/ * gcc.target/i386/builtin_target.c: Handle "avx512ifma" and "avx512vbmi". git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228399 138bc75d-0d04-0410-961f-82ee72b054a4
2015-09-24ARM: fp16 Fix PR 67624 - Incorrect conversion of float Infinity to __fp16rearnsha
PR libgcc/67624 libgcc: * config/arm/fp16.c (__gnu_f2h_internal): Handle infinity correctly. gcc/testsuite: * gcc.target/arm/fp16-inf.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228082 138bc75d-0d04-0410-961f-82ee72b054a4
2015-09-24Support PIE on Solarisro
gcc/testsuite: * lib/target-supports.exp (check_effective_target_pie): Check for PIE support on Solaris 11.x and 12. libgcc: * config.host (*-*-solaris2*): Add t-crtstuff-pic to tmake_file. Add crtbeginS.o, crtendS.o to extra_parts if libgcc_cv_solaris_crts. * config/sol2/gmon.c: (monstartup): Don't write trailing NUL of messages. (internal_mcount): Likewise. * config/sol2/t-sol2 (crtp.o, crtpg.o, gmon.o): Compile with crt_compile, add CRTSTUFF_T_CFLAGS_S. gcc: * configure.ac (gcc_cv_ld_pie): Check for gld >= 2.26 on Solaris. Check for ld -type pie on Solaris 11.x and 12. * configure: Regenerate. * config.in: Regenerate. * gcc.c (LD_PIE_SPEC): Allow redefinition. * config/sol2.h (STARTFILE_CRTBEGIN_SPEC): Define. (STARTFILE_SPEC): Use it. (ENDFILE_CRTEND_SPEC): Define. (ENDFILE_SPEC): Use it and ENDFILE_ARCH_SPEC. (SUBTARGET_EXTRA_SPECS): Add STARTFILE_CRTBEGIN_SPEC, ENDFILE_ARCH_SPEC, ENDFILE_CRTEND_SPEC. [HAVE_LD_PIE && HAVE_SOLARIS_CRTS] (LD_PIE_SPEC): Define. (!(HAVE_LD_PIE && HAVE_SOLARIS_CRTS)] (LINK_PIE_SPEC): Define. * config/i386/sol2.h (ENDFILE_SPEC): Remove. (ENDFILE_ARCH_SPEC): Define. * config/sparc/sol2.h (ENDFILE_ARCH_SPEC): Define. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228078 138bc75d-0d04-0410-961f-82ee72b054a4
2015-09-24Use CRTs provided by Solarisro
gcc: * configure.ac (gcc_cv_solaris_crts): New test. * configure. Regenerate. * config.in: Regenerate. * config/sol2.h (STARTFILE_SPEC): Simplify, provide HAVE_SOLARIS_CRTS variant. libgcc: * configure.ac (libgcc_cv_solaris_crts): New test. * configure: Regenerate. * config.in: Regenerate. * config/sol2/crtp.c, config/sol2/crtpg.c: New files. * config/gmon-sol2.c: Rename to ... * config/sol2/gmon.c: ... this. Include auto-target.h. (internal_mcount): Wrap setup handling in !HAVE_SOLARIS_CRTS. * config/t-sol2: Rename to ... * config/sol2/t-sol2: ... this. (gmon.o): Reflect renaming. (crtp.o, crtpg.o): New rules. * config.host (*-*-solaris2*): Reflect renaming. Use system CRTs if present. Remove default CRT case. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228077 138bc75d-0d04-0410-961f-82ee72b054a4
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