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AgeCommit message (Expand)Author
2020-07-21i386: Rename TARGET_USE_XCHG_FOR_ATOMIC_STORE to TARGET_AVOID_MFENCE.Uros Bizjak
2020-07-16S/390: Emit vector alignment hints for z13 if AS accepts themStefan Schulze Frielinghaus
2020-07-15c++: Treat GNU and Advanced SIMD vectors as distinct [PR95726]Richard Sandiford
2020-07-15fix _mm512_{,mask_}cmp*_p[ds]_mask at -O0 [PR96174]Jakub Jelinek
2020-07-13aarch64: Add missing ACLE support for PAC-RETSzabolcs Nagy
2020-07-13aarch64: fix __builtin_eh_return with pac-ret [PR94891]Szabolcs Nagy
2020-07-13aarch64: fix return address access with pac [PR94891][PR94791]Szabolcs Nagy
2020-07-13aarch64: Add missing ACLE support for BTISzabolcs Nagy
2020-07-10rs6000: Fix __builtin_altivec_mask_for_load to use correct typeBill Seurer
2020-07-10Aarch64: Change costs for TX2 to expose more vectorization opportunitiesAnton Youdkevitch
2020-07-10rs6000: Allow MMA built-in initialization regardless of compiler optionsPeter Bergner
2020-07-10[PATCH, rs6000]Add support to enable vmsumudm behind vec_msum builtin.Will Schmidt
2020-07-09RISC-V: Disable remove unneeded save-restore call optimization if there are a...Kito Cheng
2020-07-09RISC-V: Fix compilation failed for frflags builtin in C++ modeKito Cheng
2020-07-09RISC-V: Fix ICE on riscv_gpr_save_operation_p [PR95683]Kito Cheng
2020-07-09RISC-V: Suppress warning for signed and unsigned integer comparison.Kito Cheng
2020-07-09RISC-V: Unify the output asm pattern between gpr_save and gpr_restore pattern.Kito Cheng
2020-07-09RISC-V: Describe correct USEs for gpr_save pattern [PR95252]Kito Cheng
2020-07-09RISC-V: Make unique SECCAT_SRODATA names start with .srodata (not .sdata2)Keith Packard
2020-07-08aarch64: Fix arm_sve_vector_bits on typedefs [PR95105]Richard Sandiford
2020-07-06Backport to gcc-10Will Schmidt
2020-07-02rs6000: Define _ARCH_PWR10 when appropriateSegher Boessenkool
2020-07-02rs6000: Add support for __builtin_cpu_is ("power10")Peter Bergner
2020-07-02PowerPC: Add power10 hwcap2 bitsMichael Meissner
2020-06-30rs6000: Rename isa attribute "fut" to "p10"Segher Boessenkool
2020-06-30rs6000: Rename future to power10Segher Boessenkool
2020-06-30arm: Don't generate invalid LDRD insnsAlex Coplan
2020-06-25x96: Remove PTA_CLWB from PTA_ICELAKE_CLIENTH.J. Lu
2020-06-24rs6000: Add MMA built-in function definitions and test casesPeter Bergner
2020-06-24rs6000: Backport u8bit_cint_operand predicatePeter Bergner
2020-06-24rs6000: Add base support and types for defining MMA built-insPeter Bergner
2020-06-19Introduce flag_cunroll_grow_size for cunroll and avoid enable it at -O2guojiufu
2020-06-18identify lfs prefixed case PR95347Aaron Sawdey
2020-06-18Correctly identify stfs if prefixedAaron Sawdey
2020-06-18[PATCH][GCC] arm: Fix the MVE ACLE vaddq_m polymorphic variants.Srinath Parvathaneni
2020-06-18[PATCH][GCC] arm: Fix MVE scalar shift intrinsics code-gen.Srinath Parvathaneni
2020-06-16arm: Fix the MVE ACLE vbicq intrinsics.Srinath Parvathaneni
2020-06-16arm: Correct the grouping of operands in MVE vector scatter store intrinsics ...Srinath Parvathaneni
2020-06-16arm: Fix unintentional fall throughs in arm.cSrinath Parvathaneni
2020-06-16arm: Fix the wrong code-gen generated by MVE vector load/store intrinsics (PR...Srinath Parvathaneni
2020-06-15amdgcn: use unsigned extend for lshiftrtAndrew Stubbs
2020-06-05x86: Update Intel processor detectionH.J. Lu
2020-06-05Fix bitmask conflict between PTA_AVX512VP2INTERSECT and PTA_WAITPKG in gcc/co...Cui,Lili
2020-06-02aarch64: Add initial support for -mcpu=zeusKyrylo Tkachov
2020-05-29aarch64: PR target/94591: Don't generate invalid REV64 insnsAlex Coplan
2020-05-29amdgcn: fix vcc clobber in vector load/storeAndrew Stubbs
2020-05-28aarch64: Fix segfault in aarch64_expand_epilogue [PR95361]Richard Sandiford
2020-05-28i386: Fix V2SF horizontal addsub insnUros Bizjak
2020-05-28i386: Remove %q modifier from two pmov insn templates [PR95355]Uros Bizjak
2020-05-24i386: Fix <rounding_insn><mode>2 expander [PR95255]Uros Bizjak
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