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path: root/gcc/config/aarch64/aarch64.md
AgeCommit message (Expand)Author
2015-09-16Merge branches/gcc-5-branch rev 227732.linaro-local/gcc-5-integration-branch-newYvan Roux
2015-08-27 gcc/Yvan Roux
2015-08-27 gcc/Yvan Roux
2015-08-27 gcc/Yvan Roux
2015-08-27 gcc/Yvan Roux
2015-06-122015-06-03 Christophe Lyon <christophe.lyon@linaro.org>Christophe Lyon
2015-02-28[AArch64] Fix define_insn type in aarch64.md.jgreenhalgh
2015-02-25[AArch64] Fix illegal assembly 'eon v1, v2, v3'alalaw01
2015-02-20[AArch64] Fix wrong-code bug in right-shift SISD patternsktkachov
2015-01-27[AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobberjiwang
2015-01-26[AARCH64]Fix TLS local exec model addressing code generation inconsistency.renlin
2015-01-19[AArch64] Remove ashift pattern for QI/HIjiwang
2015-01-16[AArch64] Fix PR 64263: Do not try to split constants when destination is SIM...ktkachov
2015-01-16[AArch64] Add a new scheduling description for the ARM Cortex-A57 processorjgreenhalgh
2015-01-16[AArch64] Enable CCMP support for AArch64, PR64015 resolvedjiwang
2015-01-152015-01-15 Philipp Tomsich <ptomsich@theobroma-systems.com>ptomsich
2015-01-13gcc/rsandifo
2015-01-05 Update copyright years.jakub
2014-12-19[AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EONalalaw01
2014-12-19[AArch64 2/3] Add SIMD-reg variants of logical operators and/ior/xor/notalalaw01
2014-12-19[AArch64 1/3] Don't disparage add/sub in SIMD registersalalaw01
2014-12-18[AArch64] Simplify+improve patterns for ushr(d?)_n_u64 intrinsicalalaw01
2014-12-18[AArch64] Simplify patterns for sshr_n_[us]64 intrinsicalalaw01
2014-12-17[AArch64] Remove "generic_sched" attributejgreenhalgh
2014-12-09gcc/testsuite/:alalaw01
2014-12-08Bics instruction generation for aarch64avelenko
2014-12-08 * config/aarch64/arm_neon.h (vrecpe_u32, vrecpeq_u32): Rewrite usingfyang
2014-12-05[AArch64]load store pair optimization using sched_fusion pass.mshawcroft
2014-12-04Add prefetch support for aarch64gganesh
2014-11-18 * config/aarch64/aarch64.c (doloop_end): New pattern.fyang
2014-11-172014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>zqchen
2014-11-14[AARCH64] Add scheduler for ThunderXpinskia
2014-11-14Fix typo in *<arith_shift_insn>_shiftsiramana
2014-10-29gcc/ada/rsandifo
2014-10-24[PATCH 1/2] [AARCH64,NEON] Add patterns + builtins for vld[234](q?)_lane_* in...cbaylis
2014-10-24 PR target/63173fyang
2014-09-23[AArch64] Enable shrink wrapping.mshawcroft
2014-09-19[PATCH AArch64]: Add constraint letter for stack_protect_test patternjgreenhalgh
2014-09-07Fix PR63190vekumar
2014-09-05[PATCH][AArch64] One-liner: fix type of an add in SIMD registersalalaw01
2014-09-05[AArch64 Obvious] Add a mode to operand 1 of sibcall_value_insnjgreenhalgh
2014-09-02[AArch64] Use CC_Z and CC_NZ with csinc and similar instructions.ktkachov
2014-08-27 PR target/62262carrot
2014-08-07[AArch64] Restrict usage of FP/SIMD registers for TImode reload and absdi2 pa...ktkachov
2014-08-01[AArch64][2/2] Add constrain to address offset in storewb_pair/loadwb_pair insnsjiwang
2014-08-01[AArch64][1/2] Fix offset glitch in load reg pair patternjiwang
2014-07-272014-07-26 Andrew Pinski <apinski@cavium.com>pinskia
2014-07-23[AArch64] Simplify epilogue expansion using new helper functions.mshawcroft
2014-07-23[AArch64] Simplify prologue expand using new helper functions.mshawcroft
2014-07-22[AArch64][1/2] Remove UNSPEC_CLS and use clrsb RTL code in its' place.ktkachov
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