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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@225553 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@225551 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@225347 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@223363 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@223362 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@223359 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@223153 138bc75d-0d04-0410-961f-82ee72b054a4
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Backport from trunk r203711.
2013-10-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md
(*mov<mode>_aarch64): Fix output template for DUP (element) Scalar.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@222002 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@220730 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@220724 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@220643 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@217568 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@217565 138bc75d-0d04-0410-961f-82ee72b054a4
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2014-11-14 Michael Collison <michael.collison@linaro.org>
Backport from trunk r212178..
2014-06-30 Joseph Myers <joseph@codesourcery.com>
* var-tracking.c (add_stores): Return instead of asserting if old
and new values for conditional store are the same.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@217555 138bc75d-0d04-0410-961f-82ee72b054a4
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Add Linaro release macros (Linaro only patch.)
* Makefile.in (LINAROVER, LINAROVER_C, LINAROVER_S): Define.
(CFLAGS-cppbuiltin.o): Add LINAROVER macro definition.
(cppbuiltin.o): Depend on $(LINAROVER).
* cppbuiltin.c (parse_linarover): New.
(define_GNUC__): Define __LINARO_RELEASE__ and __LINARO_SPIN__ macros.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@217548 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@217506 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@217046 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@214617 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@214037 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@214033 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@213944 138bc75d-0d04-0410-961f-82ee72b054a4
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2014-08-11 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206529, r206530
2014-01-10 Richard Earnshaw <rearnsha@arm.com>
PR target/59744
* aarch64-modes.def (CC_Zmode): New flags mode.
* aarch64.c (aarch64_select_cc_mode): Only allow NEG when the condition
represents an equality.
(aarch64_get_condition_code): Handle CC_Zmode.
* aarch64.md (compare_neg<mode>): Restrict to equality operations.
gcc/testsuite/
2014-08-11 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206529
2014-01-10 Richard Earnshaw <rearnsha@arm.com>
PR target/59744
* gcc.target/aarch64/cmn-neg.c: Use equality comparisons.
* gcc.target/aarch64/cmn-neg2.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@213842 138bc75d-0d04-0410-961f-82ee72b054a4
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Backport from trunk r204251
2013-10-31 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Yury Gribov <y.gribov@samsung.com>
PR sanitizer/58543
* asan.c (asan_clear_shadow): Allocate a new vreg for temporary
shadow pointer to avoid clobbering the main one.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@213841 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@211850 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@209273 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@209271 138bc75d-0d04-0410-961f-82ee72b054a4
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2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r205105
2013-11-20 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md: Remove "mode" and "mode2" attributes
from all insns.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r205050
2013-11-19 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/arm.md (zero_extend<mode>di2): Add type attribute.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r204852
2013-11-19 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md: Remove v8type from all insns.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r204852
2013-11-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd.md: Remove simd_type from all
patterns.
* config/aarch64/aarch64.md: Likewise, correct "type" attribute
where it is incorrect or missing.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r204784
2013-11-14 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-cores.def (example-1): Remove.
(example-2): Likewise.
* config/aarch64/aarch64-tune.md: Regenerate.
* config/aarch64/aarch64.md: Do not include "large.md" or "small.md".
(generic_sched): Remove "large", "small".
* config/aarch64/large.md: Delete.
* config/aarch64/small.md: Delete.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r204783
2013-11-14 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-cores.def (cortex-a57): Tune for cortexa15.
* config/aarch64/aarch64-tune.md: Regenerate.
* config/aarch64/aarch64.md: Include cortex-a15 pipeline model.
(generic_sched): "no" if we are tuning for cortexa15.
* config/arm/cortex-a15.md: Include cortex-a15-neon.md by
relative path.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r204782
2013-11-14 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-arches.def (armv8-a): Tune for cortex-a53.
* config/aarch64/aarch64.md: Do not include aarch64-generic.md.
* config/aarch64/aarch64.c (aarch64_tune): Initialize to cortexa53.
(all_cores): Use cortexa53 when tuning for "generic".
(aarch64_override_options): Fix comment.
* config/aarch64/aarch64.h (TARGET_CPU_DEFAULT): Set to cortexa53.
* config/aarch64/aarch64-generic.md: Delete.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r204575
2013-11-08 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/aarch-common.c
(search_term): New typedef.
(shift_rtx_costs): New array.
(arm_rtx_shift_left_p): New.
(arm_find_sub_rtx_with_search_term): Likewise.
(arm_find_sub_rtx_with_code): Likewise.
(arm_early_load_addr_dep): Add sanity checking.
(arm_no_early_alu_shift_dep): Likewise.
(arm_no_early_alu_shift_value_dep): Likewise.
(arm_no_early_mul_dep): Likewise.
(arm_no_early_store_addr_dep): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203621
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/neon-schedgen.ml: Remove.
* config/arm/cortex-a9-neon.md: Remove comment regarding
neon-schedgen.ml.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203620
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types: Remove old neon types.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203619
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/cortex-a7.md
(cortex_a7_neon_type): New.
(cortex_a7_neon_mul): Update for new types.
(cortex_a7_neon_mla): Likewise.
(cortex_a7_neon): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203618
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/cortex-a15-neon.md
(cortex_a15_neon_type): New,
(cortex_a15_neon_int_1): Remove.
(cortex_a15_neon_int_2): Likewise.
(cortex_a15_neon_int_3): Likewise.
(cortex_a15_neon_int_4): Likewise.
(cortex_a15_neon_int_5): Likewise.
(cortex_a15_neon_vqneg_vqabs): Likewise.
(cortex_a15_neon_vmov): Likewise.
(cortex_a15_neon_vaba): Likewise.
(cortex_a15_neon_vaba_qqq): Likewise.
(cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a15_neon_mul_qqq_8_16_32_ddd_32): Likewise.
(cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
Likewise.
(cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a15_neon_mla_qqq_8_16): Likewise.
(cortex_a15_neon_mla_ddd_32_qqd_16_ddd_32_scalar): Likewise.
(cortex_a15_neon_mla_qqq_32_qqd_32_scalar): Likewise.
(cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
(cortex_a15_neon_mul_qqd_32_scalar): Likewise.
(cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
(cortex_a15_neon_shift_1): Likewise.
(cortex_a15_neon_shift_2): Likewise.
(cortex_a15_neon_shift_3): Likewise.
(cortex_a15_neon_vshl_ddd): Likewise.
(cortex_a15_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
(cortex_a15_neon_vsra_vrsra): Likewise.
(cortex_a15_neon_fp_vmla_ddd_scalar): Likewise.
(cortex_a15_neon_fp_vmla_qqq_scalar): Likewise.
(cortex_a15_neon_bp_3cycle): Likewise.
(cortex_a15_neon_ldm_2): Likewise.
(cortex_a15_neon_stm_2): Likewise.
(cortex_a15_neon_mcr): Likewise.
(cortex_a15_neon_mrc): Likewise.
(cortex_a15_neon_fp_vadd_ddd_vabs_dd): Likewise.
(cortex_a15_neon_fp_vadd_qqq_vabs_qq): Likewise.
(cortex_a15_neon_fp_vmul_ddd): Likewise.
(cortex_a15_neon_fp_vmul_qqd): Likewise.
(cortex_a15_neon_fp_vmla_ddd): Likewise.
(cortex_a15_neon_fp_vmla_qqq): Likewise.
(cortex_a15_neon_fp_vmla_ddd_scalar): Likewise.
(cortex_a15_neon_fp_vmla_qqq_scalar): Likewise.
(cortex_a15_neon_fp_vrecps_vrsqrts_ddd): Likewise.
(cortex_a15_neon_fp_vrecps_vrsqrts_qqq): Likewise.
(cortex_a15_neon_bp_simple): Likewise.
(cortex_a15_neon_bp_2cycle): Likewise.
(cortex_a15_neon_bp_3cycle): Likewise.
(cortex_a15_neon_vld1_1_2_regs): Likewise.
(cortex_a15_neon_vld1_3_4_regs): Likewise.
(cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
(cortex_a15_neon_vld2_4_regs): Likewise.
(cortex_a15_neon_vld3_vld4): Likewise.
(cortex_a15_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
(cortex_a15_neon_vst1_3_4_regs): Likewise.
(cortex_a15_neon_vst2_4_regs_vst3_vst4): Rename to...
(cortex_a15_neon_vst2_4_regs_vst3): ...This, update for new attributes.
(cortex_a15_neon_vst3_vst4): Rename to...
(cortex_a15_neon_vst4): This, update for new attributes.
(cortex_a15_neon_vld1_vld2_lane): Update for new attributes.
(cortex_a15_neon_vld3_vld4_lane): Likewise.
(cortex_a15_neon_vst1_vst2_lane): Likewise.
(cortex_a15_neon_vst3_vst4_lane): Likewise.
(cortex_a15_neon_vld3_vld4_all_lanes): Likewise.
(cortex_a15_neon_ldm_2): Likewise.
(cortex_a15_neon_stm_2): Likewise.
(cortex_a15_neon_mcr): Likewise.
(cortex_a15_neon_mcr_2_mcrr): Likewise.
(cortex_a15_neon_mrc): Likewise.
(cortex_a15_neon_mrrc): Likewise.
(cortex_a15_neon_abd): New.
(cortex_a15_neon_abd_q): Likewise.
(cortex_a15_neon_aba): Likewise.
(cortex_a15_neon_aba_q): Likewise.
(cortex_a15_neon_acc): Likewise.
(cortex_a15_neon_acc_q): Likewise.
(cortex_a15_neon_arith_basic): Likewise.
(cortex_a15_neon_arith_complex): Likewise.
(cortex_a15_neon_multiply): Likewise.
(cortex_a15_neon_multiply_q): Likewise.
(cortex_a15_neon_mla): Likewise.
(cortex_a15_neon_mla_q): Likewise.
(cortex_a15_neon_sat_mla_long): Likewise.
(cortex_a15_neon_shift_acc): Likewise.
(cortex_a15_neon_shift_imm_basic): Likewise.
(cortex_a15_neon_shift_imm_complex): Likewise.
(cortex_a15_neon_shift_reg_basic): Likewise.
(cortex_a15_neon_shift_reg_basic_q): Likewise.
(cortex_a15_neon_shift_reg_complex): Likewise.
(cortex_a15_neon_shift_reg_complex_q): Likewise.
(cortex_a15_neon_fp_negabs): Likewise
(cortex_a15_neon_fp_arith): Likewise
(cortex_a15_neon_fp_arith_q): Likewise
(cortex_a15_neon_fp_cvt_int): Likewise
(cortex_a15_neon_fp_cvt_int_q): Likewise
(cortex_a15_neon_fp_cvt_16): Likewise
(cortex_a15_neon_fp_mul): Likewise
(cortex_a15_neon_fp_mul_q): Likewise
(cortex_a15_neon_fp_mla): Likewise
(cortex_a15_neon_fp_mla_q): Likewise
(cortex_a15_neon_fp_recps_rsqrte): Likewise.
(cortex_a15_neon_fp_recps_rsqrte_q): Likewise.
(cortex_a15_neon_bitops): Likewise.
(cortex_a15_neon_bitops_q): Likewise.
(cortex_a15_neon_from_gp): Likewise.
(cortex_a15_neon_from_gp_q): Likewise.
(cortex_a15_neon_tbl3_tbl4): Likewise.
(cortex_a15_neon_zip_q): Likewise.
(cortex_a15_neon_to_gp): Likewise.
(cortex_a15_neon_load_a): Likewise.
(cortex_a15_neon_load_b): Likewise.
(cortex_a15_neon_load_c): Likewise.
(cortex_a15_neon_load_d): Likewise.
(cortex_a15_neon_load_e): Likewise.
(cortex_a15_neon_load_f): Likewise.
(cortex_a15_neon_store_a): Likewise.
(cortex_a15_neon_store_b): Likewise.
(cortex_a15_neon_store_c): Likewise.
(cortex_a15_neon_store_d): Likewise.
(cortex_a15_neon_store_e): Likewise.
(cortex_a15_neon_store_f): Likewise.
(cortex_a15_neon_store_g): Likewise.
(cortex_a15_neon_store_h): Likewise.
(cortex_a15_vfp_to_from_gp): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203617
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/cortex-a9-neon.md (cortex_a9_neon_type): New.
(cortex_a9_neon_vshl_ddd): Remove.
(cortex_a9_neon_vst3_vst4): Likewise.
(cortex_a9_neon_vld3_vld4_all_lanes): Likewise.
(cortex_a9_neon_bit_ops_q): New.
(cortex_a9_neon_int_1): Use cortex_a8_neon_type.
(cortex_a9_neon_int_2): Likewise.
(cortex_a9_neon_int_3): Likewise.
(cortex_a9_neon_int_4): Likewise.
(cortex_a9_neon_int_5): Likewise.
(cortex_a9_neon_vqneg_vqabs): Likewise.
(cortex_a9_neon_vmov): Likewise.
(cortex_a9_neon_vaba): Likewise.
(cortex_a9_neon_vaba_qqq): Likewise.
(cortex_a9_neon_shift_1): Likewise.
(cortex_a9_neon_shift_2): Likewise.
(cortex_a9_neon_shift_3): Likewise.
(cortex_a9_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
(cortex_a9_neon_vsra_vrsra): Likewise.
(cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a9_neon_mul_qqq_8_16_32_ddd_32): Likewise.
(cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
Likewise.
(cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a9_neon_mla_qqq_8_16): Likewise.
(cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long):
Likewise.
(cortex_a9_neon_mla_qqq_32_qqd_32_scalar): Likewise.
(cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
(cortex_a9_neon_mul_qqd_32_scalar): Likewise.
(cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
(cortex_a9_neon_fp_vadd_ddd_vabs_dd): Likewise.
(cortex_a9_neon_fp_vadd_qqq_vabs_qq): Likewise.
(cortex_a9_neon_fp_vsum): Likewise.
(cortex_a9_neon_fp_vmul_ddd): Likewise.
(cortex_a9_neon_fp_vmul_qqd): Likewise.
(cortex_a9_neon_fp_vmla_ddd): Likewise.
(cortex_a9_neon_fp_vmla_qqq): Likewise.
(cortex_a9_neon_fp_vmla_ddd_scalar): Likewise.
(cortex_a9_neon_fp_vmla_qqq_scalar): Likewise.
(cortex_a9_neon_fp_vrecps_vrsqrts_ddd): Likewise.
(cortex_a9_neon_fp_vrecps_vrsqrts_qqq): Likewise.
(cortex_a9_neon_bp_simple): Likewise.
(cortex_a9_neon_bp_2cycle): Likewise.
(cortex_a9_neon_bp_3cycle): Likewise.
(cortex_a9_neon_ldr): Likewise.
(cortex_a9_neon_str): Likewise.
(cortex_a9_neon_vld1_1_2_regs): Likewise.
(cortex_a9_neon_vld1_3_4_regs): Likewise.
(cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
(cortex_a9_neon_vld2_4_regs): Likewise.
(cortex_a9_neon_vld3_vld4): Likewise.
(cortex_a9_neon_vld1_vld2_lane): Likewise.
(cortex_a9_neon_vld3_vld4_lane): Likewise.
(cortex_a9_neon_vld3_vld4_all_lanes): Likewise.
(cortex_a9_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
(cortex_a9_neon_vst1_3_4_regs): Likewise.
(cortex_a9_neon_vst2_4_regs_vst3_vst4): Likewise.
(cortex_a9_neon_vst1_vst2_lane): Likewise.
(cortex_a9_neon_vst3_vst4_lane): Likewise.
(cortex_a9_neon_mcr): Likewise.
(cortex_a9_neon_mcr_2_mcrr): Likewise.
(cortex_a9_neon_mrc): Likewise.
(cortex_a9_neon_mrrc): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203616
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/cortex-a8-neon.md (cortex_a8_neon_type): New.
(cortex_a8_neon_vshl_ddd): Remove.
(cortex_a8_neon_vst3_vst4): Likewise.
(cortex_a8_neon_vld3_vld4_all_lanes): Likewise.
(cortex_a8_neon_bit_ops_q): New.
(cortex_a8_neon_int_1): Use cortex_a8_neon_type.
(cortex_a8_neon_int_2): Likewise..
(cortex_a8_neon_int_3): Likewise.
(cortex_a8_neon_int_5): Likewise.
(cortex_a8_neon_vqneg_vqabs): Likewise.
(cortex_a8_neon_int_4): Likewise.
(cortex_a8_neon_vaba): Likewise.
(cortex_a8_neon_vaba_qqq): Likewise.
(cortex_a8_neon_shift_1): Likewise.
(cortex_a8_neon_shift_2): Likewise.
(cortex_a8_neon_shift_3): Likewise.
(cortex_a8_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
(cortex_a8_neon_vsra_vrsra): Likewise.
(cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a8_neon_mul_qqq_8_16_32_ddd_32): Likewise.
(cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
Likewise.
(cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a8_neon_mla_qqq_8_16): Likewise.
(cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long):
Likewise.
(cortex_a8_neon_mla_qqq_32_qqd_32_scalar): Likewise.
(cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
(cortex_a8_neon_mul_qqd_32_scalar): Likewise.
(cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
(cortex_a8_neon_fp_vadd_ddd_vabs_dd): Likewise.
(cortex_a8_neon_fp_vadd_qqq_vabs_qq): Likewise.
(cortex_a8_neon_fp_vsum): Likewise.
(cortex_a8_neon_fp_vmul_ddd): Likewise.
(cortex_a8_neon_fp_vmul_qqd): Likewise.
(cortex_a8_neon_fp_vmla_ddd): Likewise.
(cortex_a8_neon_fp_vmla_qqq): Likewise.
(cortex_a8_neon_fp_vmla_ddd_scalar): Likewise.
(cortex_a8_neon_fp_vmla_qqq_scalar): Likewise.
(cortex_a8_neon_fp_vrecps_vrsqrts_ddd): Likewise.
(cortex_a8_neon_fp_vrecps_vrsqrts_qqq): Likewise.
(cortex_a8_neon_bp_simple): Likewise.
(cortex_a8_neon_bp_2cycle): Likewise.
(cortex_a8_neon_bp_3cycle): Likewise.
(cortex_a8_neon_ldr): Likewise.
(cortex_a8_neon_str): Likewise.
(cortex_a8_neon_vld1_1_2_regs): Likewise.
(cortex_a8_neon_vld1_3_4_regs): Likewise.
(cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
(cortex_a8_neon_vld2_4_regs): Likewise.
(cortex_a8_neon_vld3_vld4): Likewise.
(cortex_a8_neon_vld1_vld2_lane): Likewise.
(cortex_a8_neon_vld3_vld4_lane): Likewise.
(cortex_a8_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
(cortex_a8_neon_vst1_3_4_regs): Likewise.
(cortex_a8_neon_vst2_4_regs_vst3_vst4): Likewise.
(cortex_a8_neon_vst1_vst2_lane): Likewise.
(cortex_a8_neon_vst3_vst4_lane): Likewise.
(cortex_a8_neon_mcr): Likewise.
(cortex_a8_neon_mcr_2_mcrr): Likewise.
(cortex_a8_neon_mrc): Likewise.
(cortex_a8_neon_mrrc): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203614
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/iterators.md (Vetype): Add SF and DF modes.
(fp): New.
* config/aarch64/aarch64-simd.md (neon_type): Remove.
(aarch64_simd_dup<mode>): Add "type" attribute.
(aarch64_dup_lane<mode>): Likewise.
(aarch64_dup_lane_<vswap_width_name><mode>): Likewise.
(*aarch64_simd_mov<mode>): Likewise.
(aarch64_simd_mov_from_<mode>low): Likewise.
(aarch64_simd_mov_from_<mode>high): Likewise.
(orn<mode>3): Likewise.
(bic<mode>3): Likewise.
(add<mode>3): Likewise.
(sub<mode>3): Likewise.
(mul<mode>3): Likewise.
(*aarch64_mul3_elt<mode>): Likewise.
(*aarch64_mul3_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_mul3_elt_to_128df): Likewise.
(*aarch64_mul3_elt_to_64v2df): Likewise.
(neg<mode>2): Likewise.
(abs<mode>2): Likewise.
(abd<mode>_3): Likewise.
(aba<mode>_3): Likewise.
(fabd<mode>_3): Likewise.
(*fabd_scalar<mode>3): Likewise.
(and<mode>3): Likewise.
(ior<mode>3): Likewise.
(xor<mode>3): Likewise.
(one_cmpl<mode>2): Likewise.
(aarch64_simd_vec_set<mode>): Likewise.
(aarch64_simd_lshr<mode>): Likewise.
(aarch64_simd_ashr<mode>): Likewise.
(aarch64_simd_imm_shl<mode>): Likewise.
(aarch64_simd_reg_sshl<mode): Likewise.
(aarch64_simd_reg_shl<mode>_unsigned): Likewise.
(aarch64_simd_reg_shl<mode>_signed): Likewise.
(aarch64_simd_vec_setv2di): Likewise.
(aarch64_simd_vec_set<mode>): Likewise.
(aarch64_mla<mode>): Likewise.
(*aarch64_mla_elt<mode>): Likewise.
(*aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
(aarch64_mls<mode>): Likewise.
(*aarch64_mls_elt<mode>): Likewise.
(*aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
(<su><maxmin><mode>3): Likewise.
(move_lo_quad_<mode>): Likewise.
(aarch64_simd_move_hi_quad_<mode>): Likewise.
(aarch64_simd_vec_pack_trunc_<mode>): Likewise.
(vec_pack_trunc_<mode>): Likewise.
(aarch64_simd_vec_unpack<su>_lo_<mode>): Likewise.
(aarch64_simd_vec_unpack<su>_hi_<mode>): Likewise.
(*aarch64_<su>mlal_lo<mode>): Likewise.
(*aarch64_<su>mlal_hi<mode>): Likewise.
(*aarch64_<su>mlsl_lo<mode>): Likewise.
(*aarch64_<su>mlsl_hi<mode>): Likewise.
(*aarch64_<su>mlal<mode>): Likewise.
(*aarch64_<su>mlsl<mode>): Likewise.
(aarch64_simd_vec_<su>mult_lo_<mode>): Likewise.
(aarch64_simd_vec_<su>mult_hi_<mode>): Likewise.
(add<mode>3): Likewise.
(sub<mode>3): Likewise.
(mul<mode>3): Likewise.
(div<mode>3): Likewise.
(neg<mode>2): Likewise.
(abs<mode>2): Likewise.
(fma<mode>4): Likewise.
(*aarch64_fma4_elt<mode>): Likewise.
(*aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_fma4_elt_to_128df): Likewise.
(*aarch64_fma4_elt_to_64v2df): Likewise.
(fnma<mode>4): Likewise.
(*aarch64_fnma4_elt<mode>): Likewise.
(*aarch64_fnma4_elt_<vswap_width_name><mode>
(*aarch64_fnma4_elt_to_128df): Likewise.
(*aarch64_fnma4_elt_to_64v2df): Likewise.
(<frint_pattern><mode>2): Likewise.
(l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): Likewise.
(<optab><fcvt_target><VDQF:VDQF:mode>2): Likewise.
(vec_unpacks_lo_v4sf): Likewise.
(aarch64_float_extend_lo_v2df): Likewise.
(vec_unpacks_hi_v4sf): Likewise.
(aarch64_float_truncate_lo_v2sf): Likewise.
(aarch64_float_truncate_hi_v4sf): Likewise.
(aarch64_vmls<mode>): Likewise.
(<su><maxmin><mode>3): Likewise.
(<maxmin_uns><mode>3): Likewise.
(reduc_<sur>plus_<mode>): Likewise.
(reduc_<sur>plus_v2di): Likewise.
(reduc_<sur>plus_v2si): Likewise.
(reduc_<sur>plus_<mode>): Likewise.
(aarch64_addpv4sf): Likewise.
(clz<mode>2): Likewise.
(reduc_<maxmin_uns>_<mode>): Likewise.
(reduc_<maxmin_uns>_v2di): Likewise.
(reduc_<maxmin_uns>_v2si): Likewise.
(reduc_<maxmin_uns>_<mode>): Likewise.
(reduc_<maxmin_uns>_v4sf): Likewise.
(aarch64_simd_bsl<mode>_internal): Likewise.
(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): Likewise.
(*aarch64_get_lane_zero_extendsi<mode>): Likewise.
(aarch64_get_lane<mode>): Likewise.
(*aarch64_combinez<mode>): Likewise.
(aarch64_combine<mode>): Likewise.
(aarch64_simd_combine<mode>): Likewise.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>_hi_internal): Likewise.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>_lo_internal): Likewise.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>): Likewise.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>): Likewise.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal): Likewise.
(aarch64_<sur>h<addsub><mode>): Likewise.
(aarch64_<sur><addsub>hn<mode>): Likewise.
(aarch64_<sur><addsub>hn2<mode>): Likewise.
(aarch64_pmul<mode>): Likewise.
(aarch64_<su_optab><optab><mode>): Likewise.
(aarch64_<sur>qadd<mode>): Likewise.
(aarch64_sqmovun<mode>): Likewise.
(aarch64_<sur>qmovn<mode>): Likewise.
(aarch64_s<optab><mode>): Likewise.
(aarch64_sq<r>dmulh<mode>): Likewise.
(aarch64_sq<r>dmulh_lane<mode>): Likewise.
(aarch64_sq<r>dmulh_laneq<mode>): Likewise.
(aarch64_sq<r>dmulh_lane<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_n<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_n<mode>_internal): Likewise.
(aarch64_sqdmull<mode>): Likewise.
(aarch64_sqdmull_lane<mode>_internal): Likewise.
(aarch64_sqdmull_n<mode>): Likewise.
(aarch64_sqdmull2<mode>_internal): Likewise.
(aarch64_sqdmull2_lane<mode>_internal): Likewise.
(aarch64_sqdmull2_n<mode>_internal): Likewise.
(aarch64_<sur>shl<mode>): Likewise.
(aarch64_<sur>q<r>shl<mode>
(aarch64_<sur>shll_n<mode>): Likewise.
(aarch64_<sur>shll2_n<mode>): Likewise.
(aarch64_<sur>shr_n<mode>): Likewise.
(aarch64_<sur>sra_n<mode>): Likewise.
(aarch64_<sur>s<lr>i_n<mode>): Likewise.
(aarch64_<sur>qshl<u>_n<mode>): Likewise.
(aarch64_<sur>q<r>shr<u>n_n<mode>): Likewise.
(aarch64_cm<optab><mode>): Likewise.
(aarch64_cm<optab>di): Likewise.
(aarch64_cm<optab><mode>): Likewise.
(aarch64_cm<optab>di): Likewise.
(aarch64_cmtst<mode>): Likewise.
(aarch64_cmtstdi): Likewise.
(aarch64_cm<optab><mode>): Likewise.
(*aarch64_fac<optab><mode>): Likewise.
(aarch64_addp<mode>): Likewise.
(aarch64_addpdi): Likewise.
(sqrt<mode>2): Likewise.
(vec_load_lanesoi<mode>): Likewise.
(vec_store_lanesoi<mode>): Likewise.
(vec_load_lanesci<mode>): Likewise.
(vec_store_lanesci<mode>): Likewise.
(vec_load_lanesxi<mode>): Likewise.
(vec_store_lanesxi<mode>): Likewise.
(*aarch64_mov<mode>): Likewise.
(aarch64_ld2<mode>_dreg): Likewise.
(aarch64_ld2<mode>_dreg): Likewise.
(aarch64_ld3<mode>_dreg): Likewise.
(aarch64_ld3<mode>_dreg): Likewise.
(aarch64_ld4<mode>_dreg): Likewise.
(aarch64_ld4<mode>_dreg): Likewise.
(aarch64_tbl1<mode>): Likewise.
(aarch64_tbl2v16qi): Likewise.
(aarch64_combinev16qi): Likewise.
(aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>): Likewise.
(aarch64_st2<mode>_dreg): Likewise.
(aarch64_st2<mode>_dreg): Likewise.
(aarch64_st3<mode>_dreg): Likewise.
(aarch64_st3<mode>_dreg): Likewise.
(aarch64_st4<mode>_dreg): Likewise.
(aarch64_st4<mode>_dreg): Likewise.
(*aarch64_simd_ld1r<mode>): Likewise.
(aarch64_frecpe<mode>): Likewise.
(aarch64_frecp<FRECP:frecp_suffix><mode>): Likewise.
(aarch64_frecps<mode>): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203613
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/iterators.md (V_elem_ch): New.
(q): Likewise.
(VQH_type): Likewise.
* config/arm/arm.md (is_neon_type): New.
(conds): Use is_neon_type.
(anddi3_insn): Update type attribute.
(xordi3_insn): Likewise.
(one_cmpldi2): Likewise.
* gcc/config/arm/vfp.md (movhf_vfp_neon): Update type attribute.
* gcc/config/arm/neon.md (neon_mov): Update type attribute.
(*movmisalign<mode>_neon_store): Likewise.
(*movmisalign<mode>_neon_load): Likewise.
(vec_set<mode>_internal): Likewise.
(vec_set<mode>_internal): Likewise.
(vec_setv2di_internal): Likewise.
(vec_extract<mode>): Likewise.
(vec_extract<mode>): Likewise.
(vec_extractv2di): Likewise.
(*add<mode>3_neon): Likewise.
(adddi3_neon): Likewise.
(*sub<mode>3_neon): Likewise.
(subdi3_neon): Likewise.
(fma<VCVTF:mode>4): Likewise.
(fma<VCVTF:mode>4_intrinsic): Likewise.
(*fmsub<VCVTF:mode>4): Likewise.
(fmsub<VCVTF:mode>4_intrinsic): Likewise.
(neon_vrint<NEON_VRINT:nvrint_variant><VCVTF:mode>): Likewise.
(ior<mode>3): Likewise.
(and<mode>3): Likewise.
(orn<mode>3_neon): Likewise.
(orndi3_neon): Likewise.
(bic<mode>3_neon): Likewise.
(bicdi3_neon): Likewise.
(xor<mode>3): Likewise.
(one_cmpl<mode>2): Likewise.
(abs<mode>2): Likewise.
(neg<mode>2): Likewise.
(negdi2_neon): Likewise.
(*umin<mode>3_neon): Likewise.
(*umax<mode>3_neon): Likewise.
(*smin<mode>3_neon): Likewise.
(*smax<mode>3_neon): Likewise.
(vashl<mode>3): Likewise.
(vashr<mode>3_imm): Likewise.
(vlshr<mode>3_imm): Likewise.
(ashl<mode>3_signed): Likewise.
(ashl<mode>3_unsigned): Likewise.
(neon_load_count): Likewise.
(ashldi3_neon_noclobber): Likewise.
(ashldi3_neon): Likewise.
(signed_shift_di3_neon): Likewise.
(unsigned_shift_di3_neon): Likewise.
(ashrdi3_neon_imm_noclobber): Likewise.
(lshrdi3_neon_imm_noclobber): Likewise.
(<shift>di3_neon): Likewise.
(widen_ssum<mode>3): Likewise.
(widen_usum<mode>3): Likewise.
(quad_halves_<code>v4si): Likewise.
(quad_halves_<code>v4sf): Likewise.
(quad_halves_<code>v8hi): Likewise.
(quad_halves_<code>v16qi): Likewise.
(reduc_splus_v2di): Likewise.
(neon_vpadd_internal<mode>): Likewise.
(neon_vpsmin<mode>): Likewise.
(neon_vpsmax<mode>): Likewise.
(neon_vpumin<mode>): Likewise.
(neon_vpumax<mode>): Likewise.
(*ss_add<mode>_neon): Likewise.
(*us_add<mode>_neon): Likewise.
(*ss_sub<mode>_neon): Likewise.
(*us_sub<mode>_neon): Likewise.
(neon_vadd<mode>_unspec): Likewise.
(neon_vaddl<mode>): Likewise.
(neon_vaddw<mode>): Likewise.
(neon_vhadd<mode>): Likewise.
(neon_vqadd<mode>): Likewise.
(neon_vaddhn<mode>): Likewise.
(neon_vmul<mode>): Likewise.
(neon_vfms<VCVTF:mode>): Likewise.
(neon_vmlal<mode>): Likewise.
(neon_vmls<mode>): Likewise.
(neon_vmlsl<mode>): Likewise.
(neon_vqdmulh<mode>): Likewise.
(neon_vqdmlal<mode>): Likewise.
(neon_vqdmlsl<mode>): Likewise.
(neon_vmull<mode>): Likewise.
(neon_vqdmull<mode>): Likewise.
(neon_vsub<mode>_unspec): Likewise.
(neon_vsubl<mode>): Likewise.
(neon_vsubw<mode>): Likewise.
(neon_vqsub<mode>): Likewise.
(neon_vhsub<mode>): Likewise.
(neon_vsubhn<mode>): Likewise.
(neon_vceq<mode>): Likewise.
(neon_vcge<mode>): Likewise.
(neon_vcgeu<mode>): Likewise.
(neon_vcgt<mode>): Likewise.
(neon_vcgtu<mode>): Likewise.
(neon_vcle<mode>): Likewise.
(neon_vclt<mode>): Likewise.
(neon_vcage<mode>): Likewise.
(neon_vcagt<mode>): Likewise.
(neon_vtst<mode>): Likewise.
(neon_vabd<mode>): Likewise.
(neon_vabdl<mode>): Likewise.
(neon_vaba<mode>): Likewise.
(neon_vabal<mode>): Likewise.
(neon_vmax<mode>): Likewise.
(neon_vmin<mode>): Likewise.
(neon_vpaddl<mode>): Likewise.
(neon_vpadal<mode>): Likewise.
(neon_vpmax<mode>): Likewise.
(neon_vpmin<mode>): Likewise.
(neon_vrecps<mode>): Likewise.
(neon_vrsqrts<mode>): Likewise.
(neon_vqabs<mode>): Likewise.
(neon_vqneg<mode>): Likewise.
(neon_vcls<mode>): Likewise.
(clz<mode>2): Likewise.
(popcount<mode>2): Likewise.
(neon_vrecpe<mode>): Likewise.
(neon_vrsqrte<mode>): Likewise.
(neon_vget_lane<mode>_sext_internal): Likewise.
(neon_vget_lane<mode>_zext_internal): Likewise.
(neon_vdup_n<mode>): Likewise.
(neon_vdup_n<mode>): Likewise.
(neon_vdup_nv2di): Likewise.
(neon_vdup_lane<mode>_interal): Likewise.
(*neon_vswp<mode>): Likewise.
(neon_vcombine<mode>): Likewise.
(float<mode><V_cvtto>2): Likewise.
(floatuns<mode><V_cvtto>2): Likewise.
(fix_trunc<mode><V_cvtto>2): Likewise.
(fixuns_trunc<mode><V_cvtto>2
(neon_vcvt<mode>): Likewise.
(neon_vcvt<mode>): Likewise.
(neon_vcvtv4sfv4hf): Likewise.
(neon_vcvtv4hfv4sf): Likewise.
(neon_vcvt_n<mode>): Likewise.
(neon_vcvt_n<mode>): Likewise.
(neon_vmovn<mode>): Likewise.
(neon_vqmovn<mode>): Likewise.
(neon_vqmovun<mode>): Likewise.
(neon_vmovl<mode>): Likewise.
(neon_vmul_lane<mode>): Likewise.
(neon_vmul_lane<mode>): Likewise.
(neon_vmull_lane<mode>): Likewise.
(neon_vqdmull_lane<mode>): Likewise.
(neon_vqdmulh_lane<mode>): Likewise.
(neon_vqdmulh_lane<mode>): Likewise.
(neon_vmla_lane<mode>): Likewise.
(neon_vmla_lane<mode>): Likewise.
(neon_vmlal_lane<mode>): Likewise.
(neon_vqdmlal_lane<mode>): Likewise.
(neon_vmls_lane<mode>): Likewise.
(neon_vmls_lane<mode>): Likewise.
(neon_vmlsl_lane<mode>): Likewise.
(neon_vqdmlsl_lane<mode>): Likewise.
(neon_vext<mode>): Likewise.
(neon_vrev64<mode>): Likewise.
(neon_vrev32<mode>): Likewise.
(neon_vrev16<mode>): Likewise.
(neon_vbsl<mode>_internal): Likewise.
(neon_vshl<mode>): Likewise.
(neon_vqshl<mode>): Likewise.
(neon_vshr_n<mode>): Likewise.
(neon_vshrn_n<mode>): Likewise.
(neon_vqshrn_n<mode>): Likewise.
(neon_vqshrun_n<mode>): Likewise.
(neon_vshl_n<mode>): Likewise.
(neon_vqshl_n<mode>): Likewise.
(neon_vqshlu_n<mode>): Likewise.
(neon_vshll_n<mode>): Likewise.
(neon_vsra_n<mode>): Likewise.
(neon_vsri_n<mode>): Likewise.
(neon_vsli_n<mode>): Likewise.
(neon_vtbl1v8qi): Likewise.
(neon_vtbl2v8qi): Likewise.
(neon_vtbl3v8qi): Likewise.
(neon_vtbl4v8qi): Likewise.
(neon_vtbl1v16qi): Likewise.
(neon_vtbl2v16qi): Likewise.
(neon_vcombinev16qi): Likewise.
(neon_vtbx1v8qi): Likewise.
(neon_vtbx2v8qi): Likewise.
(neon_vtbx3v8qi): Likewise.
(neon_vtbx4v8qi): Likewise.
(*neon_vtrn<mode>_insn): Likewise.
(*neon_vzip<mode>_insn): Likewise.
(*neon_vuzp<mode>_insn): Likewise.
(neon_vld1<mode>): Likewise.
(neon_vld1_lane<mode>): Likewise.
(neon_vld1_lane<mode>): Likewise.
(neon_vld1_dup<mode>): Likewise.
(neon_vld1_dup<mode>): Likewise.
(neon_vld1_dupv2di): Likewise.
(neon_vst1<mode>): Likewise.
(neon_vst1_lane<mode>): Likewise.
(neon_vst1_lane<mode>): Likewise.
(neon_vld2<mode>): Likewise.
(neon_vld2<mode>): Likewise.
(neon_vld2_lane<mode>): Likewise.
(neon_vld2_lane<mode>): Likewise.
(neon_vld2_dup<mode>): Likewise.
(neon_vst2<mode>): Likewise.
(neon_vst2<mode>): Likewise.
(neon_vst2_lane<mode>): Likewise.
(neon_vst2_lane<mode>): Likewise.
(neon_vld3<mode>): Likewise.
(neon_vld3qa<mode>): Likewise.
(neon_vld3qb<mode>): Likewise.
(neon_vld3_lane<mode>): Likewise.
(neon_vld3_lane<mode>): Likewise.
(neon_vld3_dup<mode>): Likewise.
(neon_vst3<mode>): Likewise.
(neon_vst3qa<mode>): Likewise.
(neon_vst3qb<mode>): Likewise.
(neon_vst3_lane<mode>): Likewise.
(neon_vst3_lane<mode>): Likewise.
(neon_vld4<mode>): Likewise.
(neon_vld4qa<mode>): Likewise.
(neon_vld4qb<mode>): Likewise.
(neon_vld4_lane<mode>): Likewise.
(neon_vld4_lane<mode>): Likewise.
(neon_vld4_dup<mode>): Likewise.
(neon_vst4<mode>): Likewise.
(neon_vst4qa<mode>): Likewise.
(neon_vst4qb<mode>): Likewise.
(neon_vst4_lane<mode>): Likewise.
(neon_vst4_lane<mode>): Likewise.
(neon_vec_unpack<US>_lo_<mode>): Likewise.
(neon_vec_unpack<US>_hi_<mode>): Likewise.
(neon_vec_<US>mult_lo_<mode>): Likewise.
(neon_vec_<US>mult_hi_<mode>): Likewise.
(neon_vec_<US>shiftl_<mode>): Likewise.
(neon_unpack<US>_<mode>): Likewise.
(neon_vec_<US>mult_<mode>): Likewise.
(vec_pack_trunc_<mode>): Likewise.
(neon_vec_pack_trunc_<mode>): Likewise.
(neon_vabd<mode>_2): Likewise.
(neon_vabd<mode>_3): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203612
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md (movtf_aarch64): Update type attribute.
(load_pair): Update type attribute.
(store_pair): Update type attribute.
* config/aarch64/iterators.md (q): New.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203611
2013-10-15 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md: Add new types for Neon insns.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r203241
2013-10-07 Renlin Li <Renlin.Li@arm.com>
* config/arm/arm-cores.def (cortex-a53): Use cortex tuning.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202560
2013-09-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (arm_cmpsi_insn): Split rI alternative.
Set type attribute correctly. Set predicable_short_it attribute.
(cmpsi_shiftsi): Remove %? from output template.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202448
2013-09-10 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md (generic_sched): New.
* config/aarch64/aarch64-generic.md (load): Make conditional
on generic_sched attribute.
(nonload): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202334
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md
(*movtf_aarch64): Use neon_<ls>dm_2 as type where v8type
is fpsimd_<load/store>2.
(load_pair<mode>): Likewise.
(store_pair<mode>): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202333
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md (type): Add "mrs" type.
* config/aarch64/aarch64.md
(aarch64_load_tp_hard): Make type "mrs".
* config/arm/arm.md
(load_tp_hard): Make type "mrs".
* config/arm/cortex-a15.md: Update with new attributes.
* config/arm/cortex-a5.md: Update with new attributes.
* config/arm/cortex-a53.md: Update with new attributes.
* config/arm/cortex-a7.md: Update with new attributes.
* config/arm/cortex-a8.md: Update with new attributes.
* config/arm/cortex-a9.md: Update with new attributes.
* config/arm/cortex-m4.md: Update with new attributes.
* config/arm/cortex-r4.md: Update with new attributes.
* config/arm/fa526.md: Update with new attributes.
* config/arm/fa606te.md: Update with new attributes.
* config/arm/fa626te.md: Update with new attributes.
* config/arm/fa726te.md: Update with new attributes.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202332
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md
(*movti_aarch64): Use "multiple" for type where v8type is "move2".
(*movtf_aarch64): Likewise.
* config/arm/arm.md
(thumb1_movdi_insn): Use "multiple" for type where more than one
instruction is used for a move.
(*arm32_movhf): Likewise.
(*thumb_movdf_insn): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202331
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md (type): Rename fcpys to fmov.
* config/arm/vfp.md
(*arm_movsi_vfp): Rename type fcpys as fmov.
(*thumb2_movsi_vfp): Likewise
(*movhf_vfp_neon): Likewise
(*movhf_vfp): Likewise
(*movsf_vfp): Likewise
(*thumb2_movsf_vfp): Likewise
(*movsfcc_vfp): Likewise
(*thumb2_movsfcc_vfp): Likewise
* config/aarch64/aarch64-simd.md
(move_lo_quad_<mode>): Replace type mov_reg with fmovs.
* config/aarch64/aarch64.md
(*movsi_aarch64): Replace type mov_reg with fmovs.
(*movdi_aarch64): Likewise
(*movsf_aarch64): Likewise
(*movdf_aarch64): Likewise
* config/arm/arm.c
(cortexa7_older_only): Rename TYPE_FCPYS to TYPE_FMOV.
* config/arm/iwmmxt.md
(*iwmmxt_movsi_insn): Rename type fcpys as fmov.
* config/arm/arm1020e.md: Update with new attributes.
* config/arm/cortex-a15-neon.md: Update with new attributes.
* config/arm/cortex-a5.md: Update with new attributes.
* config/arm/cortex-a53.md: Update with new attributes.
* config/arm/cortex-a7.md: Update with new attributes.
* config/arm/cortex-a8-neon.md: Update with new attributes.
* config/arm/cortex-a9.md: Update with new attributes.
* config/arm/cortex-m4-fpu.md: Update with new attributes.
* config/arm/cortex-r4f.md: Update with new attributes.
* config/arm/marvell-pj4.md: Update with new attributes.
* config/arm/vfp11.md: Update with new attributes.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202330
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md
(*madd<mode>): Fix type attribute.
(*maddsi_uxtw): Likewise.
(*msub<mode>): Likewise.
(*msubsi_uxtw): Likewise.
(<su_optab>maddsidi4): Likewise.
(<su_optab>msubsidi4): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202329
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md: Split fdiv<sd> as fsqrt<sd>, fdiv<sd>.
* config/arm/arm.md (core_cycles): Remove fdiv.
* config/arm/vfp.md:
(*sqrtsf2_vfp): Update for attribute changes.
(*sqrtdf2_vfp): Likewise.
* config/aarch64/aarch64.md:
(sqrt<mode>2): Update for attribute changes.
* config/arm/arm1020e.md: Update with new attributes.
* config/arm/cortex-a15-neon.md: Update with new attributes.
* config/arm/cortex-a5.md: Update with new attributes.
* config/arm/cortex-a53.md: Update with new attributes.
* config/arm/cortex-a7.md: Update with new attributes.
* config/arm/cortex-a8-neon.md: Update with new attributes.
* config/arm/cortex-a9.md: Update with new attributes.
* config/arm/cortex-m4-fpu.md: Update with new attributes.
* config/arm/cortex-r4f.md: Update with new attributes.
* config/arm/marvell-pj4.md: Update with new attributes.
* config/arm/vfp11.md: Update with new attributes.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202328
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md
(type): Split f_cvt as f_cvt, f_cvtf2i, f_cvti2f.
* config/aarch64/aarch64.md
(l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2): Update with
new attributes.
(fix_trunc<GPF:mode><GPI:mode>2): Likewise.
(fixuns_trunc<GPF:mode><GPI:mode>2): Likewise.
(float<GPI:mode><GPF:mode>2): Likewise.
* config/arm/vfp.md
(*truncsisf2_vfp): Update with new attributes.
(*truncsidf2_vfp): Likewise.
(fixuns_truncsfsi2): Likewise.
(fixuns_truncdfsi2): Likewise.
(*floatsisf2_vfp): Likewise.
(*floatsidf2_vfp): Likewise.
(floatunssisf2): Likewise.
(floatunssidf2): Likewise.
(*combine_vcvt_f32_<FCVTI32typename>): Likewise.
(*combine_vcvt_f64_<FCVTI32typename>): Likewise.
* config/arm/arm1020e.md: Update with new attributes.
* config/arm/cortex-a15-neon.md: Update with new attributes.
* config/arm/cortex-a5.md: Update with new attributes.
* config/arm/cortex-a53.md: Update with new attributes.
* config/arm/cortex-a7.md: Update with new attributes.
* config/arm/cortex-a8-neon.md: Update with new attributes.
* config/arm/cortex-a9.md: Update with new attributes.
* config/arm/cortex-m4-fpu.md: Update with new attributes.
* config/arm/cortex-r4f.md: Update with new attributes.
* config/arm/marvell-pj4.md: Update with new attributes.
* config/arm/vfp11.md: Update with new attributes.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202323
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md: Add "no_insn", "multiple" and "untyped"
types.
* config/arm/arm-fixed.md: Add type attribute to all insn
patterns.
(add<mode>3): Add type attribute.
(add<mode>3): Likewise.
(usadd<mode>3): Likewise.
(ssadd<mode>3): Likewise.
(sub<mode>3): Likewise.
(sub<mode>3): Likewise.
(ussub<mode>3): Likewise.
(sssub<mode>3): Likewise.
(ssmulsa3): Likewise.
(usmulusa3): Likewise.
(arm_usatsihi): Likewise.
* config/arm/vfp.md
(*movdi_vfp): Add types for all instructions.
(*movdi_vfp_cortexa8): Likewise.
(*movhf_vfp_neon): Likewise.
(*movhf_vfp): Likewise.
(*movdf_vfp): Likewise.
(*thumb2_movdf_vfp): Likewise.
(*thumb2_movdfcc_vfp): Likewise.
* config/arm/arm.md: Add type attribute to all insn patterns.
(*thumb1_adddi3): Add type attribute.
(*arm_adddi3): Likewise.
(*adddi_sesidi_di): Likewise.
(*adddi_zesidi_di): Likewise.
(*thumb1_addsi3): Likewise.
(addsi3_compare0): Likewise.
(*addsi3_compare0_scratch): Likewise.
(*compare_negsi_si): Likewise.
(cmpsi2_addneg): Likewise.
(*addsi3_carryin_<optab>): Likewise.
(*addsi3_carryin_alt2_<optab>): Likewise.
(*addsi3_carryin_clobercc_<optab>): Likewise.
(*subsi3_carryin): Likewise.
(*subsi3_carryin_const): Likewise.
(*subsi3_carryin_compare): Likewise.
(*subsi3_carryin_compare_const): Likewise.
(*arm_subdi3): Likewise.
(*thumb_subdi3): Likewise.
(*subdi_di_zesidi): Likewise.
(*subdi_di_sesidi): Likewise.
(*subdi_zesidi_di): Likewise.
(*subdi_sesidi_di): Likewise.
(*subdi_zesidi_ze): Likewise.
(thumb1_subsi3_insn): Likewise.
(*arm_subsi3_insn): Likewise.
(*anddi3_insn): Likewise.
(*anddi_zesidi_di): Likewise.
(*anddi_sesdi_di): Likewise.
(*ne_zeroextracts): Likewise.
(*ne_zeroextracts): Likewise.
(*ite_ne_zeroextr): Likewise.
(*ite_ne_zeroextr): Likewise.
(*anddi_notdi_di): Likewise.
(*anddi_notzesidi): Likewise.
(*anddi_notsesidi): Likewise.
(andsi_notsi_si): Likewise.
(thumb1_bicsi3): Likewise.
(*iordi3_insn): Likewise.
(*iordi_zesidi_di): Likewise.
(*iordi_sesidi_di): Likewise.
(*thumb1_iorsi3_insn): Likewise.
(*xordi3_insn): Likewise.
(*xordi_zesidi_di): Likewise.
(*xordi_sesidi_di): Likewise.
(*arm_xorsi3): Likewise.
(*andsi_iorsi3_no): Likewise.
(*smax_0): Likewise.
(*smax_m1): Likewise.
(*arm_smax_insn): Likewise.
(*smin_0): Likewise.
(*arm_smin_insn): Likewise.
(*arm_umaxsi3): Likewise.
(*arm_uminsi3): Likewise.
(*minmax_arithsi): Likewise.
(*minmax_arithsi_): Likewise.
(*satsi_<SAT:code>): Likewise.
(arm_ashldi3_1bit): Likewise.
(arm_ashrdi3_1bit): Likewise.
(arm_lshrdi3_1bit): Likewise.
(*arm_negdi2): Likewise.
(*thumb1_negdi2): Likewise.
(*arm_negsi2): Likewise.
(*thumb1_negsi2): Likewise.
(*negdi_extendsid): Likewise.
(*negdi_zero_extend): Likewise.
(*arm_abssi2): Likewise.
(*thumb1_abssi2): Likewise.
(*arm_neg_abssi2): Likewise.
(*thumb1_neg_abss): Likewise.
(one_cmpldi2): Likewise.
(extend<mode>di2): Likewise.
(*compareqi_eq0): Likewise.
(*arm_extendhisi2addsi): Likewise.
(*arm_movdi): Likewise.
(*thumb1_movdi_insn): Likewise.
(*arm_movt): Likewise.
(*thumb1_movsi_insn): Likewise.
(pic_add_dot_plus_four): Likewise.
(pic_add_dot_plus_eight): Likewise.
(tls_load_dot_plus_eight): Likewise.
(*thumb1_movhi_insn): Likewise.
(*thumb1_movsf_insn): Likewise.
(*movdf_soft_insn): Likewise.
(*thumb_movdf_insn): Likewise.
(cbranchsi4_insn): Likewise.
(cbranchsi4_scratch): Likewise.
(*negated_cbranchsi4): Likewise.
(*tbit_cbranch): Likewise.
(*tlobits_cbranch): Likewise.
(*tstsi3_cbranch): Likewise.
(*cbranchne_decr1): Likewise.
(*addsi3_cbranch): Likewise.
(*addsi3_cbranch_scratch): Likewise.
(*arm_cmpdi_insn): Likewise.
(*arm_cmpdi_unsig): Likewise.
(*arm_cmpdi_zero): Likewise.
(*thumb_cmpdi_zero): Likewise.
(*deleted_compare): Likewise.
(*mov_scc): Likewise.
(*mov_negscc): Likewise.
(*mov_notscc): Likewise.
(*cstoresi_eq0_thumb1_insn): Likewise.
(cstoresi_nltu_thumb1): Likewise.
(cstoresi_ltu_thu): Likewise.
(thumb1_addsi3_addgeu): Likewise.
(*arm_jump): Likewise.
(*thumb_jump): Likewise.
(*check_arch2): Likewise.
(arm_casesi_internal): Likewise.
(thumb1_casesi_dispatch): Likewise.
(*arm_indirect_jump): Likewise.
(*thumb1_indirect_jump): Likewise.
(nop): Likewise.
(*and_scc): Likewise.
(*ior_scc): Likewise.
(*compare_scc): Likewise.
(*cond_move): Likewise.
(*cond_arith): Likewise.
(*cond_sub): Likewise.
(*cmp_ite0): Likewise.
(*cmp_ite1): Likewise.
(*cmp_and): Likewise.
(*cmp_ior): Likewise.
(*ior_scc_scc): Likewise.
(*ior_scc_scc_cmp): Likewise.
(*and_scc_scc): Likewise.
(*and_scc_scc_cmp): Likewise.
(*and_scc_scc_nod): Likewise.
(*negscc): Likewise.
(movcond_addsi): Likewise.
(movcond): Likewise.
(*ifcompare_plus_move): Likewise.
(*if_plus_move): Likewise.
(*ifcompare_move_plus): Likewise.
(*if_move_plus): Likewise.
(*ifcompare_arith_arith): Likewise.
(*if_arith_arith): Likewise.
(*ifcompare_arith_move): Likewise.
(*if_arith_move): Likewise.
(*ifcompare_move_arith): Likewise.
(*if_move_arith): Likewise.
(*ifcompare_move_not): Likewise.
(*if_move_not): Likewise.
(*ifcompare_not_move): Likewise.
(*if_not_move): Likewise.
(*ifcompare_shift_move): Likewise.
(*if_shift_move): Likewise.
(*ifcompare_move_shift): Likewise.
(*if_move_shift): Likewise.
(*ifcompare_shift_shift): Likewise.
(*ifcompare_not_arith): Likewise.
(*ifcompare_arith_not): Likewise.
(*if_arith_not): Likewise.
(*ifcompare_neg_move): Likewise.
(*if_neg_move): Likewise.
(*ifcompare_move_neg): Likewise.
(*if_move_neg): Likewise.
(prologue_thumb1_interwork): Likewise.
(*cond_move_not): Likewise.
(*sign_extract_onebit): Likewise.
(*not_signextract_onebit): Likewise.
(stack_tie): Likewise.
(align_4): Likewise.
(align_8): Likewise.
(consttable_end): Likewise.
(consttable_1): Likewise.
(consttable_2): Likewise.
(consttable_4): Likewise.
(consttable_8): Likewise.
(consttable_16): Likewise.
(*thumb1_tablejump): Likewise.
(prefetch): Likewise.
(force_register_use): Likewise.
(thumb_eh_return): Likewise.
(load_tp_hard): Likewise.
(load_tp_soft): Likewise.
(tlscall): Likewise.
(*arm_movtas_ze): Likewise.
(*arm_rev): Likewise.
(*arm_revsh): Likewise.
(*arm_rev16): Likewise.
* config/arm/thumb2.md
(*thumb2_smaxsi3): Likewise.
(*thumb2_sminsi3): Likewise.
(*thumb32_umaxsi3): Likewise.
(*thumb2_uminsi3): Likewise.
(*thumb2_negdi2): Likewise.
(*thumb2_abssi2): Likewise.
(*thumb2_neg_abss): Likewise.
(*thumb2_movsi_insn): Likewise.
(tls_load_dot_plus_four): Likewise.
(*thumb2_movhi_insn): Likewise.
(*thumb2_mov_scc): Likewise.
(*thumb2_mov_negs): Likewise.
(*thumb2_mov_negs): Likewise.
(*thumb2_mov_nots): Likewise.
(*thumb2_mov_nots): Likewise.
(*thumb2_movsicc_): Likewise.
(*thumb2_movsfcc_soft_insn): Likewise.
(*thumb2_indirect_jump): Likewise.
(*thumb2_and_scc): Likewise.
(*thumb2_ior_scc): Likewise.
(*thumb2_ior_scc_strict_it): Likewise.
(*thumb2_cond_move): Likewise.
(*thumb2_cond_arith): Likewise.
(*thumb2_cond_ari): Likewise.
(*thumb2_cond_sub): Likewise.
(*thumb2_negscc): Likewise.
(*thumb2_movcond): Likewise.
(thumb2_casesi_internal): Likewise.
(thumb2_casesi_internal_pic): Likewise.
(*thumb2_alusi3_short): Likewise.
(*thumb2_mov<mode>_shortim): Likewise.
(*thumb2_addsi_short): Likewise.
(*thumb2_subsi_short): Likewise.
(thumb2_addsi3_compare0): Likewise.
(*thumb2_cbz): Likewise.
(*thumb2_cbnz): Likewise.
(*thumb2_one_cmplsi2_short): Likewise.
(*thumb2_negsi2_short): Likewise.
(*orsi_notsi_si): Likewise.
* config/arm/arm1020e.md: Update with new attributes.
* config/arm/arm1026ejs.md: Update with new attributes.
* config/arm/arm1136jfs.md: Update with new attributes.
* config/arm/arm926ejs.md: Update with new attributes.
* config/arm/cortex-a15.md: Update with new attributes.
* config/arm/cortex-a5.md: Update with new attributes.
* config/arm/cortex-a53.md: Update with new attributes.
* config/arm/cortex-a7.md: Update with new attributes.
* config/arm/cortex-a8.md: Update with new attributes.
* config/arm/cortex-a9.md: Update with new attributes.
* config/arm/cortex-m4.md: Update with new attributes.
* config/arm/cortex-r4.md: Update with new attributes.
* config/arm/fa526.md: Update with new attributes.
* config/arm/fa606te.md: Update with new attributes.
* config/arm/fa626te.md: Update with new attributes.
* config/arm/fa726te.md: Update with new attributes.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202292
2013-09-05 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md
(type): Remove frecpe, frecps, frecpx.
(aarch64_frecp<FRECP:frecp_suffix><mode>): Move to aarch64-simd.md,
fix to be a TARGET_SIMD instruction.
(aarch64_frecps): Remove.
* config/aarch64/aarch64-simd.md
(aarch64_frecp<FRECP:frecp_suffix><mode>): New, moved from aarch64.md
(aarch64_frecps<mode>): Handle all float/vector of float modes.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202291
2013-09-05 James Greenhalgh <james.greenhalgh@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
* config/arm/types.md (define_attr "type"):
Expand "arlo_imm"
into "adr", "alu_imm", "alus_imm", "logic_imm", "logics_imm".
Expand "arlo_reg"
into "adc_reg", "adc_imm", "adcs_reg", "adcs_imm", "alu_ext",
"alu_reg", "alus_ext", "alus_reg", "bfm", "csel", "logic_reg",
"logics_reg", "rev".
Expand "arlo_shift"
into "alu_shift_imm", "alus_shift_imm", "logic_shift_imm",
"logics_shift_imm".
Expand "arlo_shift_reg"
into "alu_shift_reg", "alus_shift_reg", "logic_shift_reg",
"logics_shift_reg".
Expand "clz" into "clz, "rbit".
Rename "shift" to "shift_imm".
* config/arm/arm.md (define_attr "core_cycles"): Update for attribute
changes.
Update for attribute changes all occurrences of arlo_* and
shift* types.
* config/arm/arm-fixed.md: Update for attribute changes
all occurrences of arlo_* types.
* config/arm/thumb2.md: Update for attribute changes all occurrences
of arlo_* types.
* config/arm/arm.c (xscale_sched_adjust_cost): (rtx insn, rtx
(cortexa7_older_only): Likewise.
(cortexa7_younger): Likewise.
* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
(1020alu_shift_op): Likewise.
(1020alu_shift_reg_op): Likewise.
* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
(alu_shift_op): Likewise.
(alu_shift_reg_op): Likewise.
* config/arm/arm1136jfs.md (11_alu_op): Update for
attribute changes.
(11_alu_shift_op): Likewise.
(11_alu_shift_reg_op): Likewise.
* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
(9_alu_shift_reg_op): Likewise.
* config/arm/cortex-a15.md (cortex_a15_alu): Update for
attribute changes.
(cortex_a15_alu_shift): Likewise.
(cortex_a15_alu_shift_reg): Likewise.
* config/arm/cortex-a5.md (cortex_a5_alu): Update for
attribute changes.
(cortex_a5_alu_shift): Likewise.
* config/arm/cortex-a53.md
(cortex_a53_alu): Update for attribute changes.
(cortex_a53_alu_shift): Likewise.
* config/arm/cortex-a7.md
(cortex_a7_alu_imm): Update for attribute changes.
(cortex_a7_alu_reg): Likewise.
(cortex_a7_alu_shift): Likewise.
* config/arm/cortex-a8.md
(cortex_a8_alu): Update for attribute changes.
(cortex_a8_alu_shift): Likewise.
(cortex_a8_alu_shift_reg): Likewise.
* config/arm/cortex-a9.md
(cortex_a9_dp): Update for attribute changes.
(cortex_a9_dp_shift): Likewise.
* config/arm/cortex-m4.md
(cortex_m4_alu): Update for attribute changes.
* config/arm/cortex-r4.md
(cortex_r4_alu): Update for attribute changes.
(cortex_r4_mov): Likewise.
(cortex_r4_alu_shift_reg): Likewise.
* config/arm/fa526.md
(526_alu_op): Update for attribute changes.
(526_alu_shift_op): Likewise.
* config/arm/fa606te.md
(606te_alu_op): Update for attribute changes.
* config/arm/fa626te.md
(626te_alu_op): Update for attribute changes.
(626te_alu_shift_op): Likewise.
* config/arm/fa726te.md
(726te_alu_op): Update for attribute changes.
(726te_alu_shift_op): Likewise.
(726te_alu_shift_reg_op): Likewise.
* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
(mp626_alu_shift_op): Likewise.
* config/arm/marvell-pj4.md (pj4_alu): Update for attribute changes.
(pj4_alu_conds): Likewise.
(pj4_shift): Likewise.
(pj4_shift_conds): Likewise.
(pj4_alu_shift): Likewise.
(pj4_alu_shift_conds): Likewise.
* config/aarch64/aarch64.md: Update for attribute change
all occurrences of arlo_* and shift* types.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r202272
2013-08-02 James Greenhalgh <james.greenhalgh@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/aarch64.md
(*movti_aarch64): Rename r_2_f and f_2_r.
(*movsf_aarch64): Likewise.
(*movdf_aarch64): Likewise.
(*movtf_aarch64): Likewise.
(aarch64_movdi_<mode>low): Likewise.
(aarch64_movdi_<mode>high): Likewise.
(aarch64_mov<mode>high_di): Likewise.
(aarch64_mov<mode>low_di): Likewise.
(aarch64_movtilow_tilow): Likewise.
* config/arm/arm.md (attribute "neon_type"): Delete. Move attribute
values to config/arm/types.md
(attribute "conds"): Update for attribute change.
(anddi3_insn): Likewise.
(iordi3_insn): Likewise.
(xordi3_insn): Likewise.
(one_cmpldi2): Likewise.
* config/arm/types.md (type): Add Neon types.
* config/arm/neon.md (neon_mov<mode>): Remove "neon_type" attribute,
use "type" attribute.
(movmisalign<mode>_neon_store): Likewise.
(movmisalign<mode>_neon_load): Likewise.
(vec_set<mode>_internal): Likewise.
(vec_setv2di_internal): Likewise.
(vec_extract<mode>): Likewise.
(vec_extractv2di): Likewise.
(add<mode>3_neon): Likewise.
(adddi3_neon): Likewise.
(sub<mode>3_neon): Likewise.
(subdi3_neon): Likewise.
(mul<mode>3_neon): Likewise.
(mul<mode>3add<mode>_neon): Likewise.
(mul<mode>3neg<mode>add<mode>_neon): Likewise.
(fma<VCVTF:mode>4)): Likewise.
(fma<VCVTF:mode>4_intrinsic): Likewise.
(fmsub<VCVTF:mode>4)): Likewise.
(fmsub<VCVTF:mode>4_intrinsic): Likewise.
(neon_vrint<NEON_VRINT:nvrint_variant><VCVTF:mode>): Likewise.
(ior<mode>3): Likewise.
(and<mode>3): Likewise.
(anddi3_neon): Likewise.
(orn<mode>3_neon): Likewise.
(orndi3_neon): Likewise.
(bic<mode>3_neon): Likewise.
(bicdi3_neon): Likewise.
(xor<mode>3): Likewise.
(one_cmpl<mode>2): Likewise.
(abs<mode>2): Likewise.
(neg<mode>2): Likewise.
(umin<mode>3_neon): Likewise.
(umax<mode>3_neon): Likewise.
(smin<mode>3_neon): Likewise.
(smax<mode>3_neon): Likewise.
(vashl<mode>3): Likewise.
(vashr<mode>3_imm): Likewise.
(vlshr<mode>3_imm): Likewise.
(ashl<mode>3_signed): Likewise.
(ashl<mode>3_unsigned): Likewise.
(neon_load_count): Likewise.
(ashldi3_neon_noclobber): Likewise.
(signed_shift_di3_neon): Likewise.
(unsigned_shift_di3_neon): Likewise.
(ashrdi3_neon_imm_noclobber): Likewise.
(lshrdi3_neon_imm_noclobber): Likewise.
(widen_ssum<mode>3): Likewise.
(widen_usum<mode>3): Likewise.
(quad_halves_<code>v4si): Likewise.
(quad_halves_<code>v4sf): Likewise.
(quad_halves_<code>v8hi): Likewise.
(quad_halves_<code>v16qi): Likewise.
(reduc_splus_v2di): Likewise.
(neon_vpadd_internal<mode>): Likewise.
(neon_vpsmin<mode>): Likewise.
(neon_vpsmax<mode>): Likewise.
(neon_vpumin<mode>): Likewise.
(neon_vpumax<mode>): Likewise.
(ss_add<mode>_neon): Likewise.
(us_add<mode>_neon): Likewise.
(ss_sub<mode>_neon): Likewise.
(us_sub<mode>_neon): Likewise.
(neon_vadd<mode>_unspec): Likewise.
(neon_vaddl<mode>): Likewise.
(neon_vaddw<mode>): Likewise.
(neon_vhadd<mode>): Likewise.
(neon_vqadd<mode>): Likewise.
(neon_vaddhn<mode>): Likewise.
(neon_vmul<mode>): Likewise.
(neon_vmla<mode>): Likewise.
(neon_vmlal<mode>): Likewise.
(neon_vmls<mode>): Likewise.
(neon_vmlsl<mode>): Likewise.
(neon_vqdmulh<mode>): Likewise.
(neon_vqdmlal<mode>): Likewise.
(neon_vqdmlsl<mode>): Likewise.
(neon_vmull<mode>): Likewise.
(neon_vqdmull<mode>): Likewise.
(neon_vsub<mode>_unspec): Likewise.
(neon_vsubl<mode>): Likewise.
(neon_vsubw<mode>): Likewise.
(neon_vqsub<mode>): Likewise.
(neon_vhsub<mode>): Likewise.
(neon_vsubhn<mode>): Likewise.
(neon_vceq<mode>): Likewise.
(neon_vcge<mode>): Likewise.
(neon_vcgeu<mode>): Likewise.
(neon_vcgt<mode>): Likewise.
(neon_vcgtu<mode>): Likewise.
(neon_vcle<mode>): Likewise.
(neon_vclt<mode>): Likewise.
(neon_vcage<mode>): Likewise.
(neon_vcagt<mode>): Likewise.
(neon_vtst<mode>): Likewise.
(neon_vabd<mode>): Likewise.
(neon_vabdl<mode>): Likewise.
(neon_vaba<mode>): Likewise.
(neon_vabal<mode>): Likewise.
(neon_vmax<mode>): Likewise.
(neon_vmin<mode>): Likewise.
(neon_vpaddl<mode>): Likewise.
(neon_vpadal<mode>): Likewise.
(neon_vpmax<mode>): Likewise.
(neon_vpmin<mode>): Likewise.
(neon_vrecps<mode>): Likewise.
(neon_vrsqrts<mode>): Likewise.
(neon_vqabs<mode>): Likewise.
(neon_vqneg<mode>): Likewise.
(neon_vcls<mode>): Likewise.
(clz<mode>2): Likewise.
(popcount<mode>2): Likewise.
(neon_vrecpe): Likewise.
(neon_vrsqrte): Likewise.
(neon_vget_lane<mode>_sext_internal): Likewise.
(neon_vget_lane<mode>_zext_internal): Likewise.
(neon_vdup_n<mode>): Likewise.
(neon_vdup_nv2di): Likewise.
(neon_vdpu_lane<mode>_internal): Likewise.
(neon_vswp<mode>): Likewise.
(float<mode><V_cvtto>2): Likewise.
(floatuns<mode><V_cvtto>2): Likewise.
(fix_trunc<mode><V_cvtto>)2): Likewise
(fixuns_trunc<mode><V_cvtto)2): Likewise.
(neon_vcvt<mode>): Likewise.
(neon_vcvtv4sfv4hf): Likewise.
(neon_vcvtv4hfv4sf): Likewise.
(neon_vcvt_n<mode>): Likewise.
(neon_vmovn<mode>): Likewise.
(neon_vqmovn<mode>): Likewise.
(neon_vqmovun<mode>): Likewise.
(neon_vmovl<mode>): Likewise.
(neon_vmul_lane<mode>): Likewise.
(neon_vmull_lane<mode>): Likewise.
(neon_vqdmull_lane<mode>): Likewise.
(neon_vqdmulh_lane<mode>): Likewise.
(neon_vmla_lane<mode>): Likewise.
(neon_vmlal_lane<mode>): Likewise.
(neon_vqdmlal_lane<mode>): Likewise.
(neon_vmls_lane<mode>): Likewise.
(neon_vmlsl_lane<mode>): Likewise.
(neon_vqdmlsl_lane<mode>): Likewise.
(neon_vext<mode>): Likewise.
(neon_vrev64<mode>): Likewise.
(neon_vrev32<mode>): Likewise.
(neon_vrev16<mode>): Likewise.
(neon_vbsl<mode>_internal): Likewise.
(neon_vshl<mode>): Likewise.
(neon_vqshl<mode>): Likewise.
(neon_vshr_n<mode>): Likewise.
(neon_vshrn_n<mode>): Likewise.
(neon_vqshrn_n<mode>): Likewise.
(neon_vqshrun_n<mode>): Likewise.
(neon_vshl_n<mode>): Likewise.
(neon_vqshl_n<mode>): Likewise.
(neon_vqshlu_n<mode>): Likewise.
(neon_vshll_n<mode>): Likewise.
(neon_vsra_n<mode>): Likewise.
(neon_vsri_n<mode>): Likewise.
(neon_vsli_n<mode>): Likewise.
(neon_vtbl1v8qi): Likewise.
(neon_vtbl2v8qi): Likewise.
(neon_vtbl3v8qi): Likewise.
(neon_vtbl4v8qi): Likewise.
(neon_vtbx1v8qi): Likewise.
(neon_vtbx2v8qi): Likewise.
(neon_vtbx3v8qi): Likewise.
(neon_vtbx4v8qi): Likewise.
(neon_vtrn<mode>_internal): Likewise.
(neon_vzip<mode>_internal): Likewise.
(neon_vuzp<mode>_internal): Likewise.
(neon_vld1<mode>): Likewise.
(neon_vld1_lane<mode>): Likewise.
(neon_vld1_dup<mode>): Likewise.
(neon_vld1_dupv2di): Likewise.
(neon_vst1<mode>): Likewise.
(neon_vst1_lane<mode>): Likewise.
(neon_vld2<mode>): Likewise.
(neon_vld2_lane<mode>): Likewise.
(neon_vld2_dup<mode>): Likewise.
(neon_vst2<mode>): Likewise.
(neon_vst2_lane<mode>): Likewise.
(neon_vld3<mode>): Likewise.
(neon_vld3qa<mode>): Likewise.
(neon_vld3qb<mode>): Likewise.
(neon_vld3_lane<mode>): Likewise.
(neon_vld3_dup<mode>): Likewise.
(neon_vst3<mode>): Likewise.
(neon_vst3qa<mode>): Likewise.
(neon_vst3qb<mode>): Likewise.
(neon_vst3_lane<mode>): Likewise.
(neon_vld4<mode>): Likewise.
(neon_vld4qa<mode>): Likewise.
(neon_vld4qb<mode>): Likewise.
(neon_vld4_lane<mode>): Likewise.
(neon_vld4_dup<mode>): Likewise.
(neon_vst4<mode>): Likewise.
(neon_vst4qa<mode>): Likewise.
(neon_vst4qb<mode>): Likewise.
(neon_vst4_lane<mode>): Likewise.
(neon_vec_unpack<US>_lo_<mode>): Likewise.
(neon_vec_unpack<US>_hi_<mode>): Likewise.
(neon_vec_<US>mult_lo_<mode>): Likewise.
(neon_vec_<US>mult_hi_<mode>): Likewise.
(neon_vec_<US>shiftl_<mode>): Likewise.
(neon_unpack<US>_<mode>): Likewise.
(neon_vec_<US>mult_<mode>): Likewise.
(vec_pack_trunc_<mode>): Likewise.
(neon_vec_pack_trunk_<mode>): Likewise.
(neon_vabd<mode>_2): Likewise.
(neon_vabd<mode>_3): Likewise.
* config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes.
(thumb2_movsi_vfp): Likewise.
(movdi_vfp): Likewise.
(movdi_vfp_cortexa8): Likewise.
(movhf_vfp_neon): Likewise.
(movhf_vfp): Likewiwse.
(movsf_vfp): Likewiwse.
(thumb2_movsf_vfp): Likewiwse.
(movdf_vfp): Likewise.
(thumb2_movdf_vfp): Likewise.
(movsfcc_vfp): Likewise.
(thumb2_movsfcc_vfp): Likewise.
(movdfcc_vfp): Likewise.
(thumb2_movdfcc_vfp): Likewise.
* config/arm/arm.c (cortexa7_older_only): Update for attribute change.
* config/arm/arm1020e.md (v10_c2v): Update for attribute change.
(v10_v2c): Likewise.
* config/arm/cortex-a15-neon.md (cortex_a15_neon_int_1): Update for
attribute change.
(cortex_a15_neon_int_2): Likewise.
(cortex_a15_neon_int_3): Likewise.
(cortex_a15_neon_int_4): Likewise.
(cortex_a15_neon_int_5): Likewise.
(cortex_a15_neon_vqneg_vqabs): Likewise.
(cortex_a15_neon_vmov): Likewise.
(cortex_a15_neon_vaba): Likewise.
(cortex_a15_neon_vaba_qqq): Likewise.
(cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a15_neon_mul_qqq_8_16_32_ddd_32): Likewise.
(cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_\
scalar_64_32_long_scalar): Likewise.
(cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a15_neon_mla_qqq_8_16): Likewise.
(cortex_a15_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\
lotype_qdd_64_32_long): Likewise.
(cortex_a15_neon_mla_qqq_32_qqd_32_scalar): Likewise.
(cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
(cortex_a15_neon_mul_qqd_32_scalar): Likewise.
(cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
(cortex_a15_neon_shift_1): Likewise.
(cortex_a15_neon_shift_2): Likewise.
(cortex_a15_neon_shift_3): Likewise.
(cortex_a15_neon_vshl_ddd): Likewise.
(cortex_a15_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
(cortex_a15_neon_vsra_vrsra): Likewise.
(cortex_a15_neon_fp_vadd_ddd_vabs_dd): Likewise.
(cortex_a15_neon_fp_vadd_qqq_vabs_qq): Likewise.
(cortex_a15_neon_fp_vmul_ddd): Likewise.
(cortex_a15_neon_fp_vmul_qqd): Likewise.
(cortex_a15_neon_fp_vmla_ddd): Likewise.
(cortex_a15_neon_fp_vmla_qqq): Likewise.
(cortex_a15_neon_fp_vmla_ddd_scalar): Likewise.
(cortex_a15_neon_fp_vmla_qqq_scalar): Likewise.
(cortex_a15_neon_fp_vrecps_vrsqrts_ddd): Likewise.
(cortex_a15_neon_fp_vrecps_vrsqrts_qqq): Likewise.
(cortex_a15_neon_bp_simple): Likewise.
(cortex_a15_neon_bp_2cycle): Likewise.
(cortex_a15_neon_bp_3cycle): Likewise.
(cortex_a15_neon_vld1_1_2_regs): Likewise.
(cortex_a15_neon_vld1_3_4_regs): Likewise.
(cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
(cortex_a15_neon_vld2_4_regs): Likewise.
(cortex_a15_neon_vld3_vld4): Likewise.
(cortex_a15_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
(cortex_a15_neon_vst1_3_4_regs): Likewise.
(cortex_a15_neon_vst2_4_regs_vst3_vst4): Likewise.
(cortex_a15_neon_vst3_vst4): Likewise.
(cortex_a15_neon_vld1_vld2_lane): Likewise.
(cortex_a15_neon_vld3_vld4_lane" 10
(cortex_a15_neon_vst1_vst2_lane): Likewise.
(cortex_a15_neon_vst3_vst4_lane): Likewise.
(cortex_a15_neon_vld3_vld4_all_lanes): Likewise.
(cortex_a15_neon_ldm_2): Likewise.0
(cortex_a15_neon_stm_2): Likewise.
(cortex_a15_neon_mcr): Likewise.
(cortex_a15_neon_mcr_2_mcrr): Likewise.
(cortex_a15_neon_mrc): Likewise.
(cortex_a15_neon_mrrc): Likewise.
* config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute
change.
(cortex_a15_alu_shift): Likewise.
(cortex_a15_alu_shift_reg): Likewise.
(cortex_a15_mult32): Likewise.
(cortex_a15_mult64): Likewise.
(cortex_a15_block): Likewise.
(cortex_a15_branch): Likewise.
(cortex_a15_load1): Likewise.
(cortex_a15_load3): Likewise.
(cortex_a15_store1): Likewise.
(cortex_a15_store3): Likewise.
(cortex_a15_call): Likewise.
* config/arm/cortex-a5.md (cortex_a5_r2f): Update for attribute
change.
(cortex_a5_f2r): Likewise.
* config/arm/cortex-a53.md (cortex_a53_r2f): Update for attribute
change.
(cortex_a53_f2r): Likewise.
* config/arm/cortex-a7.md
(cortex_a7_branch): Update for attribute change.
(cortex_a7_call): Likewise.
(cortex_a7_alu_imm): Likewise.
(cortex_a7_alu_reg): Likewise.
(cortex_a7_alu_shift): Likewise.
(cortex_a7_mul): Likewise.
(cortex_a7_load1): Likewise.
(cortex_a7_store1): Likewise.
(cortex_a7_load2): Likewise.
(cortex_a7_store2): Likewise.
(cortex_a7_load3): Likewise.
(cortex_a7_store3): Likewise.
(cortex_a7_load4): Likewise.
(cortex_a7_store4): Likewise.
(cortex_a7_fpalu): Likewise.
(cortex_a7_fconst): Likewise.
(cortex_a7_fpmuls): Likewise.
(cortex_a7_neon_mul): Likewise.
(cortex_a7_fpmacs): Likewise.
(cortex_a7_neon_mla: Likewise.
(cortex_a7_fpmuld: Likewise.
(cortex_a7_fpmacd: Likewise.
(cortex_a7_fpfmad: Likewise.
(cortex_a7_fdivs: Likewise.
(cortex_a7_fdivd: Likewise.
(cortex_a7_r2f: Likewise.
(cortex_a7_f2r: Likewise.
(cortex_a7_f_flags: Likewise.
(cortex_a7_f_loads: Likewise.
(cortex_a7_f_loadd: Likewise.
(cortex_a7_f_stores: Likewise.
(cortex_a7_f_stored: Likewise.
(cortex_a7_neon): Likewise.
* config/arm/cortex-a8-neon.md
(cortex_a8_neon_mrc): Update for attribute change.
(cortex_a8_neon_mrrc): Likewise.
(cortex_a8_neon_int_1): Likewise.
(cortex_a8_neon_int_2): Likewise.
(cortex_a8_neon_int_3): Likewise.
(cortex_a8_neon_int_4): Likewise.
(cortex_a8_neon_int_5): Likewise.
(cortex_a8_neon_vqneg_vqabs): Likewise.
(cortex_a8_neon_vmov): Likewise.
(cortex_a8_neon_vaba): Likewise.
(cortex_a8_neon_vaba_qqq): Likewise.
(cortex_a8_neon_vsma): Likewise.
(cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a8_neon_mul_qqq_8_16_32_ddd_32): Likewise.
(cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
Likewise.
(cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a8_neon_mla_qqq_8_16): Likewise.
(cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\
long_scalar_qdd_64_32_long): Likewise.
(cortex_a8_neon_mla_qqq_32_qqd_32_scalar): Likewise.
(cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
(cortex_a8_neon_mul_qqd_32_scalar): Likewise.
(cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
(cortex_a8_neon_shift_1): Likewise.
(cortex_a8_neon_shift_2): Likewise.
(cortex_a8_neon_shift_3): Likewise.
(cortex_a8_neon_vshl_ddd): Likewise.
(cortex_a8_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
(cortex_a8_neon_vsra_vrsra): Likewise.
(cortex_a8_neon_fp_vadd_ddd_vabs_dd): Likewise.
(cortex_a8_neon_fp_vadd_qqq_vabs_qq): Likewise.
(cortex_a8_neon_fp_vsum): Likewise.
(cortex_a8_neon_fp_vmul_ddd): Likewise.
(cortex_a8_neon_fp_vmul_qqd): Likewise.
(cortex_a8_neon_fp_vmla_ddd): Likewise.
(cortex_a8_neon_fp_vmla_qqq): Likewise.
(cortex_a8_neon_fp_vmla_ddd_scalar): Likewise.
(cortex_a8_neon_fp_vmla_qqq_scalar): Likewise.
(cortex_a8_neon_fp_vrecps_vrsqrts_ddd): Likewise.
(cortex_a8_neon_fp_vrecps_vrsqrts_qqq): Likewise.
(cortex_a8_neon_bp_simple): Likewise.
(cortex_a8_neon_bp_2cycle): Likewise.
(cortex_a8_neon_bp_3cycle): Likewise.
(cortex_a8_neon_ldr): Likewise.
(cortex_a8_neon_str): Likewise.
(cortex_a8_neon_vld1_1_2_regs): Likewise.
(cortex_a8_neon_vld1_3_4_regs): Likewise.
(cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
(cortex_a8_neon_vld2_4_regs): Likewise.
(cortex_a8_neon_vld3_vld4): Likewise.
(cortex_a8_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
(cortex_a8_neon_vst1_3_4_regs): Likewise.
(cortex_a8_neon_vst2_4_regs_vst3_vst4): Likewise.
(cortex_a8_neon_vst3_vst4): Likewise.
(cortex_a8_neon_vld1_vld2_lane): Likewise.
(cortex_a8_neon_vld3_vld4_lane): Likewise.
(cortex_a8_neon_vst1_vst2_lane): Likewise.
(cortex_a8_neon_vst3_vst4_lane): Likewise.
(cortex_a8_neon_vld3_vld4_all_lanes): Likewise.
(cortex_a8_neon_mcr): Likewise.
(cortex_a8_neon_mcr_2_mcrr): Likewise.
* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute
change.
* config/arm/cortex-a9-neon.md (ca9_neon_mrc): Update for attribute
change.
(ca9_neon_mrrc): Likewise.
(cortex_a9_neon_int_1): Likewise.
(cortex_a9_neon_int_2): Likewise.
(cortex_a9_neon_int_3): Likewise.
(cortex_a9_neon_int_4): Likewise.
(cortex_a9_neon_int_5): Likewise.
(cortex_a9_neon_vqneg_vqabs): Likewise.
(cortex_a9_neon_vmov): Likewise.
(cortex_a9_neon_vaba): Likewise.
(cortex_a9_neon_vaba_qqq): Likewise.
(cortex_a9_neon_vsma): Likewise.
(cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a9_neon_mul_qqq_8_16_32_ddd_32): Likewise.
(cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar):
Likewise.
(cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise.
(cortex_a9_neon_mla_qqq_8_16): Likewise.
(cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\
long_scalar_qdd_64_32_long): Likewise.
(cortex_a9_neon_mla_qqq_32_qqd_32_scalar): Likewise.
(cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise.
(cortex_a9_neon_mul_qqd_32_scalar): Likewise.
(cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise.
(cortex_a9_neon_shift_1): Likewise.
(cortex_a9_neon_shift_2): Likewise.
(cortex_a9_neon_shift_3): Likewise.
(cortex_a9_neon_vshl_ddd): Likewise.
(cortex_a9_neon_vqshl_vrshl_vqrshl_qqq): Likewise.
(cortex_a9_neon_vsra_vrsra): Likewise.
(cortex_a9_neon_fp_vadd_ddd_vabs_dd): Likewise.
(cortex_a9_neon_fp_vadd_qqq_vabs_qq): Likewise.
(cortex_a9_neon_fp_vsum): Likewise.
(cortex_a9_neon_fp_vmul_ddd): Likewise.
(cortex_a9_neon_fp_vmul_qqd): Likewise.
(cortex_a9_neon_fp_vmla_ddd): Likewise.
(cortex_a9_neon_fp_vmla_qqq): Likewise.
(cortex_a9_neon_fp_vmla_ddd_scalar): Likewise.
(cortex_a9_neon_fp_vmla_qqq_scalar): Likewise.
(cortex_a9_neon_fp_vrecps_vrsqrts_ddd): Likewise.
(cortex_a9_neon_fp_vrecps_vrsqrts_qqq): Likewise.
(cortex_a9_neon_bp_simple): Likewise.
(cortex_a9_neon_bp_2cycle): Likewise.
(cortex_a9_neon_bp_3cycle): Likewise.
(cortex_a9_neon_ldr): Likewise.
(cortex_a9_neon_str): Likewise.
(cortex_a9_neon_vld1_1_2_regs): Likewise.
(cortex_a9_neon_vld1_3_4_regs): Likewise.
(cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise.
(cortex_a9_neon_vld2_4_regs): Likewise.
(cortex_a9_neon_vld3_vld4): Likewise.
(cortex_a9_neon_vst1_1_2_regs_vst2_2_regs): Likewise.
(cortex_a9_neon_vst1_3_4_regs): Likewise.
(cortex_a9_neon_vst2_4_regs_vst3_vst4): Likewise.
(cortex_a9_neon_vst3_vst4): Likewise.
(cortex_a9_neon_vld1_vld2_lane): Likewise.
(cortex_a9_neon_vld3_vld4_lane): Likewise.
(cortex_a9_neon_vst1_vst2_lane): Likewise.
(cortex_a9_neon_vst3_vst4_lane): Likewise.
(cortex_a9_neon_vld3_vld4_all_lanes): Likewise.
(cortex_a9_neon_mcr): Likewise.
(cortex_a9_neon_mcr_2_mcrr): Likewise.
* config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change.
(cortex_a9_fps): Likewise.
* config/arm/cortex-m4-fpu.md (cortex_m4_vmov_2): Update for attribute
change.
(cortex_m4_fmuls): Likewise.
* config/arm/cortex-r4f.md (cortex_r4_mcr): Update for attribute
change.
(cortex_r4_mrc): Likewise.
* config/arm/iterators.md: Update comment referring to neon_type.
* config/arm/iwmmxt.md
(iwmmxt_arm_movdi): Update for attribute change.
(iwmmxt_movsi_insn): Likewise.
* config/arm/marvell-pj4.md
(pj4_vfp_to_core): Update for attribute change.
(pj4_core_to_vfp): Likewise.
* config/arm/neon-schedgen.ml (emit_insn_reservations): Update for
attribute change.
* config/arm/vfp11.md (vfp_fload): Update for attribute change.
(vfp_fstore): Likewise.
* doc/md.texi: Change references to neon_type to refer to type.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r201436
2013-08-02 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/types.md (define_attr "type"): Add "load_acq" and "store_rel".
* config/arm/cortex-a53.md (cortex_a53_load1): Update for attribute
changes.
(cortex_a53_store1): Likewise.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r201400
2013-08-01 Sofiane Naci <sofiane.naci@arm.com>
* config.gcc (aarch64*-*-*): Add aarch-common.o to extra_objs. Add
aarch-common-protos.h to extra_headers.
(aarch64*-*-*): Add arm/aarch-common-protos.h to tm_p_file.
* config/aarch64/aarch64.md: Include "../arm/cortex-a53.md".
* config/aarch64/t-aarch64 (aarch-common.o): Define.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r201399
2013-08-01 Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/aarch64.md (define_attr "type"): Delete.
Include "../arm/types.md". Define "type" attribute for all patterns.
* config/aarch64/aarch64-simd.md (move_lo_quad_<mode>): Update for
attribute changes.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r201376
2013-07-31 Sofiane Naci <sofiane.naci@arm.com>
* config.gcc (arm*-*-*): Add aarch-common.o to extra_objs. Add
aarch-common-protos.h to extra_headers.
(arm*-*-*): Add arm/aarch-common-protos.h to tm_p_file.
* config/arm/arm.c (arm_early_load_addr_dep): Move from here to ...
(arm_early_store_addr_dep): Likewise.
(arm_no_early_alu_shift_dep: Likewise.
(arm_no_early_alu_shift_value_dep: Likewise.
(arm_no_early_mul_dep: Likewise.
(arm_no_early_store_addr_dep: Likewise.
(arm_mac_accumulator_is_mul_result: Likewise.
(arm_mac_accumulator_is_result: Likewise.
* config/arm/aarch-common.c: ... here. New file.
* config/arm/arm-protos.h (arm_early_load_addr_dep): Move from here to ...
(arm_early_store_addr_dep): Likewise.
(arm_no_early_alu_shift_dep: Likewise.
(arm_no_early_alu_shift_value_dep: Likewise.
(arm_no_early_mul_dep: Likewise.
(arm_no_early_store_addr_dep: Likewise.
(arm_mac_accumulator_is_mul_result: Likewise.
(arm_mac_accumulator_is_result: Likewise.
* config/arm/aarch-common-protos.h: ... here. New file.
* config/arm/t-arm (aarch-common.o): Define.
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r201375
2013-07-31 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/arm.md: Include new file "types.md".
(define_attr "type"): Move from here to ...
(define_attr "mul32"): Likewise.
(define_attr "mul64"): Likewise.
* config/arm/types.md: ... here. New file.
testsuite/
2014-04-07 Michael Collison <michael.collison@linaro.org>
Backport from trunk r204784
2013-11-14 James Greenhalgh <james.greenhalgh@arm.com>
* gcc.target/aarch64/cpu-diagnostics-2.c: Change "-mcpu="
to "cortex-a53".
* gcc.target/aarch64/cpu-diagnostics-3.c: Change "-mcpu="
to "cortex-a53".
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@209189 138bc75d-0d04-0410-961f-82ee72b054a4
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gcc/
Backport from trunk r202663
2013-09-17 Cong Hou <congh@google.com>
* tree-vect-patterns.c (vect_recog_dot_prod_pattern): Fix a bug
when checking the dot production pattern. The type of rhs operand
of multiply is now checked correctly.
testsuite/
Backport from trunk r202663
2013-09-17 Cong Hou <congh@google.com>
* gcc.dg/vect/vect-reduc-dot-s16c.c: Add a test case with dot product
on two arrays with short and int types. This should not be recognized
as a dot product pattern.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@209188 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@209178 138bc75d-0d04-0410-961f-82ee72b054a4
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|
2014-04-02 Zhenqiang Chen <zhenqiang.chen@linaro.org>
Backport from trunk r208511
2014-03-12 Christian Bruel <christian.bruel@st.com>
PR target/60264
* config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Emit a
REG_CFA_DEF_CFA note.
(arm_expand_epilogue_apcs_frame): call arm_add_cfa_adjust_cfa_note.
(arm_unwind_emit): Allow REG_CFA_DEF_CFA.
gcc/testsuite/
2014-04-02 Zhenqiang Chen <zhenqiang.chen@linaro.org>
Backport from trunk r208511
2014-03-12 Christian Bruel <christian.bruel@st.com>
PR target/60264
* gcc.target/arm/pr60264.c
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@209009 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@208578 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@208576 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@208471 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@207762 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@207760 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@207687 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@207657 138bc75d-0d04-0410-961f-82ee72b054a4
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gcc:
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206518
2014-01-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (arm_init_iwmmxt_builtins): Skip
non-iwmmxt builtins.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206151
2013-12-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/neon.ml (crypto_intrinsics): Add vceq_64 and vtst_p64.
* config/arm/arm_neon.h: Regenerate.
* config/arm/neon-docgen.ml: Add vceq_p64 and vtst_p64.
* doc/arm-neon-intrinsics.texi: Regenerate.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206149
2013-12-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm_acle.h: Add underscores before variables.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206132
2013-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/neon-docgen.ml: Add crypto intrinsics documentation.
* doc/arm-neon-intrinsics.texi: Regenerate.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206131
2013-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/neon-testgen.ml (effective_target): Handle "CRYPTO".
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206130
2013-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (enum arm_builtins): Add crypto builtins.
(arm_init_neon_builtins): Handle crypto builtins.
(bdesc_2arg): Likewise.
(bdesc_1arg): Likewise.
(bdesc_3arg): New table.
(arm_expand_ternop_builtin): New function.
(arm_expand_unop_builtin): Handle sha1h explicitly.
(arm_expand_builtin): Handle ternary builtins.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS):
Define __ARM_FEATURE_CRYPTO.
* config/arm/arm.md: Include crypto.md.
(is_neon_type): Add crypto types.
* config/arm/arm_neon_builtins.def: Add TImode reinterprets.
* config/arm/crypto.def: New.
* config/arm/crypto.md: Likewise.
* config/arm/iterators.md (CRYPTO_UNARY): New int iterator.
(CRYPTO_BINARY): Likewise.
(CRYPTO_TERNARY): Likewise.
(CRYPTO_SELECTING): Likewise.
(crypto_pattern): New int attribute.
(crypto_size_sfx): Likewise.
(crypto_mode): Likewise.
(crypto_type): Likewise.
* config/arm/neon-gen.ml: Handle poly64_t and poly128_t types.
Handle crypto intrinsics.
* config/arm/neon.ml: Add support for poly64 and polt128 types
and intrinsics. Define crypto intrinsics.
* config/arm/neon.md (neon_vreinterpretti<mode>): New pattern.
(neon_vreinterpretv16qi<mode>): Use VQXMOV mode iterator.
(neon_vreinterpretv8hi<mode>): Likewise.
(neon_vreinterpretv4si<mode>): Likewise.
(neon_vreinterpretv4sf<mode>): Likewise.
(neon_vreinterpretv2di<mode>): Likewise.
* config/arm/unspecs.md (UNSPEC_AESD, UNSPEC_AESE, UNSPEC_AESIMC,
UNSPEC_AESMC, UNSPEC_SHA1C, UNSPEC_SHA1M, UNSPEC_SHA1P, UNSPEC_SHA1H,
UNSPEC_SHA1SU0, UNSPEC_SHA1SU1, UNSPEC_SHA256H, UNSPEC_SHA256H2,
UNSPEC_SHA256SU0, UNSPEC_SHA256SU1, VMULLP64): Define.
* config/arm/arm_neon.h: Regenerate.
Modifications needed to backport into linaro-4_8-branch:
* config/arm/arm.md (attribute neon_type): neon_crypto_aes,
neon_crypto_sha1_xor, neon_crypto_sha1_fast,
neon_crypto_sha1_slow, neon_crypto_sha256_fast,
neon_crypto_sha256_slow, neon_mul_d_long: New.
instead of:
* config/arm/arm.md: Include crypto.md.
(is_neon_type): Add crypto types.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206128
2013-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* Makefile.in (TEXI_GCC_FILES): Add arm-acle-intrinsics.texi.
* config.gcc (extra_headers): Add arm_acle.h.
* config/arm/arm.c (FL_CRC32): Define.
(arm_have_crc): Likewise.
(arm_option_override): Set arm_have_crc.
(arm_builtins): Add CRC32 builtins.
(bdesc_2arg): Likewise.
(arm_init_crc32_builtins): New function.
(arm_init_builtins): Initialise CRC32 builtins.
(arm_file_start): Handle architecture extensions.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_FEATURE_CRC32.
Define __ARM_32BIT_STATE.
(TARGET_CRC32): Define.
* config/arm/arm-arches.def: Add armv8-a+crc.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.md (type): Add crc.
(<crc_variant>): New insn.
* config/arm/arm_acle.h: New file.
* config/arm/iterators.md (CRC): New int iterator.
(crc_variant, crc_mode): New int attributes.
* confg/arm/unspecs.md (UNSPEC_CRC32B, UNSPEC_CRC32H, UNSPEC_CRC32W,
UNSPEC_CRC32CB, UNSPEC_CRC32CH, UNSPEC_CRC32CW): New unspecs.
* doc/invoke.texi: Document -march=armv8-a+crc option.
* doc/extend.texi: Document ACLE intrinsics.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206120
2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins):
Define builtin types for poly64_t poly128_t.
(TYPES_BINOPP, aarch64_types_binopp_qualifiers): New.
* aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi,
aarch64_crypto_pmullv2di): New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Update table for
poly64x2_t mangler.
* config/aarch64/arm_neon.h (poly64x2_t, poly64_t, poly128_t): Define.
(vmull_p64, vmull_high_p64): New.
* config/aarch64/iterators.md (UNSPEC_PMULL<2>): New.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206119
2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-simd.md (aarch64_crypto_sha256h<sha256_op>v4si,
aarch64_crypto_sha256su0v4si, aarch64_crypto_sha256su1v4si): New.
* config/aarch64/arm_neon.h (vsha256hq_u32, vsha256h2q_u32,
vsha256su0q_u32, vsha256su1q_u32): New.
* config/aarch64/iterators.md (UNSPEC_SHA256H<2>, UNSPEC_SHA256SU<01>):
New.
(CRYPTO_SHA256): New int iterator.
(sha256_op): New int attribute.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206118
2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_ternopu_qualifiers,
TYPES_TERNOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hsi,
aarch64_crypto_sha1su1v4si, aarch64_crypto_sha1<sha1_op>v4si,
aarch64_crypto_sha1su0v4si): New.
* config/aarch64/arm_neon.h (vsha1cq_u32, sha1mq_u32, vsha1pq_u32,
vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): New.
* config/aarch64/iterators.md (UNSPEC_SHA1<CPMH>, UNSPEC_SHA1SU<01>):
New.
(CRYPTO_SHA1): New int iterator.
(sha1_op): New int attribute.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206117
2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Update builtins table.
* config/aarch64/aarch64-builtins.c (aarch64_types_binopu_qualifiers,
TYPES_BINOPU): New.
* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aes_op>v16qi,
aarch64_crypto_aes<aesmc_op>v16qi): New.
* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
vaesimcq_u8): New.
* config/aarch64/iterators.md (UNSPEC_AESE, UNSPEC_AESD, UNSPEC_AESMC,
UNSPEC_AESIMC): New.
(CRYPTO_AES, CRYPTO_AESMC): New int iterators.
(aes_op, aesmc_op): New int attributes.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206115
2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* config/arm/types.md (neon_mul_d_long, crypto_aes, crypto_sha1_xor,
crypto_sha1_fast, crypto_sha1_slow, crypto_sha256_fast,
crypto_sha256_slow): New.
Modifications needed to backport into linaro-4_8-branch:
* config/aarch64/aarch64-simd.md (attribute simd_type):
(simd_mul_d_long, simd_crypto_aes, simd_crypto_sha1_xor,
simd_crypto_sha1_fast, simd_crypto_sha1_slow, simd_crypto_sha256_fast,
simd_crypto_sha256_slow) : New.
instead of the above change.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206114
2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64.h (TARGET_CRYPTO): New.
(__ARM_FEATURE_CRYPTO): Define if TARGET_CRYPTO is true.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r205384.
2013-11-26 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_type_qualifiers): Add qualifier_poly.
(aarch64_build_scalar_type): Also build Poly types.
(aarch64_build_vector_type): Likewise.
(aarch64_build_type): Likewise.
(aarch64_build_signed_type): New.
(aarch64_build_unsigned_type): Likewise.
(aarch64_build_poly_type): Likewise.
(aarch64_init_simd_builtins): Also handle Poly types.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r205383.
2013-11-26 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c
(VAR1): Use new naming scheme for aarch64_builtins.
(aarch64_builtin_vectorized_function): Use new
aarch64_builtins names.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r205092.
2013-11-20 James Greenhalgh <james.greenhalgh@arm.com>
* gcc/config/aarch64/aarch64-builtins.c
(aarch64_simd_itype): Remove.
(aarch64_simd_builtin_datum): Remove itype, add
qualifiers pointer.
(VAR1): Use qualifiers.
(aarch64_build_scalar_type): New.
(aarch64_build_vector_type): Likewise.
(aarch64_build_type): Likewise.
(aarch64_init_simd_builtins): Refactor, remove special cases,
consolidate main loop.
(aarch64_simd_expand_args): Likewise.
gcc/testsuite:
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206519
2014-01-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* lib/target-supports.exp
(check_effective_target_arm_crypto_ok_nocache): New.
(check_effective_target_arm_crypto_ok): Use above procedure.
(add_options_for_arm_crypto): Use et_arm_crypto_flags.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206151
2013-12-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/arm/neon-vceq_p64.c: New test.
* gcc.target/arm/neon-vtst_p64.c: Likewise.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206131
2013-12-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* lib/target-supports.exp (check_effective_target_arm_crypto_ok):
New procedure.
(add_options_for_arm_crypto): Likewise.
* gcc.target/arm/crypto-vaesdq_u8.c: New test.
* gcc.target/arm/crypto-vaeseq_u8.c: Likewise.
* gcc.target/arm/crypto-vaesimcq_u8.c: Likewise.
* gcc.target/arm/crypto-vaesmcq_u8.c: Likewise.
* gcc.target/arm/crypto-vldrq_p128.c: Likewise.
* gcc.target/arm/crypto-vmull_high_p64.c: Likewise.
* gcc.target/arm/crypto-vmullp64.c: Likewise.
* gcc.target/arm/crypto-vsha1cq_u32.c: Likewise.
* gcc.target/arm/crypto-vsha1h_u32.c: Likewise.
* gcc.target/arm/crypto-vsha1mq_u32.c: Likewise.
* gcc.target/arm/crypto-vsha1pq_u32.c: Likewise.
* gcc.target/arm/crypto-vsha1su0q_u32.c: Likewise.
* gcc.target/arm/crypto-vsha1su1q_u32.c: Likewise.
* gcc.target/arm/crypto-vsha256h2q_u32.c: Likewise.
* gcc.target/arm/crypto-vsha256hq_u32.c: Likewise.
* gcc.target/arm/crypto-vsha256su0q_u32.c: Likewise.
* gcc.target/arm/crypto-vsha256su1q_u32.c: Likewise.
* gcc.target/arm/crypto-vstrq_p128.c: Likewise.
* gcc.target/arm/neon/vbslQp64: Generate.
* gcc.target/arm/neon/vbslp64: Likewise.
* gcc.target/arm/neon/vcombinep64: Likewise.
* gcc.target/arm/neon/vcreatep64: Likewise.
* gcc.target/arm/neon/vdupQ_lanep64: Likewise.
* gcc.target/arm/neon/vdupQ_np64: Likewise.
* gcc.target/arm/neon/vdup_lanep64: Likewise.
* gcc.target/arm/neon/vdup_np64: Likewise.
* gcc.target/arm/neon/vextQp64: Likewise.
* gcc.target/arm/neon/vextp64: Likewise.
* gcc.target/arm/neon/vget_highp64: Likewise.
* gcc.target/arm/neon/vget_lowp64: Likewise.
* gcc.target/arm/neon/vld1Q_dupp64: Likewise.
* gcc.target/arm/neon/vld1Q_lanep64: Likewise.
* gcc.target/arm/neon/vld1Qp64: Likewise.
* gcc.target/arm/neon/vld1_dupp64: Likewise.
* gcc.target/arm/neon/vld1_lanep64: Likewise.
* gcc.target/arm/neon/vld1p64: Likewise.
* gcc.target/arm/neon/vld2_dupp64: Likewise.
* gcc.target/arm/neon/vld2p64: Likewise.
* gcc.target/arm/neon/vld3_dupp64: Likewise.
* gcc.target/arm/neon/vld3p64: Likewise.
* gcc.target/arm/neon/vld4_dupp64: Likewise.
* gcc.target/arm/neon/vld4p64: Likewise.
* gcc.target/arm/neon/vreinterpretQf32_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQf32_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_f32: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_p16: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_p8: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_s16: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_s32: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_s64: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_s8: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_u16: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_u32: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_u64: Likewise.
* gcc.target/arm/neon/vreinterpretQp128_u8: Likewise.
* gcc.target/arm/neon/vreinterpretQp16_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQp16_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_f32: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_p16: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_p8: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_s16: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_s32: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_s64: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_s8: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_u16: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_u32: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_u64: Likewise.
* gcc.target/arm/neon/vreinterpretQp64_u8: Likewise.
* gcc.target/arm/neon/vreinterpretQp8_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQp8_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQs16_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQs16_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQs32_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQs32_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQs64_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQs64_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQs8_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQs8_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQu16_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQu16_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQu32_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQu32_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQu64_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQu64_p64: Likewise.
* gcc.target/arm/neon/vreinterpretQu8_p128: Likewise.
* gcc.target/arm/neon/vreinterpretQu8_p64: Likewise.
* gcc.target/arm/neon/vreinterpretf32_p64: Likewise.
* gcc.target/arm/neon/vreinterpretp16_p64: Likewise.
* gcc.target/arm/neon/vreinterpretp64_f32: Likewise.
* gcc.target/arm/neon/vreinterpretp64_p16: Likewise.
* gcc.target/arm/neon/vreinterpretp64_p8: Likewise.
* gcc.target/arm/neon/vreinterpretp64_s16: Likewise.
* gcc.target/arm/neon/vreinterpretp64_s32: Likewise.
* gcc.target/arm/neon/vreinterpretp64_s64: Likewise.
* gcc.target/arm/neon/vreinterpretp64_s8: Likewise.
* gcc.target/arm/neon/vreinterpretp64_u16: Likewise.
* gcc.target/arm/neon/vreinterpretp64_u32: Likewise.
* gcc.target/arm/neon/vreinterpretp64_u64: Likewise.
* gcc.target/arm/neon/vreinterpretp64_u8: Likewise.
* gcc.target/arm/neon/vreinterpretp8_p64: Likewise.
* gcc.target/arm/neon/vreinterprets16_p64: Likewise.
* gcc.target/arm/neon/vreinterprets32_p64: Likewise.
* gcc.target/arm/neon/vreinterprets64_p64: Likewise.
* gcc.target/arm/neon/vreinterprets8_p64: Likewise.
* gcc.target/arm/neon/vreinterpretu16_p64: Likewise.
* gcc.target/arm/neon/vreinterpretu32_p64: Likewise.
* gcc.target/arm/neon/vreinterpretu64_p64: Likewise.
* gcc.target/arm/neon/vreinterpretu8_p64: Likewise.
* gcc.target/arm/neon/vsliQ_np64: Likewise.
* gcc.target/arm/neon/vsli_np64: Likewise.
* gcc.target/arm/neon/vsriQ_np64: Likewise.
* gcc.target/arm/neon/vsri_np64: Likewise.
* gcc.target/arm/neon/vst1Q_lanep64: Likewise.
* gcc.target/arm/neon/vst1Qp64: Likewise.
* gcc.target/arm/neon/vst1_lanep64: Likewise.
* gcc.target/arm/neon/vst1p64: Likewise.
* gcc.target/arm/neon/vst2p64: Likewise.
* gcc.target/arm/neon/vst3p64: Likewise.
* gcc.target/arm/neon/vst4p64: Likewise.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206128
2013-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* lib/target-supports.exp (add_options_for_arm_crc): New procedure.
(check_effective_target_arm_crc_ok_nocache): Likewise.
(check_effective_target_arm_crc_ok): Likewise.
* gcc.target/arm/acle/: New directory.
* gcc.target/arm/acle/acle.exp: New.
* gcc.target/arm/acle/crc32b.c: New test.
* gcc.target/arm/acle/crc32h.c: Likewise.
* gcc.target/arm/acle/crc32w.c: Likewise.
* gcc.target/arm/acle/crc32d.c: Likewise.
* gcc.target/arm/acle/crc32cb.c: Likewise.
* gcc.target/arm/acle/crc32ch.c: Likewise.
* gcc.target/arm/acle/crc32cw.c: Likewise.
* gcc.target/arm/acle/crc32cd.c: Likewise.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206120
2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* gcc.target/aarch64/pmull_1.c: New.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206119
2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* gcc.target/aarch64/sha256_1.c: New.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206118
2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* gcc.target/aarch64/sha1_1.c: New.
2014-02-10 Michael Collison <michael.collison@linaro.org>
Backport from trunk r206117
2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* gcc.target/aarch64/aes_1.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@207655 138bc75d-0d04-0410-961f-82ee72b054a4
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Backport from trunk r202875,202980.
2013-09-24 Xinliang David Li <davidxl@google.com>
* tree-vect-data-refs.c (vect_enhance_data_refs_alignment):
Check max peel iterations parameter.
* param.def: New parameter.
* doc/invoke.texi: Document New parameter.
2013-09-27 Xinliang David Li <davidxl@google.com>
* opts.c (finish_options): Adjust parameters
according to vect cost model.
(common_handle_option): Set dynamic vect cost
model for FDO.
targhooks.c (default_add_stmt_cost): Compute stmt cost
unconditionally.
* tree-vect-loop.c (vect_estimate_min_profitable_iters):
Use helper function.
* tree-vectorizer.h (unlimited_cost_model): New function.
* tree-vect-slp.c (vect_slp_analyze_bb_1): Use helper function.
* tree-vect-data-refs.c (vect_peeling_hash_insert): Use helper
function.
(vect_enhance_data_refs_alignment): Ditto.
* flag-types.h: New enum.
* common/config/i386/i386-common.c (ix86_option_init_struct):
No need to initialize vect_cost_model flag.
* config/i386/i386.c (ix86_add_stmt_cost): Compute stmt cost
unconditionally.
2014-02-01 Christophe Lyon <christophe.lyon@linaro.org>
Backport from trunk r203057.
2013-10-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR tree-optimization/58556
* gcc.dg/tree-ssa/gen-vect-26.c: Use dynamic vector cost model.
* gcc.dg/tree-ssa/gen-vect-28.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@207631 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@207552 138bc75d-0d04-0410-961f-82ee72b054a4
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gcc/
Backport from trunk r200103
2013-06-15 Jeff Law <law@redhat.com>
* gimple.h (gimple_can_coalesce_p): Prototype.
* tree-ssa-coalesce.c (gimple_can_coalesce_p): New function.
(create_outofssa_var_map, coalesce_partitions): Use it.
* tree-ssa-uncprop.c (uncprop_into_successor_phis): Similarly.
* tree-ssa-live.c (var_map_base_init): Use TYPE_CANONICAL
if it's available.
gcc/testsuite/
Backport from trunk r205509 and r200103
2013-11-29 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* gcc.target/arm/lp1243022.c: Skip target arm-neon.
Backport mainline r200103
2013-06-15 Jeff Law <law@redhat.com>
* gcc.dg/tree-ssa/coalesce-1.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@206909 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@206884 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@206882 138bc75d-0d04-0410-961f-82ee72b054a4
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Linaro local patch for armv4t multilib support.
* gcc/config/arm/t-mlibs: New file.
* config.gcc: Add t-mlibs.
* incpath.c (add_standard_paths): Try multilib path first.
* gcc.c (for_each_path): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@206704 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@206579 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@206343 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@206341 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@205960 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@205893 138bc75d-0d04-0410-961f-82ee72b054a4
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Backport from trunk r203774
2013-10-17 Michael Hudson-Doyle <michael.hudson@linaro.org>
* libatomic/configure.tgt (aarch64*): Remove code preventing
build.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@205747 138bc75d-0d04-0410-961f-82ee72b054a4
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