Age | Commit message (Collapse) | Author |
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Subject: [AArch64] Add missing copyright and build dependency for aarch64-simd-builtins.def
gcc/
* config/aarch64/aarch64-simd-builtins.def: Add copyright header.
* config/aarch64/t-aarch64
(aarch64-builtins.o): Depend on aarch64-simd-builtins.def.
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[AArch64-4.7] Backport: Fix g++.dg/abi/aarch64_guard1.C
gcc/testsuite/
* g++.dg/abi/aarch64_guard1.C: Add -fno-section-anchors.
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[AArch64-4.7] Backport: Implement section anchors
gcc/
* common/config/aarch64/aarch64-common.c
(aarch_option_optimization_table): New.
(TARGET_OPTION_OPTIMIZATION_TABLE): Define.
* gcc/config/aarch64/aarch64-elf.h (ASM_OUTPUT_DEF): New definition.
* gcc/config/aarch64/aarch64.c (TARGET_MIN_ANCHOR_OFFSET): Define.
(TARGET_MAX_ANCHOR_OFFSET): Likewise.
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[AARCH64-4.7] Backport: Fix warning in aarch64.md
gcc/
* config/aarch64/aarch64.md (insv_imm<mode>): Add modes
for source operands.
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[AARCH64-4.7] Fix warning - Mixed code and declarations in aarch64_simd_const_bounds.
gcc/
* config/aarch64/aarch64.c
(aarch64_simd_const_bounds): Move declaration of 'lane' above code.
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[AARCH64-4.7] Fix warning - aarch64_trampoline_init passes the wrong type to emit_library_call.
gcc/
* config/aarch64/aarch64.c
(aarch64_trampoline_init): Pass 'LCT_NORMAL' rather than '0'
to emit_library_call.
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[AARCH64-4.7] Fix warning - aarch64_legitimize_reload_address passes the
wrong type to push_reload.
gcc/
* config/aarch64/aarch64.c
(aarch64_legitimize_reload_address): Cast 'type' before
passing to push_reload.
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[AARCH64-4.7] Fix warning - aarch64_add_constant mixed code and declarations.
gcc/
* config/aarch64/aarch64.c
(aarch64_add_constant): Move declaration of 'shift' above code.
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[AARCH64-4.7] Fix warning - Initialise generic_tunings.
gcc/
* config/aarch64/aarch64.c (generic_tunings): Initialise.
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Added test case that tests the implementation of TARGET_FIXED_CONDITION_CODE_REGS
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Back port from mainline implementaion of target hook TARGET_FIXED_CONDITION_CODE_REGS to optimize cmp for some cases
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2013-01-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Separate sq<r>dmulh_lane
entries into lane and laneq entries.
* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_lane<mode>): Remove
AdvSIMD scalar modes.
(aarch64_sq<r>dmulh_laneq<mode>): New.
(aarch64_sq<r>dmulh_lane<mode>): New RTL pattern for Scalar AdvSIMD
modes.
* config/aarch64/arm_neon.h: Fix all the vq<r>dmulh_lane* intrinsics'
builtin implementations to relfect changes in RTL in aarch64-simd.md.
* config/aarch64/iterators.md (VCOND): New.
(VCONQ): New.
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[AArch64-4.7] Backport: Fix unordered comparisons to floating-point vcond.
gcc/
* config/aarch64/aarch64-simd.md
(aarch64_vcond_internal<mode>): Handle unordered cases.
* config/aarch64/iterators.md (v_cmp_result): New.
gcc/testsuite/
* gcc.target/aarch64/vect-fcm-gt-f.c: Change expected output.
* gcc.target/aarch64/vect-fcm-gt-d.c: Likewise.
* gcc.target/aarch64/vect-fcm-ge-f.c: Likewise.
* gcc.target/aarch64/vect-fcm-ge-d.c: Likewise.
* gcc.target/aarch64/vect-fcm-eq-f.c: Likewise.
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[AArch64-4.7] Backport: Add support for floating-point vcond.
gcc/
* config/aarch64/aarch64-simd.md
(aarch64_simd_bsl<mode>_internal): Add floating-point modes.
(aarch64_simd_bsl): Likewise.
(aarch64_vcond_internal<mode>): Likewise.
(vcond<mode><mode>): Likewise.
(aarch64_cm<cmp><mode>): Fix constraints, add new modes.
* config/aarch64/iterators.md (V_cmp_result): Add V2DF.
gcc/testsuite/
* gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c: New.
* gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c: Likewise.
* gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c: Likewise.
* gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c: Likewise.
* gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c: Likewise.
* gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c: Likewise.
* gcc/testsuite/gcc.target/aarch64/vect-fcm.x: Likewise.
* gcc/testsuite/lib/target-supports.exp
(check_effective_target_vect_cond): Enable for AArch64.
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2013-01-18 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/arm_neon.h: Map scalar types to standard types.
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Moved change logs of backported changes to ChangeLog.aarch64 in libgcc.
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2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Cast the
results of (dcache_lsize - 1) and (icache_lsize - 1) to the type
__UINTPTR_TYPE__; also cast 'base' to the same type before the
alignment operation.
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[AARCH64] Fix __clear_cache.
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2013-01-14 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): New.
* config/aarch64/iterators.md (VALLDI): New.
testsuite/
* gcc.target/aarch64/aarch64/vect-ld1r-compile-fp.c: New.
* gcc.target/aarch64/vect-ld1r-compile.c: New.
* gcc.target/aarch64/vect-ld1r-fp.c: New.
* gcc.target/aarch64/vect-ld1r.c: New.
* gcc.target/aarch64/vect-ld1r.x: New.
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[AARCH64-4.7] Backport: Fix support for vectorization over sqrt (), sqrtf ().
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Handle sqrt, sqrtf.
gcc/testsuite/
* gcc.target/aarch64/vsqrt.c (test_square_root_v2sf): Use
endian-safe float pool loading.
(test_square_root_v4sf): Likewise.
(test_square_root_v2df): Likewise.
* lib/target-supports.exp
(check_effective_target_vect_call_sqrtf): Add AArch64.
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* config/aarch64/aarch64.c (aarch64_print_operand): Replace %r
in asm_fprintf with reg_names.
(aarch64_print_operand_address): Likewise.
(aarch64_return_addr): Likewise.
* config/aarch64/aarch64.h (ASM_FPRINTF_EXTENSIONS): Remove.
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2013-01-08 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (vec_init<mode>): New.
* config/aarch64/aarch64-protos.h (aarch64_expand_vector_init): Declare.
* config/aarch64/aarch64.c (aarch64_simd_dup_constant,
aarch64_simd_make_constant, aarch64_expand_vector_init): New.
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2013-01-08 Tejas Belagod <tejas.belagod@arm.com>
* gcc.target/aarch64/vect-mull-compile.c: Explicitly scan for
instructions generated instead of number of occurances.
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2013-01-08 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>,
aarch64_simd_vec_<su>mult_hi_<mode>): Separate instruction and operand
with tab instead of space.
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[AARCH64-4.7] Backport: Make argument of ld1 intrinsics const.
gcc/
2013-01-08 James Greenhalgh <james.greenhalgh@arm.com>
Backport from mainline.
2013-01-07 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/arm_neon.h (vld1_dup_*): Make argument const.
(vld1q_dup_*): Likewise.
(vld1_*): Likewise.
(vld1q_*): Likewise.
(vld1_lane_*): Likewise.
(vld1q_lane_*): Likewise.
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[AARCH64-4.7] Backport: Add support for vector and scalar floating-point immediate loads.
gcc/
* config/aarch64/aarch64-protos.h
(aarch64_const_double_zero_rtx_p): Rename to...
(aarch64_float_const_zero_rtx_p): ...this.
(aarch64_float_const_representable_p): New.
(aarch64_output_simd_mov_immediate): Likewise.
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Refactor
move immediate case.
* config/aarch64/aarch64.c
(aarch64_const_double_zero_rtx_p): Rename to...
(aarch64_float_const_zero_rtx_p): ...this.
(aarch64_print_operand): Allow printing of new constants.
(aarch64_valid_floating_const): New.
(aarch64_legitimate_constant_p): Check for valid floating-point
constants.
(aarch64_simd_valid_immediate): Likewise.
(aarch64_vect_float_const_representable_p): New.
(aarch64_float_const_representable_p): Likewise.
(aarch64_simd_imm_zero_p): Also allow for floating-point 0.0.
(aarch64_output_simd_mov_immediate): New.
* config/aarch64/aarch64.md (*movsf_aarch64): Add new alternative.
(*movdf_aarch64): Likewise.
* config/aarch64/constraints.md (Ufc): New.
(Y): call aarch64_float_const_zero_rtx.
* config/aarch64/predicates.md (aarch64_fp_compare_operand): New.
gcc/testsuite/
* gcc.target/aarch64/fmovd.c: New.
* gcc.target/aarch64/fmovf.c: Likewise.
* gcc.target/aarch64/fmovd-zero.c: Likewise.
* gcc.target/aarch64/fmovf-zero.c: Likewise.
* gcc.target/aarch64/vect-fmovd.c: Likewise.
* gcc.target/aarch64/vect-fmovf.c: Likewise.
* gcc.target/aarch64/vect-fmovd-zero.c: Likewise.
* gcc.target/aarch64/vect-fmovf-zero.c: Likewise.
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2013-01-07 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vmovn_high_is16, vmovn_high_s32,
vmovn_high_s64, vmovn_high_u16, vmovn_high_u32, vmovn_high_u64,
vqmovn_high_s16, vqmovn_high_s32, vqmovn_high_s64, vqmovn_high_u16,
vqmovn_high_u32, vqmovn_high_u64, vqmovun_high_s16, vqmovun_high_s32,
vqmovun_high_s64): Fix source operand number and update copyright.
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Backport from mainline r193508
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