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From-SVN: r258522
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From-SVN: r257048
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stage 2: implementation of k-arity promotion/reduction in the series "Improving
effectiveness and generality of autovectorization using unified representation".
The permute nodes within primitive reorder tree(PRT) generated from input
program can have any arity depending upon stride of accesses. However, the
target cannot have instructions to support all arities. Hence, we need to
promote or reduce the arity of PRT to enable successful tree tiling.
In classic autovectorization, if vectorization stride > 2, arity reduction is
performed by generating cascaded extract and interleave instructions as
described by "Auto-vectorization of Interleaved Data for SIMD" by D. Nuzman,
I. Rosen and A. Zaks.
Moreover, to enable SLP across loop, "Loop-aware SLP in GCC" by D. Nuzman,
I. Rosen and A. Zaks unrolls loop till stride = vector size.
k-arity reduction/promotion algorithm makes use of modulo arithmetic to generate
PRT of desired arity for both above-mentioned cases.
Single ILV node of arity k can be reduced into cascaded ILV nodes with single
node of arity m with children of arity k/m such that ith child of original ILV
node becomes floor (i/m) th child of (i%m) th child of new parent.
Single EXTR node with k parts and i selector can be reduced into cascaded EXTR
nodes such that parent EXTR node has m parts and i/(k/m) selection on child EXTR
node with k/m parts and i % (k/m) selection.
Similarly, loop unrolling to get desired arity m can be represented as arity
promotion from k to m.
Single ILV node of arity k can be promoted to single ILV node of arity m by
adding extraction with m/k parts and selection i/k of i%k the child of original
tree as ith child of new ILV node.
To enable loop-aware SLP, we first promote arity of input PRT to maximum vector
size permissible on the architecture. This can have impact on vector code size,
though performance will be the same. To eliminate redundant ILV and EXTR
operations, thereby undoing unneccessary unrolling, we can perform unity
reduction optimization:
- EXTR_m,x (ILV_M(S1, S2, ... Sm)) => Sx
- ILV_m (EXTR_0(S), EXTR_1(S),...EXTR_m-1(S)) => S
Later we apply arity promotion reduction algorithm on the output tree to get tree
with desired arity. For now, we are supporting target arity = 2, as most of the
architectures have support for that. However, the code can be extended for
additional arity supports as well.
We have also implemented unity reduction optimization which eliminates redundant
ILV and EXTR nodes thereby undoing unneccessary unrolling - which can bloat up
the code size otherwise.
From-SVN: r246610
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From-SVN: r245428
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From-SVN: r245416
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From-SVN: r238425
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Current GCC framework does not give complete overview of the loop to be vectorized ...
Add new pass to perform autovectorization using unified representation - Current
GCC framework does not give complete overview of the loop to be vectorized : it
either breaks the loop across body, or across iterations. Because of which these
data structures can not be reused for our approach which gathers all the
information of loop body at one place using primitive permute operations. Hence,
define new data structures and populate them.
Add support for vectorization of LOAD/STORE instructions
a. Create permute order tree for the loop with LOAD and STORE instructions
for single or multi-dimensional arrays, aggregates within nested loops.
This change adds new pass to perform autovectorization using unified
representation, defines new data structures to cater to this requirement and
creates primitive reorder tree for LOAD/STORE instructions within the loop.
The whole loop is represented using the ITER_NODE, which have information about
- The preparatory statements for vectorization to be executed before entering
the loop (like initialization of vectors, prepping for reduction operations,
peeling etc.)
- Vectorizable loop body represented as PRIMOP_TREE (primitive reordering tree)
- Final statements (For peeling, variable loop bound, COLLAPSE operation for
reduction etc.)
- Other loop attributes (loop bound, peeling needed, dependences, etc.)
Memory accesses within a loop have definite repetitive pattern which can be
captured using primitive permute operators which can be used to determine
desired permute order for the vector computations. The PRIMOP_TREE is AST which
records all computations and permutations required to store destination vector
into continuous memory at the end of all iterations of the loop. It can have
INTERLEAVE, CONCAT, EXTRACT, SPLIT, ITER or any compute operation as
intermediate node. Leaf nodes can either be memory reference, constant or vector
of loop invariants. Depending upon the operation, PRIMOP_TREE holds appropriate
information about the statement within the loop which is necessary for
vectorization.
At this stage, these data structures are populated by gathering all the
information of the loop, statements within the loop and correlation of the
statements within the loop. Moreover the loop body is analyzed to check if
vectorization of each statement is possible. One has to note however that this
analysis phase will give worst-case estimate of instruction selection, as it
checks if specific named pattern is defined in .md for the target. It not
necessarily give optimal cover which is aim of the transformation phase using
tree tiling algorithm - and can be invoked only once the loop body is
represented using primitive reoder tree.
At this stage, the focus is to create permute order tree for the loop with LOAD
and STORE instructions only. The code we intend to compile is of the form
FOR(i = 0; i < N; i + +)
{
stmt 1 : D[k ∗ i + d 1 ] =S 1 [k ∗ i + c 11 ]
stmt 2 : D[k ∗ i + d 2 ] =S 1 [k ∗ i + c 21 ]
...
stmt k : D[k ∗ i + d k ] =S 1 [k ∗ i + c k 1 ]
}
Here we are assuming that any data reference can be represented using base + k *
index + offset (The data structure struct data_reference from GCC is used
currently for this purpose). If not, the address is normalized to convert to
such representation.
From-SVN: r238205
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PR middle-end/71606
* fold-const.c (fold_convertible_p): As COMPLEX_TYPE
folding produces SAVE_EXPRs, thus return false for the type.
* gcc.dg/torture/pr71606.c: New test.
From-SVN: r238157
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2016-07-07 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR fortran/71764
* trans-expr.c (gfc_trans_structure_assign): Remove assert.
* gfortran.dg/pr71764.f90: New test.
From-SVN: r238156
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From-SVN: r238155
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pointer to function members)
PR c++/70869
PR c++/71054
* cp-gimplify.c (cp_genericize_r): For DECL_EXPR for non-static
artificial vars, genericize their initializers.
* g++.dg/cpp0x/pr70869.C: New test.
* g++.dg/cpp0x/pr71054.C: New test.
Co-Authored-By: Kai Tietz <ktietz70@googlemail.com>
From-SVN: r238124
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From-SVN: r238122
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* doc/xml/manual/status_cxx2014.xml: Update LFTS status table.
* doc/html/*: Regenerate.
From-SVN: r238120
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2016-07-07 Ed Schonberg <schonberg@adacore.com>
* exp_ch6.adb (Expand_Internal_Init_Call): Subsidiary procedure
to Expand_Protected_ Subprogram_Call, to handle properly a
call to a protected function that provides the initialization
expression for a private component of the same protected type.
* sem_ch9.adb (Analyze_Protected_Definition): Layout must be
applied to itypes generated for a private operation of a protected
type that has a formal of an anonymous access to subprogram,
because these itypes have no freeze nodes and are frozen in place.
* sem_ch4.adb (Analyze_Selected_Component): If prefix is a
protected type and it is not a current instance, do not examine
the first private component of the type.
2016-07-07 Arnaud Charlet <charlet@adacore.com>
* exp_imgv.adb, g-dynhta.adb, s-regexp.adb, s-fatgen.adb, s-poosiz.adb:
Minor removal of extra whitespace.
* einfo.ads: minor removal of repeated "as" in comment
2016-07-07 Vadim Godunko <godunko@adacore.com>
* adaint.c: Complete previous change.
From-SVN: r238117
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2016-07-07 Vadim Godunko <godunko@adacore.com>
* adainit.h, adainit.c (__gnat_is_read_accessible_file): New
subprogram.
(__gnat_is_write_accessible_file): New subprogram.
* s-os_lib.ads, s-os_lib.adb (Is_Read_Accessible_File): New subprogram.
(Is_Write_Accessible_File): New subprogram.
2016-07-07 Justin Squirek <squirek@adacore.com>
* sem_ch12.adb (Install_Body): Minor refactoring in the order
of local functions.
(In_Same_Scope): Change loop condition to be more expressive.
From-SVN: r238116
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2016-07-07 Gary Dismukes <dismukes@adacore.com>
* sem_ch3.adb, sem_prag.adb, sem_prag.ads, prj-ext.adb, freeze.adb,
sem_attr.adb: Minor reformatting, fix typos.
2016-07-07 Justin Squirek <squirek@adacore.com>
* sem_ch12.adb (In_Same_Scope): Created this function to check
a generic package definition against an instantiation for scope
dependancies.
(Install_Body): Add function In_Same_Scope and
amend conditional in charge of delaying the package instance.
(Is_In_Main_Unit): Add guard to check if parent is present in
assignment of Current_Unit.
From-SVN: r238115
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* gfortran.dg/do_1.f90: Remove a corner case that triggers
an undefined behavior.
* gfortran.dg/do_3.F90: Likewise.
* gfortran.dg/do_check_11.f90: New test.
* gfortran.dg/do_check_12.f90: New test.
* gfortran.dg/do_corner_warn.f90: New test.
* lang.opt (Wundefined-do-loop): New option.
* resolve.c (gfc_resolve_iterator): Warn for Wundefined-do-loop.
(gfc_trans_simple_do): Generate a c-style loop.
(gfc_trans_do): Fix GNU coding style.
* invoke.texi: Mention the new warning.
From-SVN: r238114
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comments and formatting.
2016-07-07 Eric Botcazou <ebotcazou@adacore.com>
* sem_ch6.adb (Analyze_Subprogram_Body_Helper): Remove redundant test,
adjust comments and formatting.
* sem_prag.adb (Inlining_Not_Possible): Do not test Front_End_Inlining
here but...
(Make_Inline): ...here before calling Inlining_Not_Possible instead.
(Set_Inline_Flags): Remove useless test.
(Analyze_Pragma) <Pragma_Inline>: Add comment about -gnatn switch.
From-SVN: r238113
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* trans-stmt.c (gfc_trans_do): Add expect builtin for DO
loops with step bigger than +-1.
* gfortran.dg/predict-1.f90: Ammend the test.
* gfortran.dg/predict-2.f90: Likewise.
From-SVN: r238112
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2016-07-07 Ed Schonberg <schonberg@adacore.com>
* sem_prag.ads, sem_prag.adb (Build_Classwide_Expression): Include
overridden operation as parameter, in order to map formals of
the overridden and overring operation properly prior to rewriting
the inherited condition.
* freeze.adb (Check_Inherited_Cnonditions): Change call to
Build_Class_Wide_Expression accordingly. In Spark_Mode, add
call to analyze the contract of the parent operation, prior to
mapping formals between operations.
2016-07-07 Arnaud Charlet <charlet@adacore.com>
* adabkend.adb (Scan_Back_End_Switches): Ignore -o/-G switches
as done in back_end.adb.
(Scan_Compiler_Args): Remove special case for CodePeer/SPARK, no longer
needed, and prevents proper handling of multi-unit sources.
2016-07-07 Thomas Quinot <quinot@adacore.com>
* g-sechas.adb, g-sechas.ads (GNAT.Secure_Hashes.H): Add Hash_Stream
type with Write primitive calling Update on the underlying context
(and dummy Read primitive raising P_E).
2016-07-07 Thomas Quinot <quinot@adacore.com>
* sem_ch13.adb: Minor reformatting.
From-SVN: r238111
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2016-07-07 Thomas Quinot <quinot@adacore.com>
* g-socket.ads: Document performance consideration for stream
wrapper.
2016-07-07 Arnaud Charlet <charlet@adacore.com>
* osint-c.ads (Set_File_Name): Clarify spec.
From-SVN: r238110
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2016-07-07 Eric Botcazou <ebotcazou@adacore.com>
* freeze.adb: Reenable code.
From-SVN: r238109
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From-SVN: r238107
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subprograms.
2016-07-07 Yannick Moy <moy@adacore.com>
* sem_ch6.adb (Process_Formals): Set ghost flag
on formal entities of ghost subprograms.
* ghost.adb (Check_Ghost_Context.Is_OK_Ghost_Context): Accept ghost
entities in use type clauses.
From-SVN: r238106
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* file-find.c (remove_prefix): New function.
* file-find.h (remove_prefix): Declare the function.
* gcc-ar.c (main): Skip a folder of the wrapper if
a wrapped binary would point to the same file.
From-SVN: r238089
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* tree-scalar-evolution.c (iv_can_overflow_p): export.
* tree-scalar-evolution.h (iv_can_overflow_p): Declare.
* tree-ssa-loop-ivopts.c (alloc_iv): Use it.
From-SVN: r238088
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gcc/
PR ipa/71624
* ipa-inline-analysis.c (compute_inline_parameters): Set
local.can_change_signature to false for intrumentation
thunk callees.
gcc/testsuite/
PR ipa/71624
* g++.dg/pr71624.C: New test.
From-SVN: r238086
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2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm.h (TARGET_USE_MOVT): Check MOVT/MOVW availability
with TARGET_HAVE_MOVT.
(TARGET_HAVE_MOVT): Define.
* config/arm/arm.c (const_ok_for_op): Check MOVT/MOVW
availability with TARGET_HAVE_MOVT.
* config/arm/arm.md (arm_movt): Use TARGET_HAVE_MOVT to check MOVT
availability.
(addsi splitter): Use TARGET_THUMB && TARGET_HAVE_MOVT rather than
TARGET_THUMB2.
(symbol_refs movsi splitter): Remove TARGET_32BIT check.
(arm_movtas_ze): Use TARGET_HAVE_MOVT to check MOVT availability.
* config/arm/constraints.md (define_constraint "j"): Use
TARGET_HAVE_MOVT to check MOVT availability.
From-SVN: r238083
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2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm-protos.h: Reindent FL_FOR_* macro definitions.
From-SVN: r238082
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2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm-arches.def (armv8-m.base): Define new architecture.
(armv8-m.main): Likewise.
(armv8-m.main+dsp): Likewise.
* config/arm/arm-protos.h (FL_FOR_ARCH8M_BASE): Define.
(FL_FOR_ARCH8M_MAIN): Likewise.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/bpabi.h: Add armv8-m.base, armv8-m.main and
armv8-m.main+dsp to BE8_LINK_SPEC.
* config/arm/arm.h (TARGET_HAVE_LDACQ): Exclude ARMv8-M.
(enum base_architecture): Add BASE_ARCH_8M_BASE and BASE_ARCH_8M_MAIN.
* config/arm/arm.c (arm_arch_name): Increase size to work with ARMv8-M
Baseline and Mainline.
(arm_option_override_internal): Also disable arm_restrict_it when
!arm_arch_notm. Update comment for -munaligned-access to also cover
ARMv8-M Baseline.
(arm_file_start): Increase buffer size for printing architecture name.
* doc/invoke.texi: Document architectures armv8-m.base, armv8-m.main
and armv8-m.main+dsp.
(mno-unaligned-access): Clarify that this is disabled by default for
ARMv8-M Baseline architectures as well.
gcc/testsuite/
* lib/target-supports.exp: Generate add_options_for_arm_arch_FUNC and
check_effective_target_arm_arch_FUNC_multilib for ARMv8-M Baseline and
ARMv8-M Mainline architectures.
libgcc/
* config/arm/lib1funcs.S (__ARM_ARCH__): Define to 8 for ARMv8-M.
From-SVN: r238081
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than for a fixed list of...
2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
libgcc/
* config/arm/lib1funcs.S (HAVE_ARM_CLZ): Define for ARMv6* or later
and ARMv5t* rather than for a fixed list of architectures.
From-SVN: r238080
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prevent...
2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to
decide whether to prevent some libgcc routines being included for some
multilibs rather than __ARM_ARCH_6M__ and add comment to indicate the
link between this condition and the one in
libgcc/config/arm/lib1func.S.
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_arm_cortex_m): Use
__ARM_ARCH_ISA_ARM to test for Cortex-M devices.
libgcc/
* config/arm/bpabi-v6m.S: Clarify what architectures is the
implementation suitable for.
* config/arm/lib1funcs.S (__prefer_thumb__): Define among other cases
for all Thumb-1 only targets.
(NOT_ISA_TARGET_32BIT): Define for Thumb-1 only targets.
(THUMB_LDIV0): Test for NOT_ISA_TARGET_32BIT rather than
__ARM_ARCH_6M__.
(EQUIV): Likewise.
(ARM_FUNC_ALIAS): Likewise.
(umodsi3): Add check to __ARM_ARCH_ISA_THUMB != 1 to guard the idiv
version.
(modsi3): Likewise.
(clzsi2): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__.
(clzdi2): Likewise.
(ctzsi2): Likewise.
(L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than
__ARM_ARCH_6M__ in guard for checking whether it is defined.
(final includes): Test for NOT_ISA_TARGET_32BIT rather than
__ARM_ARCH_6M__ and add comment to indicate the connection between
this condition and the one in gcc/config/arm/elf.h.
* config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and
__ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__.
* config/arm/t-softfp: Likewise.
From-SVN: r238079
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2016-07-07 Richard Biener <rguenther@suse.de>
* tree-ssa-pre.c: Include alias.h.
(compute_avail): If we have multiple VN_REFERENCEs with the
same hashtable entry adjust that to make it a valid replacement
for all of them with respect to alignment and aliasing
when doing insertion.
* tree-ssa-sccvn.h (vn_reference_operands_for_lookup): Declare.
* tree-ssa-sccvn.c (vn_reference_operands_for_lookup): New function.
From-SVN: r238078
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Similar to PR70098, which is about integers in floating point registers,
we can have the completely analogous problem with vector registers as well
now that we allow integers in vector registers. So, this patch solves it
in the same way. This only works for targets with direct move.
To recap: register allocation can decide to put an integer mode value in
a floating point or vector register. If that register is used in a bd*z
instruction, which is a jump instruction, reload can not do an output
reload on it (it does not do output reloads on any jump insns), so the
float or vector register will remain, and we have to allow it here or
recog will ICE. Later on we will split this to valid instructions,
including a move from that fp/vec register to an int register; it is this
move that will still fail (PR70098) if we do not have direct move enabled.
PR target/70098
PR target/71763
* config/rs6000/rs6000.md (*ctr<mode>_internal1, *ctr<mode>_internal2,
*ctr<mode>_internal5, *ctr<mode>_internal6): Add *wi to the output
constraint.
gcc/testsuite/
PR target/70098
PR target/71763
* gcc.target/powerpc/pr71763.c: New file.
From-SVN: r238076
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From-SVN: r238073
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The last target to use this was i386-interix, so since that is gone we
don't need this anymore.
libgcc/ChangeLog:
2016-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* libgcc2.c (SYMBOL__MAIN): Remove checks for
CTOR_LISTS_DEFINED_EXTERNALLY.
From-SVN: r238067
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gcc/ChangeLog:
2016-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* var-tracking.c (struct adjust_mem_data): Make side_effects a vector.
(adjust_mems): Adjust.
(adjust_insn): Likewise.
(prepare_call_arguments): Likewise.
From-SVN: r238066
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gcc/ChangeLog:
2016-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* gcse.c (struct ls_expr): Make stores field a vector.
(ldst_entry): Adjust.
(free_ldst_entry): Likewise.
(print_ldst_list): Likewise.
(compute_ld_motion_mems): Likewise.
(update_ld_motion_stores): Likewise.
From-SVN: r238065
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gcc/ChangeLog:
2016-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* gcse.c (struct ls_expr): Remove loads field.
(ldst_entry): Adjust.
(free_ldst_entry): Likewise.
(print_ldst_list): Likewise.
(compute_ld_motion_mems): Likewise.
From-SVN: r238064
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gcc/ChangeLog:
2016-07-06 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* store-motion.c (struct st_expr): Make antic_stores a vector.
(st_expr_entry): Adjust.
(free_st_expr_entry): Likewise.
(print_store_motion_mems): Likewise.
(find_moveable_store): Likewise.
(compute_store_table): Likewise.
(remove_reachable_equiv_notes): Likewise.
(replace_store_insn): Likewise.
(build_store_vectors): Likewise.
From-SVN: r238063
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* include/Makefile.am: Add any and c++17_warning.h to exported headers.
* include/Makefile.in: Likewise.
* include/std/any: New.
* testsuite/20_util/any/assign/1.cc: Likewise.
* testsuite/20_util/any/assign/2.cc: Likewise.
* testsuite/20_util/any/assign/self.cc: Likewise.
* testsuite/20_util/any/cons/1.cc: Likewise.
* testsuite/20_util/any/cons/2.cc: Likewise.
* testsuite/20_util/any/cons/aligned.cc: Likewise.
* testsuite/20_util/any/cons/nontrivial.cc: Likewise.
* testsuite/20_util/any/misc/any_cast.cc: Likewise.
* testsuite/20_util/any/misc/any_cast_neg.cc: Likewise.
* testsuite/20_util/any/misc/any_cast_no_rtti.cc: Likewise.
* testsuite/20_util/any/misc/swap.cc: Likewise.
* testsuite/20_util/any/modifiers/1.cc: Likewise.
* testsuite/20_util/any/observers/type.cc: Likewise.
* testsuite/20_util/any/typedefs.cc: Likewise.
From-SVN: r238061
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From-SVN: r238058
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Adds notes to function parameters which summarize the escape of that
parameter with respect to the function's scope.
Reviewed-on: https://go-review.googlesource.com/18443
From-SVN: r238057
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* config/arm/driver-arm.c (arm_cpu_table): Add entries for cortex-a32,
cortex-a35, cortex-a53, cortex-a57, cortex-a72, cortex-a73.
From-SVN: r238056
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64-bit mode (not in 32-bit mode))
gcc/
2016-07-06 Yuri Rumyantsev <ysrumyan@gmail.com>
PR tree-optimization/71518
* tree-vect-data-refs.c (vect_compute_data_ref_alignment): Adjust
misalign also for outer loops with negative step.
gcc/testsuite/
2016-07-06 Yuri Rumyantsev <ysrumyan@gmail.com>
PR tree-optimization/71518
* gcc.dg/pr71518.c: New test.
From-SVN: r238055
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its aspects to the internally built...
2016-07-06 Javier Miranda <miranda@adacore.com>
* sem_ch6.adb (Check_Inline_Pragma): if the subprogram has no spec
then move its aspects to the internally built subprogram spec.
From-SVN: r238052
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as ghost if needed when created.
2016-07-06 Yannick Moy <moy@adacore.com>
* sem_ch6.adb (Analyze_Expression_Function): Mark body of
expression function as ghost if needed when created.
* sem_prag.adb (Analyze_Pragma.Process_Inline.Set_Inline_Flags):
Remove special case.
From-SVN: r238051
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2016-07-06 Arnaud Charlet <charlet@adacore.com>
* lib.adb (Check_Same_Extended_Unit): Complete previous change.
* sem_intr.adb (Errint): New parameter Relaxed. Refine previous
change to only disable errors selectively.
* sem_util.adb: minor style fix in object declaration
2016-07-06 Yannick Moy <moy@adacore.com>
* sem_warn.adb (Check_Infinite_Loop_Warning.Find_Var): Special case a
call to a volatile function, so that it does not lead to a warning in
that case.
2016-07-06 Hristian Kirtchev <kirtchev@adacore.com>
* sem_ch12.adb, sem_ch4.adb, sem_ch6.adb: Minor reformatting.
2016-07-06 Hristian Kirtchev <kirtchev@adacore.com>
* gnat1drv.adb: Code clean up. Do not emit any
code generation errors when the unit is ignored Ghost.
2016-07-06 Ed Schonberg <schonberg@adacore.com>
* sem_eval.adb (Check_Non_Static_Context): If the expression
is a real literal of a floating point type that is part of a
larger expression and is not a static expression, transform it
into a machine number now so that the rest of the computation,
even if other components are static, is not evaluated with
extra precision.
2016-07-06 Javier Miranda <miranda@adacore.com>
* sem_ch13.adb (Freeze_Entity_Checks): Undo previous patch and move the
needed functionality to Analyze_Freeze_Generic_Entity.
(Analyze_Freeze_Generic_Entity): If the entity is not already frozen
and has delayed aspects then analyze them.
2016-07-06 Yannick Moy <moy@adacore.com>
* sem_prag.adb (Analyze_Pragma.Process_Inline.Set_Inline_Flags):
Special case for unanalyzed body entity of ghost expression function.
From-SVN: r238050
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Implement LWG 2451, optional<T> should 'forward' T's
implicit conversions.
* include/experimental/optional (__is_optional_impl, __is_optional):
New.
(optional()): Make constexpr and default.
(optional(_Up&&), optional(const optional<_Up>&),
optional(optional<_Up>&& __t): New.
(operator=(_Up&&)): Constrain.
(operator=(const optional<_Up>&), operator=(optional<_Up>&&)): New.
* testsuite/experimental/optional/cons/value.cc:
Add tests for the functionality added by LWG 2451.
* testsuite/experimental/optional/cons/value_neg.cc: New.
From-SVN: r238049
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This patch improves the accuracy of the Cortex-A53 integer scheduler,
resulting in performance gains across a wide range of benchmarks.
gcc/
* config/arm/cortex-a53.md: Use final_presence_set for in-order.
(cortex_a53_shift): Add mov_shift.
(cortex_a53_shift_reg): Add new reservation for register shifts.
(cortex_a53_alu): Remove bfm.
(cortex_a53_alu_shift): Add bfm, remove mov_shift.
(cortex_a53_alu_extr): Add new reservation for EXTR.
(bypasses): Improve bypass modelling.
From-SVN: r238048
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