diff options
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-tuning-flags.def | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 20 |
2 files changed, 24 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def index 048c2a3e3f7..68b5ba0ad0e 100644 --- a/gcc/config/aarch64/aarch64-tuning-flags.def +++ b/gcc/config/aarch64/aarch64-tuning-flags.def @@ -29,3 +29,8 @@ AARCH64_TUNE_ to give an enum name. */ AARCH64_EXTRA_TUNING_OPTION ("rename_fma_regs", RENAME_FMA_REGS) + +/* Don't create non-8 byte aligned load/store pair. That is if the +two load/stores are not at least 8 byte aligned don't create load/store +pairs. */ +AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 17e36f239ae..a4a34b57f0e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -687,7 +687,7 @@ static const struct tune_params thunderx_tunings = 0, /* max_case_values. */ 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) /* tune_flags. */ }; static const struct tune_params xgene1_tunings = @@ -13571,6 +13571,15 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load, if (MEM_VOLATILE_P (mem_1) || MEM_VOLATILE_P (mem_2)) return false; + /* If we have SImode and slow unaligned ldp, + check the alignment to be at least 8 byte. */ + if (mode == SImode + && (aarch64_tune_params.extra_tuning_flags + & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) + && !optimize_size + && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT) + return false; + /* Check if the addresses are in the form of [base+offset]. */ extract_base_offset_in_addr (mem_1, &base_1, &offset_1); if (base_1 == NULL_RTX || offset_1 == NULL_RTX) @@ -13730,6 +13739,15 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load, return false; } + /* If we have SImode and slow unaligned ldp, + check the alignment to be at least 8 byte. */ + if (mode == SImode + && (aarch64_tune_params.extra_tuning_flags + & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) + && !optimize_size + && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT) + return false; + if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1))) rclass_1 = FP_REGS; else |