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-rw-r--r--gcc/config/arm/arm.md11
1 files changed, 9 insertions, 2 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index d931ed45d76..829421cb07c 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -109,6 +109,11 @@
;; given instruction does not shift one of its input operands.
(define_attr "shift" "" (const_int 0))
+;; [For compatibility with AArch64 in pipeline models]
+;; Attribute that specifies whether or not the instruction touches fp
+;; registers.
+(define_attr "fp" "no,yes" (const_string "no"))
+
; Floating Point Unit. If we only have floating point emulation, then there
; is no point in scheduling the floating point insns. (Well, for best
; performance we should try and group them together).
@@ -373,7 +378,8 @@
arm926ejs,arm1020e,arm1026ejs,arm1136js,\
arm1136jfs,cortexa5,cortexa7,cortexa8,\
cortexa9,cortexa12,cortexa15,cortexa53,\
- cortexm4,cortexm7,marvell_pj4")
+ cortexm4,cortexm7,marvell_pj4,
+ xgene1")
(eq_attr "tune_cortexr4" "yes"))
(const_string "no")
(const_string "yes"))))
@@ -383,7 +389,7 @@
(and (eq_attr "fpu" "vfp")
(eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,\
cortexa8,cortexa9,cortexa53,cortexm4,\
- cortexm7,marvell_pj4")
+ cortexm7,marvell_pj4,xgene1")
(eq_attr "tune_cortexr4" "no"))
(const_string "yes")
(const_string "no"))))
@@ -412,6 +418,7 @@
(include "cortex-m4-fpu.md")
(include "vfp11.md")
(include "marvell-pj4.md")
+(include "xgene1.md")
;;---------------------------------------------------------------------------