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-rw-r--r--gcc/config/arm/arm.md325
1 files changed, 325 insertions, 0 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 59efdecefa5..f90bf1e81f0 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -543,6 +543,32 @@
(set_attr "type" "multiple")]
)
+(define_expand "addv<mode>4"
+ [(match_operand:SIDI 0 "register_operand")
+ (match_operand:SIDI 1 "register_operand")
+ (match_operand:SIDI 2 "register_operand")
+ (match_operand 3 "")]
+ "TARGET_32BIT"
+{
+ emit_insn (gen_add<mode>3_compareV (operands[0], operands[1], operands[2]));
+ arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
+
+ DONE;
+})
+
+(define_expand "uaddv<mode>4"
+ [(match_operand:SIDI 0 "register_operand")
+ (match_operand:SIDI 1 "register_operand")
+ (match_operand:SIDI 2 "register_operand")
+ (match_operand 3 "")]
+ "TARGET_32BIT"
+{
+ emit_insn (gen_add<mode>3_compareC (operands[0], operands[1], operands[2]));
+ arm_gen_unlikely_cbranch (NE, CC_Cmode, operands[3]);
+
+ DONE;
+})
+
(define_expand "addsi3"
[(set (match_operand:SI 0 "s_register_operand" "")
(plus:SI (match_operand:SI 1 "s_register_operand" "")
@@ -620,6 +646,165 @@
]
)
+(define_insn_and_split "adddi3_compareV"
+ [(set (reg:CC_V CC_REGNUM)
+ (ne:CC_V
+ (plus:TI
+ (sign_extend:TI (match_operand:DI 1 "register_operand" "r"))
+ (sign_extend:TI (match_operand:DI 2 "register_operand" "r")))
+ (sign_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
+ (set (match_operand:DI 0 "register_operand" "=&r")
+ (plus:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_32BIT"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:CC_C CC_REGNUM)
+ (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
+ (match_dup 1)))
+ (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
+ (parallel [(set (reg:CC_V CC_REGNUM)
+ (ne:CC_V
+ (plus:DI (plus:DI
+ (sign_extend:DI (match_dup 4))
+ (sign_extend:DI (match_dup 5)))
+ (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
+ (plus:DI (sign_extend:DI
+ (plus:SI (match_dup 4) (match_dup 5)))
+ (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
+ (set (match_dup 3) (plus:SI (plus:SI
+ (match_dup 4) (match_dup 5))
+ (ltu:SI (reg:CC_C CC_REGNUM)
+ (const_int 0))))])]
+ "
+ {
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[4] = gen_highpart (SImode, operands[1]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[5] = gen_highpart (SImode, operands[2]);
+ operands[2] = gen_lowpart (SImode, operands[2]);
+ }"
+ [(set_attr "conds" "set")
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
+)
+
+(define_insn "addsi3_compareV"
+ [(set (reg:CC_V CC_REGNUM)
+ (ne:CC_V
+ (plus:DI
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
+ (sign_extend:DI (plus:SI (match_dup 1) (match_dup 2)))))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_dup 1) (match_dup 2)))]
+ "TARGET_32BIT"
+ "adds%?\\t%0, %1, %2"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_sreg")]
+)
+
+(define_insn "*addsi3_compareV_upper"
+ [(set (reg:CC_V CC_REGNUM)
+ (ne:CC_V
+ (plus:DI
+ (plus:DI
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
+ (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
+ (plus:DI (sign_extend:DI
+ (plus:SI (match_dup 1) (match_dup 2)))
+ (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI
+ (plus:SI (match_dup 1) (match_dup 2))
+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+ "TARGET_32BIT"
+ "adcs%?\\t%0, %1, %2"
+ [(set_attr "conds" "set")
+ (set_attr "type" "adcs_reg")]
+)
+
+(define_insn_and_split "adddi3_compareC"
+ [(set (reg:CC_C CC_REGNUM)
+ (ne:CC_C
+ (plus:TI
+ (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
+ (zero_extend:TI (match_operand:DI 2 "register_operand" "r")))
+ (zero_extend:TI (plus:DI (match_dup 1) (match_dup 2)))))
+ (set (match_operand:DI 0 "register_operand" "=&r")
+ (plus:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_32BIT"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:CC_C CC_REGNUM)
+ (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
+ (match_dup 1)))
+ (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
+ (parallel [(set (reg:CC_C CC_REGNUM)
+ (ne:CC_C
+ (plus:DI (plus:DI
+ (zero_extend:DI (match_dup 4))
+ (zero_extend:DI (match_dup 5)))
+ (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
+ (plus:DI (zero_extend:DI
+ (plus:SI (match_dup 4) (match_dup 5)))
+ (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
+ (set (match_dup 3) (plus:SI
+ (plus:SI (match_dup 4) (match_dup 5))
+ (ltu:SI (reg:CC_C CC_REGNUM)
+ (const_int 0))))])]
+ "
+ {
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[4] = gen_highpart (SImode, operands[1]);
+ operands[5] = gen_highpart (SImode, operands[2]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[2] = gen_lowpart (SImode, operands[2]);
+ }"
+ [(set_attr "conds" "set")
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
+)
+
+(define_insn "*addsi3_compareC_upper"
+ [(set (reg:CC_C CC_REGNUM)
+ (ne:CC_C
+ (plus:DI
+ (plus:DI
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
+ (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))
+ (plus:DI (zero_extend:DI
+ (plus:SI (match_dup 1) (match_dup 2)))
+ (ltu:DI (reg:CC_C CC_REGNUM) (const_int 0)))))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI
+ (plus:SI (match_dup 1) (match_dup 2))
+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+ "TARGET_32BIT"
+ "adcs%?\\t%0, %1, %2"
+ [(set_attr "conds" "set")
+ (set_attr "type" "adcs_reg")]
+)
+
+(define_insn "addsi3_compareC"
+ [(set (reg:CC_C CC_REGNUM)
+ (ne:CC_C
+ (plus:DI
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
+ (zero_extend:DI
+ (plus:SI (match_dup 1) (match_dup 2)))))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_dup 1) (match_dup 2)))]
+ "TARGET_32BIT"
+ "adds%?\\t%0, %1, %2"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_sreg")]
+)
+
(define_insn "addsi3_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
@@ -869,6 +1054,75 @@
(set_attr "type" "adcs_reg")]
)
+(define_expand "subv<mode>4"
+ [(match_operand:SIDI 0 "register_operand")
+ (match_operand:SIDI 1 "register_operand")
+ (match_operand:SIDI 2 "register_operand")
+ (match_operand 3 "")]
+ "TARGET_32BIT"
+{
+ emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
+ arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
+
+ DONE;
+})
+
+(define_expand "usubv<mode>4"
+ [(match_operand:SIDI 0 "register_operand")
+ (match_operand:SIDI 1 "register_operand")
+ (match_operand:SIDI 2 "register_operand")
+ (match_operand 3 "")]
+ "TARGET_32BIT"
+{
+ emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
+ arm_gen_unlikely_cbranch (LTU, CCmode, operands[3]);
+
+ DONE;
+})
+
+(define_insn_and_split "subdi3_compare1"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC
+ (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")))
+ (set (match_operand:DI 0 "register_operand" "=&r")
+ (minus:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_32BIT"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
+ (parallel [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_dup 4) (match_dup 5)))
+ (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))])]
+ {
+ operands[3] = gen_highpart (SImode, operands[0]);
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[4] = gen_highpart (SImode, operands[1]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[5] = gen_highpart (SImode, operands[2]);
+ operands[2] = gen_lowpart (SImode, operands[2]);
+ }
+ [(set_attr "conds" "set")
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
+)
+
+(define_insn "subsi3_compare1"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC
+ (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (minus:SI (match_dup 1) (match_dup 2)))]
+ "TARGET_32BIT"
+ "subs%?\\t%0, %1, %2"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_sreg")]
+)
+
(define_insn "*subsi3_carryin"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I")
@@ -4350,6 +4604,63 @@
;; Unary arithmetic insns
+(define_expand "negvsi3"
+ [(match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "register_operand")
+ (match_operand 2 "")]
+ "TARGET_32BIT"
+{
+ emit_insn (gen_subsi3_compare (operands[0], const0_rtx, operands[1]));
+ arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
+
+ DONE;
+})
+
+(define_expand "negvdi3"
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand 2 "")]
+ "TARGET_ARM"
+{
+ emit_insn (gen_negdi2_compare (operands[0], operands[1]));
+ arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);
+
+ DONE;
+})
+
+
+(define_insn_and_split "negdi2_compare"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC
+ (const_int 0)
+ (match_operand:DI 1 "register_operand" "0,r")))
+ (set (match_operand:DI 0 "register_operand" "=r,&r")
+ (minus:DI (const_int 0) (match_dup 1)))]
+ "TARGET_ARM"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:CC CC_REGNUM)
+ (compare:CC (const_int 0) (match_dup 1)))
+ (set (match_dup 0) (minus:SI (const_int 0)
+ (match_dup 1)))])
+ (parallel [(set (reg:CC CC_REGNUM)
+ (compare:CC (const_int 0) (match_dup 3)))
+ (set (match_dup 2)
+ (minus:SI
+ (minus:SI (const_int 0) (match_dup 3))
+ (ltu:SI (reg:CC_C CC_REGNUM)
+ (const_int 0))))])]
+ {
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[3] = gen_highpart (SImode, operands[1]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ }
+ [(set_attr "conds" "set")
+ (set_attr "length" "8")
+ (set_attr "type" "multiple")]
+)
+
(define_expand "negdi2"
[(parallel
[(set (match_operand:DI 0 "s_register_operand" "")
@@ -4390,6 +4701,20 @@
(set_attr "type" "multiple")]
)
+(define_insn "*negsi2_carryin_compare"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (const_int 0)
+ (match_operand:SI 1 "s_register_operand" "r")))
+ (set (match_operand:SI 0 "s_register_operand" "=r")
+ (minus:SI (minus:SI (const_int 0)
+ (match_dup 1))
+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+ "TARGET_ARM"
+ "rscs\\t%0, %1, #0"
+ [(set_attr "conds" "set")
+ (set_attr "type" "alus_imm")]
+)
+
(define_expand "negsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
(neg:SI (match_operand:SI 1 "s_register_operand" "")))]
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 12:05:20 +0000