diff options
Diffstat (limited to 'gcc/config/arm/arm.h')
| -rw-r--r-- | gcc/config/arm/arm.h | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 3495ab857ea..c7777706781 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -816,7 +816,8 @@ extern const int arm_arch_cde_coproc_bits[]; s16-s31 S VFP variable (aka d8-d15). vfpcc Not a real register. Represents the VFP condition code flags. - vpr Used to represent MVE VPR predication. */ + vpr Used to represent MVE VPR predication. + ra_auth_code Pseudo register to save PAC. */ /* The stack backtrace structure is as follows: fp points to here: | save code pointer | [fp] @@ -857,7 +858,7 @@ extern const int arm_arch_cde_coproc_bits[]; 1,1,1,1,1,1,1,1, \ 1,1,1,1, \ /* Specials. */ \ - 1,1,1,1,1,1,1 \ + 1,1,1,1,1,1,1,1 \ } /* 1 for registers not available across function calls. @@ -887,7 +888,7 @@ extern const int arm_arch_cde_coproc_bits[]; 1,1,1,1,1,1,1,1, \ 1,1,1,1, \ /* Specials. */ \ - 1,1,1,1,1,1,1 \ + 1,1,1,1,1,1,1,1 \ } #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE @@ -1063,10 +1064,10 @@ extern const int arm_arch_cde_coproc_bits[]; && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP - + 1 APSRQ + 1 APSRGE + 1 VPR. */ + + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */ /* Intel Wireless MMX Technology registers add 16 + 4 more. */ /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ -#define FIRST_PSEUDO_REGISTER 107 +#define FIRST_PSEUDO_REGISTER 108 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) @@ -1253,12 +1254,15 @@ extern int arm_regs_in_sequence[]; CC_REGNUM, VFPCC_REGNUM, \ FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \ - APSRGE_REGNUM, VPR_REGNUM \ + APSRGE_REGNUM, VPR_REGNUM, RA_AUTH_CODE \ } #define IS_VPR_REGNUM(REGNUM) \ ((REGNUM) == VPR_REGNUM) +#define IS_PAC_Pseudo_REGNUM(REGNUM) \ + ((REGNUM) == RA_AUTH_CODE) + /* Use different register alloc ordering for Thumb. */ #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () @@ -1297,6 +1301,7 @@ enum reg_class SFP_REG, AFP_REG, VPR_REG, + PAC_REG, GENERAL_AND_VPR_REGS, ALL_REGS, LIM_REG_CLASSES @@ -1327,6 +1332,7 @@ enum reg_class "SFP_REG", \ "AFP_REG", \ "VPR_REG", \ + "PAC_REG", \ "GENERAL_AND_VPR_REGS", \ "ALL_REGS" \ } @@ -1356,6 +1362,7 @@ enum reg_class { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000800 }, /* PAC_REG. */ \ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \ { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000040F } /* ALL_REGS. */ \ } |