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-rw-r--r--gcc/config/arm/arm.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index bf5f8242ca1..7f5ddc3e7e2 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2052,6 +2052,29 @@ const struct tune_params arm_xgene1_tune =
tune_params::SCHED_AUTOPREF_OFF
};
+const struct tune_params arm_qdf24xx_tune =
+{
+ arm_9e_rtx_costs,
+ &qdf24xx_extra_costs,
+ NULL, /* Scheduler cost adjustment. */
+ arm_default_branch_cost,
+ &arm_default_vec_cost, /* Vectorizer costs. */
+ 1, /* Constant limit. */
+ 2, /* Max cond insns. */
+ 8, /* Memset max inline. */
+ 4, /* Issue rate. */
+ ARM_PREFETCH_BENEFICIAL (0, -1, 64),
+ tune_params::PREF_CONST_POOL_FALSE,
+ tune_params::PREF_LDRD_TRUE,
+ tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* Thumb. */
+ tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* ARM. */
+ tune_params::DISPARAGE_FLAGS_ALL,
+ tune_params::PREF_NEON_64_FALSE,
+ tune_params::PREF_NEON_STRINGOPS_TRUE,
+ FUSE_OPS (tune_params::FUSE_MOVW_MOVT),
+ tune_params::SCHED_AUTOPREF_FULL
+};
+
/* Branches can be dual-issued on Cortex-A5, so conditional execution is
less appealing. Set max_insns_skipped to a low value. */