gcc/

	Backport from trunk r240504.
	2016-09-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* tree.h (memmodel_from_int, memmodel_base, is_mm_relaxed,
	is_mm_consume, is_mm_acquire, is_mm_release, is_mm_acq_rel,
	is_mm_seq_cst, is_mm_sync): Move to ...
	* memmodel.h: This.  New file.
	* builtins.c: Include memmodel.h.
	* optabs.c: Likewise.
	* tsan.c: Likewise.
	* config/aarch64/aarch64.c: Likewise.
	* config/alpha/alpha.c: Likewise.
	* config/arm/arm.c: Likewise.
	* config/i386/i386.c: Likewise.
	* config/ia64/ia64.c: Likewise.
	* config/mips/mips.c: Likewise.
	* config/rs6000/rs6000.c: Likewise.
	* config/sparc/sparc.c: Likewise.
	* genconditions.c: Include memmodel.h in generated file.
	* genemit.c: Likewise.
	* genoutput.c: Likewise.
	* genpeep.c: Likewise.
	* genpreds.c: Likewise.
	* genrecog.c: Likewise.

	gcc/c-family/
	Backport from trunk r240504.
	2016-09-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* c-common.c: Include memmodel.h.

	gcc/
	Backport from trunk r241507.
	2016-10-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/constraints.md (Q constraint): Document its use for
	Thumb-1.
	(Pf constraint): New constraint for relaxed, consume or relaxed memory
	models.
	* config/arm/sync.md (atomic_load<mode>): Add new ARMv8-M Baseline only
	alternatives to allow any register when memory model matches Pf and
	thus lda is used, but only low registers otherwise.  Use unpredicated
	output template for Thumb-1 targets.
	(atomic_store<mode>): Likewise for stl.
	(arm_load_exclusive<mode>): Add new ARMv8-M Baseline only alternative
	whose output template does not have predication.
	(arm_load_acquire_exclusive<mode>): Likewise.
	(arm_load_exclusivesi): Likewise.
	(arm_load_acquire_exclusivesi): Likewise.
	(arm_store_release_exclusive<mode>): Likewise.
	(arm_store_exclusive<mode>): Use unpredicated output template for
	Thumb-1 targets.

	gcc/
	Backport from trunk r241577.
	2016-10-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (arm_expand_compare_and_swap): Add new bdst local
	variable.  Add the new parameter to the insn generator.  Set that
	parameter to be CC flag for 32-bit targets, bval otherwise.  Set the
	return value from the negation of that parameter for Thumb-1, keeping
	the logic unchanged otherwise except for using bdst as the destination
	register of the compare_and_swap insn.
	(arm_split_compare_and_swap): Add explanation about how is the value
	returned to the function comment.  Rename scratch variable to
	neg_bval.  Adapt initialization of variables holding operands to the
	new operand numbers.  Use return register to hold result of store
	exclusive for Thumb-1, scratch register otherwise.  Construct the
	appropriate cbranch for Thumb-1 targets, keeping the logic unchanged
	for 32-bit targets.  Guard Z flag setting to restrict to 32bit targets.
	Use gen_cbranchsi4 rather than hand-written conditional branch to loop
	for strongly ordered compare_and_swap.
	* config/arm/predicates.md (cc_register_operand): New predicate.
	* config/arm/sync.md (atomic_compare_and_swap<mode>_1): Use a
	match_operand with the new predicate to accept either the CC flag or a
	destination register for the boolean return value, restricting it to
	CC flag only via constraint.  Adapt operand numbers accordingly.

	gcc/
	Backport from trunk r241578.
	2016-10-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/sync.md (atomic_compare_and_swap<mode>_1): Add new ARMv8-M
	Baseline only alternatives to (i) hold store atomic success value in a
	return register rather than a scratch register, (ii) use a low register
	for it and to (iii) ensure the cbranchsi insn generated by the split
	respect the constraints of Thumb-1 cbranchsi4_insn and
	cbranchsi4_scratch.
	* config/arm/thumb1.md (cbranchsi4_insn): Add comment to indicate
	constraints must match those in atomic_compare_and_swap.
	(cbranchsi4_scratch): Likewise.

	gcc/
	Backport from trunk r241614.
	2016-10-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (arm_split_atomic_op): Add function comment.  Add
	logic to to decide whether to copy over old value to register for new
	value.
	* config/arm/sync.md: Add comments explaning why mode and code
	attribute are not defined in iterators.md
	(thumb1_atomic_op_str): New code attribute.
	(thumb1_atomic_newop_str): Likewise.
	(thumb1_atomic_fetch_op_str): Likewise.
	(thumb1_atomic_fetch_newop_str): Likewise.
	(thumb1_atomic_fetch_oldop_str): Likewise.
	(atomic_exchange<mode>): Add new ARMv8-M Baseline only alternatives to
	mirror the more restrictive constraints of the Thumb-1 insns after
	split compared to Thumb-2 counterpart insns.
	(atomic_<sync_optab><mode>): Likewise.  Add comment to keep constraints
	in sync with non atomic version.
	(atomic_nand<mode>): Likewise.
	(atomic_fetch_<sync_optab><mode>): Likewise.
	(atomic_fetch_nand<mode>): Likewise.
	(atomic_<sync_optab>_fetch<mode>): Likewise.
	(atomic_nand_fetch<mode>): Likewise.
	* config/arm/thumb1.md (thumb1_addsi3): Add comment to keep contraint
	in sync with atomic version.
	(thumb1_subsi3_insn): Likewise.
	(thumb1_andsi3_insn): Likewise.
	(thumb1_iorsi3_insn): Likewise.
	(thumb1_xorsi3_insn): Likewise.

	gcc/
	Backport from trunk r241615.
	2016-10-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline.
	(TARGET_HAVE_LDREXBH): Likewise.
	(TARGET_HAVE_LDACQ): Likewise.

	gcc/testsuite/
	Backport from trunk r241615.
	2016-10-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test.
	* gcc.target/arm/atomic-op-acq_rel-3.c: Likewise.
	* gcc.target/arm/atomic-op-acquire-3.c: Likewise.
	* gcc.target/arm/atomic-op-char-3.c: Likewise.
	* gcc.target/arm/atomic-op-consume-3.c: Likewise.
	* gcc.target/arm/atomic-op-int-3.c: Likewise.
	* gcc.target/arm/atomic-op-relaxed-3.c: Likewise.
	* gcc.target/arm/atomic-op-release-3.c: Likewise.
	* gcc.target/arm/atomic-op-seq_cst-3.c: Likewise.
	* gcc.target/arm/atomic-op-short-3.c: Likewise.

	gcc/
	Backport from trunk r241848.
	2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-arches.def (armv8-m.base): Set Cortex-M23 as
	representative core for this architecture.
	* config/arm/arm-cores.def (cortex-m23): Define new processor.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Likewise.
	* config/arm/arm.c (arm_v6m_tune): Add Cortex-M23 to the list of cores
	this tuning parameters apply to in the comment.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Add Cortex-M23 to the list of
	valid -mcpu options.
	* doc/invoke.texi (ARM Options): Document new Cortex-M23 processor.

	gcc/
	Backport from trunk r241849.
	2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-arches.def (armv8-m.main+dsp): Set Cortex-M33 as
	representative core for this architecture.
	* config/arm/arm-cores.def (cortex-m33): Define new processor.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Likewise.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Add Cortex-M33 to the list of
	valid -mcpu options.
	* doc/invoke.texi (ARM Options): Document new Cortex-M33 processor.

	gcc/
	Backport from trunk r242596.
	2016-11-18  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-protos.h (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M,
	FL_MODE26, FL_MODE32, FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED,
	FL_STRONG, FL_ARCH5E, FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF,
	FL_ARCH6K, FL_THUMB2, FL_NOTM, FL_THUMB_DIV, FL_VFPV3, FL_NEON,
	FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV, FL_ARCH8, FL_CRC32, FL_SMALLMUL,
	FL_NO_VOLATILE_CE, FL_IWMMXT, FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1,
	FL2_ARCH8_2, FL2_FP16INST): Reindent comment, add final dot when
	missing and make value unsigned.
	(arm_feature_set): Use unsigned entries instead of unsigned long.

	gcc/
	Backport from trunk r242597.
	2016-11-18  Terry Guo  <terry.guo@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* common/config/arm/arm-common.c (arm_target_thumb_only): New function.
	* config/arm/arm-opts.h: Include arm-flags.h.
	(struct arm_arch_core_flag): Define.
	(arm_arch_core_flags): Define.
	* config/arm/arm-protos.h: Include arm-flags.h
	(FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32,
	FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E,
	FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM,
	FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV,
	FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT,
	FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST,
	FL_TUNE, FL_FOR_ARCH2, FL_FOR_ARCH3, FL_FOR_ARCH3M, FL_FOR_ARCH4,
	FL_FOR_ARCH4T, FL_FOR_ARCH5, FL_FOR_ARCH5T, FL_FOR_ARCH5E,
	FL_FOR_ARCH5TE, FL_FOR_ARCH5TEJ, FL_FOR_ARCH6, FL_FOR_ARCH6J,
	FL_FOR_ARCH6K, FL_FOR_ARCH6Z, FL_FOR_ARCH6ZK, FL_FOR_ARCH6KZ,
	FL_FOR_ARCH6T2, FL_FOR_ARCH6M, FL_FOR_ARCH7, FL_FOR_ARCH7A,
	FL_FOR_ARCH7VE, FL_FOR_ARCH7R, FL_FOR_ARCH7M, FL_FOR_ARCH7EM,
	FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A, FL2_FOR_ARCH8_2A, FL_FOR_ARCH8M_BASE,
	FL_FOR_ARCH8M_MAIN, arm_feature_set, ARM_FSET_MAKE,
	ARM_FSET_MAKE_CPU1, ARM_FSET_MAKE_CPU2, ARM_FSET_CPU1, ARM_FSET_CPU2,
	ARM_FSET_EMPTY, ARM_FSET_ANY, ARM_FSET_HAS_CPU1, ARM_FSET_HAS_CPU2,
	ARM_FSET_HAS_CPU, ARM_FSET_ADD_CPU1, ARM_FSET_ADD_CPU2,
	ARM_FSET_DEL_CPU1, ARM_FSET_DEL_CPU2, ARM_FSET_UNION, ARM_FSET_INTER,
	ARM_FSET_XOR, ARM_FSET_EXCLUDE, ARM_FSET_IS_EMPTY,
	ARM_FSET_CPU_SUBSET): Move to ...
	* config/arm/arm-flags.h: This new file.
	* config/arm/arm.h (TARGET_MODE_SPEC_FUNCTIONS): Define.
	(EXTRA_SPEC_FUNCTIONS): Add TARGET_MODE_SPEC_FUNCTIONS to its value.
	(TARGET_MODE_SPECS): Define.
	(DRIVER_SELF_SPECS): Add TARGET_MODE_SPECS to its value.

	gcc/testsuite/
	Backport from trunk r242597.
	2016-11-18  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/optional_thumb-1.c: New test.
	* gcc.target/arm/optional_thumb-2.c: New test.
	* gcc.target/arm/optional_thumb-3.c: New test.

	gcc/
	Backport from trunk r242696.
	2016-11-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config.gcc: Allow new rmprofile value for configure option
	--with-multilib-list.
	* config/arm/t-rmprofile: New file.
	* doc/install.texi (--with-multilib-list): Document new rmprofile value
	for ARM.

	gcc/testsuite/
	Backport from trunk r243013.
	2016-11-30  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* lib/target-supports.exp (add_options_for_arm_arch_v6m): Add
	-mfloat-abi=soft option.
	(add_options_for_arm_arch_v8m_base): Likewise.  Reindent containing
	foreach loop.

	gcc/
	Backport from trunk r243015.
	2016-11-30  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/t-rmprofile: Add mappings for Cortex-M23 and Cortex-M33.

	gcc/
	Backport from trunk r243187.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config.gcc (extra_headers): Added arm_cmse.h.
	* config/arm/arm-arches.def (ARM_ARCH):
	(armv8-m): Add FL2_CMSE.
	(armv8-m.main): Likewise.
	(armv8-m.main+dsp): Likewise.
	* config/arm/arm-c.c
	(arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
	* config/arm/arm-flags.h: Define FL2_CMSE.
	* config/arm.c (arm_arch_cmse): New.
	(arm_option_override): New error for unsupported cmse target.
	* config/arm/arm.h (arm_arch_cmse): New.
	* config/arm/arm.opt (mcmse): New.
	* config/arm/arm_cmse.h: New file.
	* doc/invoke.texi (ARM Options): Add -mcmse.
	* doc/sourcebuild.texi (arm_cmse_ok): Add new effective target.
	* doc/extend.texi: Add ARMv8-M Security Extensions entry.

	gcc/testsuite/
	Backport from trunk r243187.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse.exp: New.
	* gcc.target/arm/cmse/cmse-1.c: New.
	* gcc.target/arm/cmse/cmse-12.c: New.
	* lib/target-supports.exp
	(check_effective_target_arm_cmse_ok): New.

	libgcc/
	Backport from trunk r243187.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/t-arm (HAVE_CMSE): New.
	* config/arm/cmse.c: New.

	gcc/
	Backport from trunk r243188.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (arm_handle_cmse_nonsecure_entry): New.
	(arm_attribute_table): Added cmse_nonsecure_entry
	(arm_compute_func_type): Handle cmse_nonsecure_entry.
	(cmse_func_args_or_return_in_stack): New.
	(arm_handle_cmse_nonsecure_entry): New.
	* config/arm/arm.h (ARM_FT_CMSE_ENTRY): New macro define.
	(IS_CMSE_ENTRY): Likewise.
	* doc/extend.texi (ARM ARMv8-M Security Extensions): New attribute.

	gcc/testsuite/
	Backport from trunk r243188.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse-3.c: New.

	gcc/
	Backport from trunk r243189.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (use_return_insn): Change to return with  bxns
	when cmse_nonsecure_entry.
	(output_return_instruction): Likewise.
	(arm_output_function_prologue): Likewise.
	(thumb_pop): Likewise.
	(thumb_exit): Likewise.
	(thumb2_expand_return): Assert that entry functions always have simple
	returns.
	(arm_expand_epilogue): Handle entry functions.
	(arm_function_ok_for_sibcall): Disable sibcall for entry functions.
	(arm_asm_declare_function_name): New.
	* config/arm/arm-protos.h (arm_asm_declare_function_name): New.
	* config/arm/elf.h (ASM_DECLARE_FUNCTION_NAME): Redefine to
	use arm_asm_declare_function_name.

	gcc/testsuite/
	Backport from trunk r243189.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse-4.c: New.
	* gcc.target/arm/cmse/cmse-9.c: New.
	* gcc.target/arm/cmse/cmse-10.c: New.

	gcc/
	Backport from trunk r243190.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (output_return_instruction): Clear
	registers.
	(thumb2_expand_return): Likewise.
	(thumb1_expand_epilogue): Likewise.
	(thumb_exit): Likewise.
	(arm_expand_epilogue): Likewise.
	(cmse_nonsecure_entry_clear_before_return): New.
	(comp_not_to_clear_mask_str_un): New.
	(compute_not_to_clear_mask): New.
	* config/arm/thumb1.md (*epilogue_insns): Change length attribute.
	* config/arm/thumb2.md (*thumb2_return): Disable for
	cmse_nonsecure_entry functions.
	(*thumb2_cmse_entry_return): Duplicate thumb2_return pattern for
	cmse_nonsecure_entry functions.

	gcc/testsuite/
	Backport from trunk r243190.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse.exp: Test different multilibs separate.
	* gcc.target/arm/cmse/struct-1.c: New.
	* gcc.target/arm/cmse/bitfield-1.c: New.
	* gcc.target/arm/cmse/bitfield-2.c: New.
	* gcc.target/arm/cmse/bitfield-3.c: New.
	* gcc.target/arm/cmse/baseline/cmse-2.c: New.
	* gcc.target/arm/cmse/baseline/softfp.c: New.
	* gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
	* gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
	* gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.

	gcc/
	Backport from trunk r243191.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (gimplify.h): New include.
	(arm_handle_cmse_nonsecure_call): New.
	(arm_attribute_table): Added cmse_nonsecure_call.
	(arm_comp_type_attributes): Deny compatibility of function types
	with without the cmse_nonsecure_call attribute.
	* doc/extend.texi (ARM ARMv8-M Security Extensions): New attribute.

	gcc/testsuite/
	Backport from trunk r243191.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse-3.c: Add tests.
	* gcc.target/arm/cmse/cmse-4.c: Add tests.
	* gcc.target/arm/cmse/cmse-15.c: New.

	gcc/
	Backport from trunk r243192.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm.c (detect_cmse_nonsecure_call): New.
	(cmse_nonsecure_call_clear_caller_saved): New.
	(arm_reorg): Use cmse_nonsecure_call_clear_caller_saved.
	(arm_function_ok_for_sibcall): Disable sibcalls for
	cmse_nonsecure_call.
	* config/arm/arm-protos.h (detect_cmse_nonsecure_call): New.
	* config/arm/arm.md (call): Handle cmse_nonsecure_entry.
	(call_value): Likewise.
	(nonsecure_call_internal): New.
	(nonsecure_call_value_internal): New.
	* config/arm/thumb1.md (*nonsecure_call_reg_thumb1_v5): New.
	(*nonsecure_call_value_reg_thumb1_v5): New.
	* config/arm/thumb2.md (*nonsecure_call_reg_thumb2): New.
	(*nonsecure_call_value_reg_thumb2): New.
	* config/arm/unspecs.md (UNSPEC_NONSECURE_MEM): New.

	gcc/testsuite/
	Backport from trunk r243192.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse.exp: Run tests in mainline dir.
	* gcc.target/arm/cmse/cmse-9.c: Added some extra tests.
	* gcc.target/arm/cmse/cmse-14.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-4.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-5.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-6.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-7.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-8.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-9.c: New.
	* gcc.target/arm/cmse/baseline/bitfield-and-union-1.c: New.
	* gcc.target/arm/cmse/baseline/cmse-11.c: New.
	* gcc.target/arm/cmse/baseline/cmse-13.c: New.
	* gcc.target/arm/cmse/baseline/cmse-6.c: New.
	* gcc.target/arm/cmse/baseline/union-1.c: New.
	* gcc.target/arm/cmse/baseline/union-2.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-4.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-5.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-6.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-7.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-8.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-9.c: New.
	* gcc.target/arm/cmse/mainline/bitfield-and-union-1.c: New.
	* gcc.target/arm/cmse/mainline/union-1.c: New.
	* gcc.target/arm/cmse/mainline/union-2.c: New.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: New.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: New.
	* gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: New.
	* gcc.target/arm/cmse/mainline/hard/cmse-13.c: New.
	* gcc.target/arm/cmse/mainline/hard/cmse-7.c: New.
	* gcc.target/arm/cmse/mainline/hard/cmse-8.c: New.
	* gcc.target/arm/cmse/mainline/soft/cmse-13.c: New.
	* gcc.target/arm/cmse/mainline/soft/cmse-7.c: New.
	* gcc.target/arm/cmse/mainline/soft/cmse-8.c: New.
	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: New.
	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: New.
	* gcc.target/arm/cmse/mainline/softfp/cmse-13.c: New.
	* gcc.target/arm/cmse/mainline/softfp/cmse-7.c: New.
	* gcc.target/arm/cmse/mainline/softfp/cmse-8.c: New.

	libgcc/
	Backport from trunk r243192.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/cmse_nonsecure_call.S: New.
	* config/arm/t-arm: Compile cmse_nonsecure_call.S

	gcc/
	Backport from trunk r243193.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/arm/arm-builtins.c (arm_builtins): Define
	ARM_BUILTIN_CMSE_NONSECURE_CALLER.
	(bdesc_2arg): Add line for cmse_nonsecure_caller.
	(arm_init_builtins): Handle cmse_nonsecure_caller.
	(arm_expand_builtin): Likewise.
	* config/arm/arm_cmse.h (cmse_nonsecure_caller): New.

	gcc/testsuite/
	Backport from trunk r243193.
	2016-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
	    Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* gcc.target/arm/cmse/cmse-1.c: Add test for
	cmse_nonsecure_caller.

	gcc/
	Backport from trunk r243216.
	2016-12-01  Jeff Law  <law@redhat.com>

	* config/arm/arm.c (arm_handle_cmse_nonsecure_call): Remove unused
	variable main_variant.

Change-Id: Ibe821b25c811c214c51d5cbaceb4ea960c619633

3 files changed, 253 insertions, 0 deletions

diff --git a/libgcc/config/arm/cmse.c b/libgcc/config/arm/cmse.c
new file mode 100644
index 00000000000..fe3a22967c8
--- /dev/null
+++ b/libgcc/config/arm/cmse.c
@@ -0,0 +1,108 @@
+/* ARMv8-M Security Extensions routines.
+   Copyright (C) 2015-2016 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 3, or (at your option) any
+   later version.
+
+   This file is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+
+#if __ARM_FEATURE_CMSE & 1
+
+#include <arm_cmse.h>
+
+/* ARM intrinsic function to perform a permission check on a given
+   address range.  See ACLE changes for ARMv8-M.  */
+
+void *
+cmse_check_address_range (void *p, size_t size, int flags)
+{
+  cmse_address_info_t permb, perme;
+  char *pb = (char *) p, *pe;
+
+  /* Check if the range wraps around.  */
+  if (UINTPTR_MAX - (uintptr_t) p < size)
+    return NULL;
+
+  /* Check if an unknown flag is present.  */
+  int known = CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE | CMSE_MPU_READ;
+  int known_secure_level = CMSE_MPU_UNPRIV;
+#if __ARM_FEATURE_CMSE & 2
+  known |= CMSE_AU_NONSECURE | CMSE_MPU_NONSECURE;
+  known_secure_level |= CMSE_MPU_NONSECURE;
+#endif
+  if (flags & (~known))
+    return NULL;
+
+  /* Execute the right variant of the TT instructions.  */
+  pe = pb + size - 1;
+  const int singleCheck = (((uintptr_t) pb ^ (uintptr_t) pe) < 32);
+  switch (flags & known_secure_level)
+    {
+    case 0:
+      permb = cmse_TT (pb);
+      perme = singleCheck ? permb : cmse_TT (pe);
+      break;
+    case CMSE_MPU_UNPRIV:
+      permb = cmse_TTT (pb);
+      perme = singleCheck ? permb : cmse_TTT (pe);
+      break;
+#if __ARM_FEATURE_CMSE & 2
+    case CMSE_MPU_NONSECURE:
+      permb = cmse_TTA (pb);
+      perme = singleCheck ? permb : cmse_TTA (pe);
+      break;
+    case CMSE_MPU_UNPRIV | CMSE_MPU_NONSECURE:
+      permb = cmse_TTAT (pb);
+      perme = singleCheck ? permb : cmse_TTAT (pe);
+      break;
+#endif
+    default:
+      /* Invalid flag, eg.  CMSE_MPU_NONSECURE specified but
+	 __ARM_FEATURE_CMSE & 2 == 0.  */
+      return NULL;
+    }
+
+  /* Check that the range does not cross MPU, SAU, or IDAU boundaries.  */
+  if (permb.value != perme.value)
+    return NULL;
+
+  /* Check the permissions on the range.  */
+  switch (flags & (~known_secure_level))
+    {
+#if __ARM_FEATURE_CMSE & 2
+    case CMSE_MPU_READ | CMSE_MPU_READWRITE | CMSE_AU_NONSECURE:
+    case		 CMSE_MPU_READWRITE | CMSE_AU_NONSECURE:
+      return permb.flags.nonsecure_readwrite_ok	? p : NULL;
+    case CMSE_MPU_READ | CMSE_AU_NONSECURE:
+      return permb.flags.nonsecure_read_ok	? p : NULL;
+    case CMSE_AU_NONSECURE:
+      return permb.flags.secure			? NULL : p;
+#endif
+    case CMSE_MPU_READ | CMSE_MPU_READWRITE:
+    case		 CMSE_MPU_READWRITE:
+      return permb.flags.readwrite_ok		? p : NULL;
+    case CMSE_MPU_READ:
+      return permb.flags.read_ok		? p : NULL;
+    default:
+      return NULL;
+    }
+}
+
+
+#endif /* __ARM_FEATURE_CMSE & 1.  */
diff --git a/libgcc/config/arm/cmse_nonsecure_call.S b/libgcc/config/arm/cmse_nonsecure_call.S
new file mode 100644
index 00000000000..68b6a1cb500
--- /dev/null
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -0,0 +1,131 @@
+/* CMSE wrapper function used to save, clear and restore callee saved registers
+   for cmse_nonsecure_call's.
+
+   Copyright (C) 2016 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 3, or (at your option) any
+   later version.
+
+   This file is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+.syntax unified
+.thumb
+.global __gnu_cmse_nonsecure_call
+__gnu_cmse_nonsecure_call:
+#if defined(__ARM_ARCH_8M_MAIN__)
+push	    {r5-r11,lr}
+mov	    r7, r4
+mov	    r8, r4
+mov	    r9, r4
+mov	    r10, r4
+mov	    r11, r4
+mov	    ip, r4
+
+/* Save and clear callee-saved registers only if we are dealing with hard float
+   ABI.  The unused caller-saved registers have already been cleared by GCC
+   generated code.  */
+#ifdef __ARM_PCS_VFP
+vpush.f64   {d8-d15}
+mov	    r5, #0
+vmov	    d8, r5, r5
+#if __ARM_FP & 0x04
+vmov	    s18, s19, r5, r5
+vmov	    s20, s21, r5, r5
+vmov	    s22, s23, r5, r5
+vmov	    s24, s25, r5, r5
+vmov	    s26, s27, r5, r5
+vmov	    s28, s29, r5, r5
+vmov	    s30, s31, r5, r5
+#elif __ARM_FP & 0x08
+vmov.f64    d9, d8
+vmov.f64    d10, d8
+vmov.f64    d11, d8
+vmov.f64    d12, d8
+vmov.f64    d13, d8
+vmov.f64    d14, d8
+vmov.f64    d15, d8
+#else
+#error "Half precision implementation not supported."
+#endif
+/* Clear the cumulative exception-status bits (0-4,7) and the
+   condition code bits (28-31) of the FPSCR.  */
+vmrs	    r5, fpscr
+movw	    r6, #65376
+movt	    r6, #4095
+ands	    r5, r6
+vmsr	    fpscr, r5
+
+/* We are not dealing with hard float ABI, so we can safely use the vlstm and
+   vlldm instructions without needing to preserve the registers used for
+   argument passing.  */
+#else
+sub	    sp, sp, #0x88 /* Reserve stack space to save all floating point
+			     registers, including FPSCR.  */
+vlstm	    sp		  /* Lazy store and clearance of d0-d16 and FPSCR.  */
+#endif /* __ARM_PCS_VFP */
+
+/* Make sure to clear the 'GE' bits of the APSR register if 32-bit SIMD
+   instructions are available.  */
+#if defined(__ARM_FEATURE_SIMD32)
+msr	    APSR_nzcvqg, r4
+#else
+msr	    APSR_nzcvq, r4
+#endif
+
+mov	    r5, r4
+mov	    r6, r4
+blxns	    r4
+
+#ifdef __ARM_PCS_VFP
+vpop.f64    {d8-d15}
+#else
+vlldm	    sp		  /* Lazy restore of d0-d16 and FPSCR.  */
+add	    sp, sp, #0x88 /* Free space used to save floating point registers.  */
+#endif /* __ARM_PCS_VFP */
+
+pop	    {r5-r11, pc}
+
+#elif defined (__ARM_ARCH_8M_BASE__)
+push	    {r5-r7, lr}
+mov	    r5, r8
+mov	    r6, r9
+mov	    r7, r10
+push	    {r5-r7}
+mov	    r5, r11
+push	    {r5}
+mov	    r5, r4
+mov	    r6, r4
+mov	    r7, r4
+mov	    r8, r4
+mov	    r9, r4
+mov	    r10, r4
+mov	    r11, r4
+mov	    ip, r4
+msr	    APSR_nzcvq, r4
+blxns	    r4
+pop	    {r5}
+mov	    r11, r5
+pop	    {r5-r7}
+mov	    r10, r7
+mov	    r9, r6
+mov	    r8, r5
+pop	    {r5-r7, pc}
+
+#else
+#error "This should only be used for armv8-m base- and mainline."
+#endif
diff --git a/libgcc/config/arm/t-arm b/libgcc/config/arm/t-arm
index 4e17e99b4a5..9e85ac06b14 100644
--- a/libgcc/config/arm/t-arm
+++ b/libgcc/config/arm/t-arm
@@ -1,3 +1,17 @@
 LIB1ASMSRC = arm/lib1funcs.S
 LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi _thumb1_case_shi \
 	_thumb1_case_uhi _thumb1_case_si
+
+HAVE_CMSE:=$(findstring __ARM_FEATURE_CMSE,$(shell $(gcc_compile_bare) -dM -E - </dev/null))
+ifneq ($(shell $(gcc_compile_bare) -E -mcmse - </dev/null 2>/dev/null),)
+CMSE_OPTS:=-mcmse
+endif
+
+ifdef HAVE_CMSE
+libgcc-objects += cmse.o cmse_nonsecure_call.o
+
+cmse.o: $(srcdir)/config/arm/cmse.c
+	$(gcc_compile) -c $(CMSE_OPTS) $<
+cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S
+		       $(gcc_compile) -c $<
+endif