diff options
| author | krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-06-24 06:47:47 +0000 |
|---|---|---|
| committer | krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-06-24 06:47:47 +0000 |
| commit | 9e034d188726e3ebdb754ad0b99b4ed8ef8f3a45 (patch) | |
| tree | 79bf7d56590e8706329cc1ed8e91b344dc9c393e /gcc | |
| parent | 8aaac84f5fc2626b3ba462feb5f2f2f46e54ab19 (diff) | |
S/390: Switch mode attribute to bhfgq for vec scatter
gcc/ChangeLog:
2015-06-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/vx-builtins.md
("vec_scatter_element<mode>_<non_vec_int>")
("vec_scatter_element<V_HW_64:mode>_SI"): Replace gf mode
attribute with bhfgq.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@224874 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/s390/vx-builtins.md | 4 |
2 files changed, 9 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c4aceca2351..be625c5b06b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2015-06-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + * config/s390/vx-builtins.md + ("vec_scatter_element<mode>_<non_vec_int>") + ("vec_scatter_element<V_HW_64:mode>_SI"): Replace gf mode + attribute with bhfgq. + +2015-06-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + * config/s390/s390-builtins.def: Fix vpopct instruction comments. 2015-06-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com> diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index e306ee8bd05..35ada1371ff 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -414,7 +414,7 @@ (unspec:<non_vec> [(match_operand:V_HW_64 0 "register_operand" "v") (match_dup 3)] UNSPEC_VEC_EXTRACT))] "TARGET_VX && !TARGET_64BIT" - "vsce<V_HW_64:gf>\t%v0,%O2(%v1,%R2),%3" + "vsce<V_HW_64:bhfgq>\t%v0,%O2(%v1,%R2),%3" [(set_attr "op_type" "VRV")]) ; Element size and target adress size is the same @@ -428,7 +428,7 @@ (unspec:<non_vec> [(match_operand:V_HW_32_64 0 "register_operand" "v") (match_dup 3)] UNSPEC_VEC_EXTRACT))] "TARGET_VX" - "vsce<gf>\t%v0,%O2(%v1,%R2),%3" + "vsce<bhfgq>\t%v0,%O2(%v1,%R2),%3" [(set_attr "op_type" "VRV")]) ; Depending on the address size we have to expand a different pattern. |