diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2017-07-04 10:40:48 +0200 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@linaro.org> | 2017-07-04 13:48:56 +0000 |
| commit | e8f14d2a2414f0b30a7fde8f25a512e9d57dd279 (patch) | |
| tree | 7bec34ac900df4a5d5c4fd7fa93d08d7788c29f4 /gcc | |
| parent | 20e5294447e540aad0ddea8f3117f37e60fe30f0 (diff) | |
gcc/
Backport from trunk r248836.
2017-06-02 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for
comparision with zero.
gcc/testsuite/
Backport from trunk r248836.
2017-06-02 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/cmp_shifted_reg_1.c: New.
Change-Id: I12a9b3a5a33d0fced8fccf00f8d038fadcdad317
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c | 11 |
2 files changed, 12 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index bb8212351a0..9a95c41c304 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4775,7 +4775,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y) the comparison will have to be swapped when we emit the assembly code. */ if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) - && (REG_P (y) || GET_CODE (y) == SUBREG) + && (REG_P (y) || GET_CODE (y) == SUBREG || y == const0_rtx) && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)) diff --git a/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c b/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c new file mode 100644 index 00000000000..cacecf4e71d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 " } */ + +int f3 (int x, int y) +{ + int res = x << 3; + return res != 0; +} + +/* We should combine the shift and compare */ +/* { dg-final { scan-assembler "cmp\.*\twzr, w\[0-9\]+, lsl 3" } } */ |