diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2015-10-13 13:22:01 +0200 |
|---|---|---|
| committer | Linaro Code Review <review@review.linaro.org> | 2015-10-14 08:00:45 +0000 |
| commit | 01ba833e17aeea179d0034792bf7dce1d22a750e (patch) | |
| tree | 75d7ff0197a235d70d1acfc61274e389983962ec /gcc | |
| parent | 50f39acd0c53d173690cd1e18aa3934205673398 (diff) | |
gcc/
Backport from trunk r226253.
2015-07-27 Wilco Dijkstra <wdijkstr@arm.com>
* gcc/config/aarch64/aarch64.md (aarch64_lshr_sisd_or_int_<mode>3):
Place integer variant first.
(aarch64_ashr_sisd_or_int_<mode>3): Likewise.
Change-Id: If119d9605e334be3a74f61aeffc6d320094bf6ea
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 35812702f5e..fe7e2152f5e 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3534,17 +3534,18 @@ ;; Logical right shift using SISD or Integer instruction (define_insn "*aarch64_lshr_sisd_or_int_<mode>3" - [(set (match_operand:GPI 0 "register_operand" "=w,&w,r") + [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w") (lshiftrt:GPI - (match_operand:GPI 1 "register_operand" "w,w,r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,w,rUs<cmode>")))] + (match_operand:GPI 1 "register_operand" "r,w,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w,0")))] "" "@ + lsr\t%<w>0, %<w>1, %<w>2 ushr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 # - lsr\t%<w>0, %<w>1, %<w>2" - [(set_attr "simd" "yes,yes,no") - (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")] + #" + [(set_attr "simd" "no,yes,yes,yes") + (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] ) (define_split @@ -3579,18 +3580,18 @@ ;; Arithmetic right shift using SISD or Integer instruction (define_insn "*aarch64_ashr_sisd_or_int_<mode>3" - [(set (match_operand:GPI 0 "register_operand" "=w,&w,&w,r") + [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w") (ashiftrt:GPI - (match_operand:GPI 1 "register_operand" "w,w,w,r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "Us<cmode>,w,0,rUs<cmode>")))] + (match_operand:GPI 1 "register_operand" "r,w,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "rUs<cmode>,Us<cmode>,w,0")))] "" "@ + asr\t%<w>0, %<w>1, %<w>2 sshr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 # - # - asr\t%<w>0, %<w>1, %<w>2" - [(set_attr "simd" "yes,yes,yes,no") - (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>,shift_reg")] + #" + [(set_attr "simd" "no,yes,yes,yes") + (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] ) (define_split |