diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2016-09-16 15:17:22 +0200 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@linaro.org> | 2016-09-16 15:17:22 +0200 |
| commit | ae5de607bec054c1611c7d91c4d12cf070fa4159 (patch) | |
| tree | b02baf1682bb31f7fc6ffed95aa6b7bd8350b6a8 /gcc/testsuite/gcc.target | |
| parent | afe3fc322a7edd6a564d5a79b0ab640be227f548 (diff) | |
All added testcases since linaro 6 branch creation.linaro-local/Yvan-linaro-6-branch-tests
Change-Id: Ibd63e9edfec0418ef3b882b2e0f82a1a17c357b6
Diffstat (limited to 'gcc/testsuite/gcc.target')
249 files changed, 9730 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/test_27.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/test_27.c new file mode 100644 index 00000000000..7bc79f5fcaf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/test_27.c @@ -0,0 +1,46 @@ +/* Test AAPCS64 layout + + Test named homogeneous floating-point aggregates of __fp16 data, + which should be passed in SIMD/FP registers or via the stack. */ + +/* { dg-do run { target aarch64*-*-* } } */ + +#ifndef IN_FRAMEWORK +#define TESTFILE "test_27.c" + +struct x0 +{ + __fp16 v[1]; +} f16x1; + +struct x1 +{ + __fp16 v[2]; +} f16x2; + +struct x2 +{ + __fp16 v[3]; +} f16x3; + +#define HAS_DATA_INIT_FUNC +void init_data () +{ + f16x1.v[0] = 2.0f; + f16x2.v[0] = 4.0f; + f16x2.v[1] = 8.0f; + f16x3.v[0] = 16.0f; + f16x3.v[1] = 32.0f; + f16x3.v[2] = 64.0f; +} + +#include "abitest.h" +#else +ARG (struct x0, f16x1, H0) +ARG (struct x1, f16x2, H1) +ARG (struct x2, f16x3, H3) +ARG (struct x1, f16x2, H6) +ARG (struct x0, f16x1, STACK) +ARG (int, 0xdeadbeef, W0) +LAST_ARG (double, 456.789, STACK+8) +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-16.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-16.c new file mode 100644 index 00000000000..73f8f1c7bef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-16.c @@ -0,0 +1,28 @@ +/* Test AAPCS64 layout and __builtin_va_arg. + + This test is focused particularly on __fp16 unnamed homogeneous + floating-point aggregate types which should be passed in fp/simd + registers until we run out of those, then the stack. */ + +/* { dg-do run { target aarch64*-*-* } } */ + +#ifndef IN_FRAMEWORK +#define AAPCS64_TEST_STDARG +#define TESTFILE "va_arg-16.c" +#include "type-def.h" + +struct hfa_f16x1_t hfa_f16x1 = {2.0f}; +struct hfa_f16x2_t hfa_f16x2 = {4.0f, 8.0f}; +struct hfa_f16x3_t hfa_f16x3 = {16.0f, 32.0f, 64.0f}; + +#include "abitest.h" +#else + ARG (int, 1, W0, LAST_NAMED_ARG_ID) + DOTS + ANON (struct hfa_f16x1_t, hfa_f16x1, H0 , 0) + ANON (struct hfa_f16x2_t, hfa_f16x2, H1 , 1) + ANON (struct hfa_f16x3_t, hfa_f16x3, H3 , 2) + ANON (struct hfa_f16x2_t, hfa_f16x2, H6 , 3) + ANON (struct hfa_f16x1_t, hfa_f16x1, STACK , 4) + LAST_ANON(double , 1.0 , STACK+8, 5) +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c new file mode 100644 index 00000000000..519cffb0125 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/p64_p128.c @@ -0,0 +1,663 @@ +/* This file contains tests for all the *p64 intrinsics, except for + vreinterpret which have their own testcase. */ + +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results: vbsl. */ +VECT_VAR_DECL(vbsl_expected,poly,64,1) [] = { 0xfffffff1 }; +VECT_VAR_DECL(vbsl_expected,poly,64,2) [] = { 0xfffffff1, + 0xfffffff1 }; + +/* Expected results: vceq. */ +VECT_VAR_DECL(vceq_expected,uint,64,1) [] = { 0x0 }; + +/* Expected results: vcombine. */ +VECT_VAR_DECL(vcombine_expected,poly,64,2) [] = { 0xfffffffffffffff0, 0x88 }; + +/* Expected results: vcreate. */ +VECT_VAR_DECL(vcreate_expected,poly,64,1) [] = { 0x123456789abcdef0 }; + +/* Expected results: vdup_lane. */ +VECT_VAR_DECL(vdup_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vdup_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff0 }; + +/* Expected results: vdup_n. */ +VECT_VAR_DECL(vdup_n_expected0,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vdup_n_expected0,poly,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff0 }; +VECT_VAR_DECL(vdup_n_expected1,poly,64,1) [] = { 0xfffffffffffffff1 }; +VECT_VAR_DECL(vdup_n_expected1,poly,64,2) [] = { 0xfffffffffffffff1, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vdup_n_expected2,poly,64,1) [] = { 0xfffffffffffffff2 }; +VECT_VAR_DECL(vdup_n_expected2,poly,64,2) [] = { 0xfffffffffffffff2, + 0xfffffffffffffff2 }; + +/* Expected results: vext. */ +VECT_VAR_DECL(vext_expected,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vext_expected,poly,64,2) [] = { 0xfffffffffffffff1, 0x88 }; + +/* Expected results: vget_low. */ +VECT_VAR_DECL(vget_low_expected,poly,64,1) [] = { 0xfffffffffffffff0 }; + +/* Expected results: vld1. */ +VECT_VAR_DECL(vld1_expected,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vld1_expected,poly,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; + +/* Expected results: vld1_dup. */ +VECT_VAR_DECL(vld1_dup_expected0,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vld1_dup_expected0,poly,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff0 }; +VECT_VAR_DECL(vld1_dup_expected1,poly,64,1) [] = { 0xfffffffffffffff1 }; +VECT_VAR_DECL(vld1_dup_expected1,poly,64,2) [] = { 0xfffffffffffffff1, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vld1_dup_expected2,poly,64,1) [] = { 0xfffffffffffffff2 }; +VECT_VAR_DECL(vld1_dup_expected2,poly,64,2) [] = { 0xfffffffffffffff2, + 0xfffffffffffffff2 }; + +/* Expected results: vld1_lane. */ +VECT_VAR_DECL(vld1_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vld1_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0, + 0xaaaaaaaaaaaaaaaa }; + +/* Expected results: vldX. */ +VECT_VAR_DECL(vld2_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vld2_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 }; +VECT_VAR_DECL(vld3_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vld3_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 }; +VECT_VAR_DECL(vld3_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 }; +VECT_VAR_DECL(vld4_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vld4_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 }; +VECT_VAR_DECL(vld4_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 }; +VECT_VAR_DECL(vld4_expected_3,poly,64,1) [] = { 0xfffffffffffffff3 }; + +/* Expected results: vldX_dup. */ +VECT_VAR_DECL(vld2_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vld2_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 }; +VECT_VAR_DECL(vld3_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vld3_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 }; +VECT_VAR_DECL(vld3_dup_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 }; +VECT_VAR_DECL(vld4_dup_expected_0,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vld4_dup_expected_1,poly,64,1) [] = { 0xfffffffffffffff1 }; +VECT_VAR_DECL(vld4_dup_expected_2,poly,64,1) [] = { 0xfffffffffffffff2 }; +VECT_VAR_DECL(vld4_dup_expected_3,poly,64,1) [] = { 0xfffffffffffffff3 }; + +/* Expected results: vsli. */ +VECT_VAR_DECL(vsli_expected,poly,64,1) [] = { 0x10 }; +VECT_VAR_DECL(vsli_expected,poly,64,2) [] = { 0x7ffffffffffff0, + 0x7ffffffffffff1 }; +VECT_VAR_DECL(vsli_expected_max_shift,poly,64,1) [] = { 0x7ffffffffffffff0 }; +VECT_VAR_DECL(vsli_expected_max_shift,poly,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; + +/* Expected results: vsri. */ +VECT_VAR_DECL(vsri_expected,poly,64,1) [] = { 0xe000000000000000 }; +VECT_VAR_DECL(vsri_expected,poly,64,2) [] = { 0xfffffffffffff800, + 0xfffffffffffff800 }; +VECT_VAR_DECL(vsri_expected_max_shift,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vsri_expected_max_shift,poly,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; + +/* Expected results: vst1_lane. */ +VECT_VAR_DECL(vst1_lane_expected,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vst1_lane_expected,poly,64,2) [] = { 0xfffffffffffffff0, + 0x3333333333333333 }; + +int main (void) +{ + int i; + + /* vbsl_p64 tests. */ +#define TEST_MSG "VBSL/VBSLQ" + +#define TEST_VBSL(T3, Q, T1, T2, W, N) \ + VECT_VAR(vbsl_vector_res, T1, W, N) = \ + vbsl##Q##_##T2##W(VECT_VAR(vbsl_vector_first, T3, W, N), \ + VECT_VAR(vbsl_vector, T1, W, N), \ + VECT_VAR(vbsl_vector2, T1, W, N)); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vbsl_vector_res, T1, W, N)) + + DECL_VARIABLE(vbsl_vector, poly, 64, 1); + DECL_VARIABLE(vbsl_vector, poly, 64, 2); + DECL_VARIABLE(vbsl_vector2, poly, 64, 1); + DECL_VARIABLE(vbsl_vector2, poly, 64, 2); + DECL_VARIABLE(vbsl_vector_res, poly, 64, 1); + DECL_VARIABLE(vbsl_vector_res, poly, 64, 2); + + DECL_VARIABLE(vbsl_vector_first, uint, 64, 1); + DECL_VARIABLE(vbsl_vector_first, uint, 64, 2); + + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + VLOAD(vbsl_vector, buffer, , poly, p, 64, 1); + VLOAD(vbsl_vector, buffer, q, poly, p, 64, 2); + + VDUP(vbsl_vector2, , poly, p, 64, 1, 0xFFFFFFF3); + VDUP(vbsl_vector2, q, poly, p, 64, 2, 0xFFFFFFF3); + + VDUP(vbsl_vector_first, , uint, u, 64, 1, 0xFFFFFFF2); + VDUP(vbsl_vector_first, q, uint, u, 64, 2, 0xFFFFFFF2); + + TEST_VBSL(uint, , poly, p, 64, 1); + TEST_VBSL(uint, q, poly, p, 64, 2); + + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vbsl_expected, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vbsl_expected, ""); + + /* vceq_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VCEQ" + +#define TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N) \ + VECT_VAR(vceq_vector_res, T3, W, N) = \ + INSN##Q##_##T2##W(VECT_VAR(vceq_vector, T1, W, N), \ + VECT_VAR(vceq_vector2, T1, W, N)); \ + vst1##Q##_u##W(VECT_VAR(result, T3, W, N), VECT_VAR(vceq_vector_res, T3, W, N)) + +#define TEST_VCOMP(INSN, Q, T1, T2, T3, W, N) \ + TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N) + + DECL_VARIABLE(vceq_vector, poly, 64, 1); + DECL_VARIABLE(vceq_vector2, poly, 64, 1); + DECL_VARIABLE(vceq_vector_res, uint, 64, 1); + + CLEAN(result, uint, 64, 1); + + VLOAD(vceq_vector, buffer, , poly, p, 64, 1); + + VDUP(vceq_vector2, , poly, p, 64, 1, 0x88); + + TEST_VCOMP(vceq, , poly, p, uint, 64, 1); + + CHECK(TEST_MSG, uint, 64, 1, PRIx64, vceq_expected, ""); + + /* vcombine_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VCOMBINE" + +#define TEST_VCOMBINE(T1, T2, W, N, N2) \ + VECT_VAR(vcombine_vector128, T1, W, N2) = \ + vcombine_##T2##W(VECT_VAR(vcombine_vector64_a, T1, W, N), \ + VECT_VAR(vcombine_vector64_b, T1, W, N)); \ + vst1q_##T2##W(VECT_VAR(result, T1, W, N2), VECT_VAR(vcombine_vector128, T1, W, N2)) + + DECL_VARIABLE(vcombine_vector64_a, poly, 64, 1); + DECL_VARIABLE(vcombine_vector64_b, poly, 64, 1); + DECL_VARIABLE(vcombine_vector128, poly, 64, 2); + + CLEAN(result, poly, 64, 2); + + VLOAD(vcombine_vector64_a, buffer, , poly, p, 64, 1); + + VDUP(vcombine_vector64_b, , poly, p, 64, 1, 0x88); + + TEST_VCOMBINE(poly, p, 64, 1, 2); + + CHECK(TEST_MSG, poly, 64, 2, PRIx16, vcombine_expected, ""); + + /* vcreate_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VCREATE" + +#define TEST_VCREATE(T1, T2, W, N) \ + VECT_VAR(vcreate_vector_res, T1, W, N) = \ + vcreate_##T2##W(VECT_VAR(vcreate_val, T1, W, N)); \ + vst1_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vcreate_vector_res, T1, W, N)) + +#define DECL_VAL(VAR, T1, W, N) \ + uint64_t VECT_VAR(VAR, T1, W, N) + + DECL_VAL(vcreate_val, poly, 64, 1); + DECL_VARIABLE(vcreate_vector_res, poly, 64, 1); + + CLEAN(result, poly, 64, 2); + + VECT_VAR(vcreate_val, poly, 64, 1) = 0x123456789abcdef0ULL; + + TEST_VCREATE(poly, p, 64, 1); + + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vcreate_expected, ""); + + /* vdup_lane_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VDUP_LANE/VDUP_LANEQ" + +#define TEST_VDUP_LANE(Q, T1, T2, W, N, N2, L) \ + VECT_VAR(vdup_lane_vector_res, T1, W, N) = \ + vdup##Q##_lane_##T2##W(VECT_VAR(vdup_lane_vector, T1, W, N2), L); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vdup_lane_vector_res, T1, W, N)) + + DECL_VARIABLE(vdup_lane_vector, poly, 64, 1); + DECL_VARIABLE(vdup_lane_vector, poly, 64, 2); + DECL_VARIABLE(vdup_lane_vector_res, poly, 64, 1); + DECL_VARIABLE(vdup_lane_vector_res, poly, 64, 2); + + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + VLOAD(vdup_lane_vector, buffer, , poly, p, 64, 1); + + TEST_VDUP_LANE(, poly, p, 64, 1, 1, 0); + TEST_VDUP_LANE(q, poly, p, 64, 2, 1, 0); + + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vdup_lane_expected, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vdup_lane_expected, ""); + + /* vdup_n_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VDUP/VDUPQ" + +#define TEST_VDUP(Q, T1, T2, W, N) \ + VECT_VAR(vdup_n_vector, T1, W, N) = \ + vdup##Q##_n_##T2##W(VECT_VAR(buffer_dup, T1, W, N)[i]); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vdup_n_vector, T1, W, N)) + + DECL_VARIABLE(vdup_n_vector, poly, 64, 1); + DECL_VARIABLE(vdup_n_vector, poly, 64, 2); + + /* Try to read different places from the input buffer. */ + for (i=0; i< 3; i++) { + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + TEST_VDUP(, poly, p, 64, 1); + TEST_VDUP(q, poly, p, 64, 2); + + switch (i) { + case 0: + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected0, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected0, ""); + break; + case 1: + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected1, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected1, ""); + break; + case 2: + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vdup_n_expected2, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vdup_n_expected2, ""); + break; + default: + abort(); + } + } + + /* vexit_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VEXT/VEXTQ" + +#define TEST_VEXT(Q, T1, T2, W, N, V) \ + VECT_VAR(vext_vector_res, T1, W, N) = \ + vext##Q##_##T2##W(VECT_VAR(vext_vector1, T1, W, N), \ + VECT_VAR(vext_vector2, T1, W, N), \ + V); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vext_vector_res, T1, W, N)) + + DECL_VARIABLE(vext_vector1, poly, 64, 1); + DECL_VARIABLE(vext_vector1, poly, 64, 2); + DECL_VARIABLE(vext_vector2, poly, 64, 1); + DECL_VARIABLE(vext_vector2, poly, 64, 2); + DECL_VARIABLE(vext_vector_res, poly, 64, 1); + DECL_VARIABLE(vext_vector_res, poly, 64, 2); + + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + VLOAD(vext_vector1, buffer, , poly, p, 64, 1); + VLOAD(vext_vector1, buffer, q, poly, p, 64, 2); + + VDUP(vext_vector2, , poly, p, 64, 1, 0x88); + VDUP(vext_vector2, q, poly, p, 64, 2, 0x88); + + TEST_VEXT(, poly, p, 64, 1, 0); + TEST_VEXT(q, poly, p, 64, 2, 1); + + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vext_expected, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vext_expected, ""); + + /* vget_low_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VGET_LOW" + +#define TEST_VGET_LOW(T1, T2, W, N, N2) \ + VECT_VAR(vget_low_vector64, T1, W, N) = \ + vget_low_##T2##W(VECT_VAR(vget_low_vector128, T1, W, N2)); \ + vst1_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vget_low_vector64, T1, W, N)) + + DECL_VARIABLE(vget_low_vector64, poly, 64, 1); + DECL_VARIABLE(vget_low_vector128, poly, 64, 2); + + CLEAN(result, poly, 64, 1); + + VLOAD(vget_low_vector128, buffer, q, poly, p, 64, 2); + + TEST_VGET_LOW(poly, p, 64, 1, 2); + + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vget_low_expected, ""); + + /* vld1_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VLD1/VLD1Q" + +#define TEST_VLD1(VAR, BUF, Q, T1, T2, W, N) \ + VECT_VAR(VAR, T1, W, N) = vld1##Q##_##T2##W(VECT_VAR(BUF, T1, W, N)); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(VAR, T1, W, N)) + + DECL_VARIABLE(vld1_vector, poly, 64, 1); + DECL_VARIABLE(vld1_vector, poly, 64, 2); + + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + VLOAD(vld1_vector, buffer, , poly, p, 64, 1); + VLOAD(vld1_vector, buffer, q, poly, p, 64, 2); + + TEST_VLD1(vld1_vector, buffer, , poly, p, 64, 1); + TEST_VLD1(vld1_vector, buffer, q, poly, p, 64, 2); + + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld1_expected, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vld1_expected, ""); + + /* vld1_dup_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VLD1_DUP/VLD1_DUPQ" + +#define TEST_VLD1_DUP(VAR, BUF, Q, T1, T2, W, N) \ + VECT_VAR(VAR, T1, W, N) = \ + vld1##Q##_dup_##T2##W(&VECT_VAR(BUF, T1, W, N)[i]); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(VAR, T1, W, N)) + + DECL_VARIABLE(vld1_dup_vector, poly, 64, 1); + DECL_VARIABLE(vld1_dup_vector, poly, 64, 2); + + /* Try to read different places from the input buffer. */ + for (i=0; i<3; i++) { + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + TEST_VLD1_DUP(vld1_dup_vector, buffer_dup, , poly, p, 64, 1); + TEST_VLD1_DUP(vld1_dup_vector, buffer_dup, q, poly, p, 64, 2); + + switch (i) { + case 0: + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected0, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected0, ""); + break; + case 1: + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected1, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected1, ""); + break; + case 2: + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld1_dup_expected2, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vld1_dup_expected2, ""); + break; + default: + abort(); + } + } + + /* vld1_lane_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VLD1_LANE/VLD1_LANEQ" + +#define TEST_VLD1_LANE(Q, T1, T2, W, N, L) \ + memset (VECT_VAR(vld1_lane_buffer_src, T1, W, N), 0xAA, W/8*N); \ + VECT_VAR(vld1_lane_vector_src, T1, W, N) = \ + vld1##Q##_##T2##W(VECT_VAR(vld1_lane_buffer_src, T1, W, N)); \ + VECT_VAR(vld1_lane_vector, T1, W, N) = \ + vld1##Q##_lane_##T2##W(VECT_VAR(buffer, T1, W, N), \ + VECT_VAR(vld1_lane_vector_src, T1, W, N), L); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vld1_lane_vector, T1, W, N)) + + DECL_VARIABLE(vld1_lane_vector, poly, 64, 1); + DECL_VARIABLE(vld1_lane_vector, poly, 64, 2); + DECL_VARIABLE(vld1_lane_vector_src, poly, 64, 1); + DECL_VARIABLE(vld1_lane_vector_src, poly, 64, 2); + + ARRAY(vld1_lane_buffer_src, poly, 64, 1); + ARRAY(vld1_lane_buffer_src, poly, 64, 2); + + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + TEST_VLD1_LANE(, poly, p, 64, 1, 0); + TEST_VLD1_LANE(q, poly, p, 64, 2, 0); + + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld1_lane_expected, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vld1_lane_expected, ""); + + /* vldX_p64 tests. */ +#define DECL_VLDX(T1, W, N, X) \ + VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vldX_vector, T1, W, N, X); \ + VECT_VAR_DECL(vldX_result_bis_##X, T1, W, N)[X * N] + +#define TEST_VLDX(Q, T1, T2, W, N, X) \ + VECT_ARRAY_VAR(vldX_vector, T1, W, N, X) = \ + /* Use dedicated init buffer, of size X */ \ + vld##X##Q##_##T2##W(VECT_ARRAY_VAR(buffer_vld##X, T1, W, N, X)); \ + vst##X##Q##_##T2##W(VECT_VAR(vldX_result_bis_##X, T1, W, N), \ + VECT_ARRAY_VAR(vldX_vector, T1, W, N, X)); \ + memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(vldX_result_bis_##X, T1, W, N), \ + sizeof(VECT_VAR(result, T1, W, N))); + + /* Overwrite "result" with the contents of "result_bis"[Y]. */ +#define TEST_EXTRA_CHUNK(T1, W, N, X,Y) \ + memcpy(VECT_VAR(result, T1, W, N), \ + &(VECT_VAR(vldX_result_bis_##X, T1, W, N)[Y*N]), \ + sizeof(VECT_VAR(result, T1, W, N))); + + DECL_VLDX(poly, 64, 1, 2); + DECL_VLDX(poly, 64, 1, 3); + DECL_VLDX(poly, 64, 1, 4); + + VECT_ARRAY_INIT2(buffer_vld2, poly, 64, 1); + PAD(buffer_vld2_pad, poly, 64, 1); + VECT_ARRAY_INIT3(buffer_vld3, poly, 64, 1); + PAD(buffer_vld3_pad, poly, 64, 1); + VECT_ARRAY_INIT4(buffer_vld4, poly, 64, 1); + PAD(buffer_vld4_pad, poly, 64, 1); + +#undef TEST_MSG +#define TEST_MSG "VLD2/VLD2Q" + CLEAN(result, poly, 64, 1); + TEST_VLDX(, poly, p, 64, 1, 2); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld2_expected_0, "chunk 0"); + CLEAN(result, poly, 64, 1); + TEST_EXTRA_CHUNK(poly, 64, 1, 2, 1); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld2_expected_1, "chunk 1"); + +#undef TEST_MSG +#define TEST_MSG "VLD3/VLD3Q" + CLEAN(result, poly, 64, 1); + TEST_VLDX(, poly, p, 64, 1, 3); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_0, "chunk 0"); + CLEAN(result, poly, 64, 1); + TEST_EXTRA_CHUNK(poly, 64, 1, 3, 1); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_1, "chunk 1"); + CLEAN(result, poly, 64, 1); + TEST_EXTRA_CHUNK(poly, 64, 1, 3, 2); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_expected_2, "chunk 2"); + +#undef TEST_MSG +#define TEST_MSG "VLD4/VLD4Q" + CLEAN(result, poly, 64, 1); + TEST_VLDX(, poly, p, 64, 1, 4); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_0, "chunk 0"); + CLEAN(result, poly, 64, 1); + TEST_EXTRA_CHUNK(poly, 64, 1, 4, 1); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_1, "chunk 1"); + CLEAN(result, poly, 64, 1); + TEST_EXTRA_CHUNK(poly, 64, 1, 4, 2); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_2, "chunk 2"); + CLEAN(result, poly, 64, 1); + TEST_EXTRA_CHUNK(poly, 64, 1, 4, 3); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_expected_3, "chunk 3"); + + /* vldX_dup_p64 tests. */ +#define DECL_VLDX_DUP(T1, W, N, X) \ + VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X); \ + VECT_VAR_DECL(vldX_dup_result_bis_##X, T1, W, N)[X * N] + +#define TEST_VLDX_DUP(Q, T1, T2, W, N, X) \ + VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X) = \ + vld##X##Q##_dup_##T2##W(&VECT_VAR(buffer_dup, T1, W, N)[0]); \ + \ + vst##X##Q##_##T2##W(VECT_VAR(vldX_dup_result_bis_##X, T1, W, N), \ + VECT_ARRAY_VAR(vldX_dup_vector, T1, W, N, X)); \ + memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(vldX_dup_result_bis_##X, T1, W, N), \ + sizeof(VECT_VAR(result, T1, W, N))); + + /* Overwrite "result" with the contents of "result_bis"[Y]. */ +#define TEST_VLDX_DUP_EXTRA_CHUNK(T1, W, N, X,Y) \ + memcpy(VECT_VAR(result, T1, W, N), \ + &(VECT_VAR(vldX_dup_result_bis_##X, T1, W, N)[Y*N]), \ + sizeof(VECT_VAR(result, T1, W, N))); + + DECL_VLDX_DUP(poly, 64, 1, 2); + DECL_VLDX_DUP(poly, 64, 1, 3); + DECL_VLDX_DUP(poly, 64, 1, 4); + + +#undef TEST_MSG +#define TEST_MSG "VLD2_DUP/VLD2Q_DUP" + CLEAN(result, poly, 64, 1); + TEST_VLDX_DUP(, poly, p, 64, 1, 2); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld2_dup_expected_0, "chunk 0"); + CLEAN(result, poly, 64, 1); + TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 2, 1); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld2_dup_expected_1, "chunk 1"); + +#undef TEST_MSG +#define TEST_MSG "VLD3_DUP/VLD3Q_DUP" + CLEAN(result, poly, 64, 1); + TEST_VLDX_DUP(, poly, p, 64, 1, 3); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_0, "chunk 0"); + CLEAN(result, poly, 64, 1); + TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 3, 1); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_1, "chunk 1"); + CLEAN(result, poly, 64, 1); + TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 3, 2); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld3_dup_expected_2, "chunk 2"); + +#undef TEST_MSG +#define TEST_MSG "VLD4_DUP/VLD4Q_DUP" + CLEAN(result, poly, 64, 1); + TEST_VLDX_DUP(, poly, p, 64, 1, 4); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_0, "chunk 0"); + CLEAN(result, poly, 64, 1); + TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 1); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_1, "chunk 1"); + CLEAN(result, poly, 64, 1); + TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 2); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_2, "chunk 2"); + CLEAN(result, poly, 64, 1); + TEST_VLDX_DUP_EXTRA_CHUNK(poly, 64, 1, 4, 3); + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vld4_dup_expected_3, "chunk 3"); + + /* vsli_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VSLI" + +#define TEST_VSXI1(INSN, Q, T1, T2, W, N, V) \ + VECT_VAR(vsXi_vector_res, T1, W, N) = \ + INSN##Q##_n_##T2##W(VECT_VAR(vsXi_vector, T1, W, N), \ + VECT_VAR(vsXi_vector2, T1, W, N), \ + V); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vsXi_vector_res, T1, W, N)) + +#define TEST_VSXI(INSN, Q, T1, T2, W, N, V) \ + TEST_VSXI1(INSN, Q, T1, T2, W, N, V) + + DECL_VARIABLE(vsXi_vector, poly, 64, 1); + DECL_VARIABLE(vsXi_vector, poly, 64, 2); + DECL_VARIABLE(vsXi_vector2, poly, 64, 1); + DECL_VARIABLE(vsXi_vector2, poly, 64, 2); + DECL_VARIABLE(vsXi_vector_res, poly, 64, 1); + DECL_VARIABLE(vsXi_vector_res, poly, 64, 2); + + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + VLOAD(vsXi_vector, buffer, , poly, p, 64, 1); + VLOAD(vsXi_vector, buffer, q, poly, p, 64, 2); + + VDUP(vsXi_vector2, , poly, p, 64, 1, 2); + VDUP(vsXi_vector2, q, poly, p, 64, 2, 3); + + TEST_VSXI(vsli, , poly, p, 64, 1, 3); + TEST_VSXI(vsli, q, poly, p, 64, 2, 53); + + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vsli_expected, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vsli_expected, ""); + + /* Test cases with maximum shift amount. */ + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + TEST_VSXI(vsli, , poly, p, 64, 1, 63); + TEST_VSXI(vsli, q, poly, p, 64, 2, 63); + +#define COMMENT "(max shift amount)" + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vsli_expected_max_shift, COMMENT); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vsli_expected_max_shift, COMMENT); + + /* vsri_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VSRI" + + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + VLOAD(vsXi_vector, buffer, , poly, p, 64, 1); + VLOAD(vsXi_vector, buffer, q, poly, p, 64, 2); + + VDUP(vsXi_vector2, , poly, p, 64, 1, 2); + VDUP(vsXi_vector2, q, poly, p, 64, 2, 3); + + TEST_VSXI(vsri, , poly, p, 64, 1, 3); + TEST_VSXI(vsri, q, poly, p, 64, 2, 53); + + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vsri_expected, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vsri_expected, ""); + + /* Test cases with maximum shift amount. */ + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + TEST_VSXI(vsri, , poly, p, 64, 1, 64); + TEST_VSXI(vsri, q, poly, p, 64, 2, 64); + +#define COMMENT "(max shift amount)" + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vsri_expected_max_shift, COMMENT); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vsri_expected_max_shift, COMMENT); + + /* vst1_lane_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VST1_LANE/VST1_LANEQ" + +#define TEST_VST1_LANE(Q, T1, T2, W, N, L) \ + VECT_VAR(vst1_lane_vector, T1, W, N) = \ + vld1##Q##_##T2##W(VECT_VAR(buffer, T1, W, N)); \ + vst1##Q##_lane_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vst1_lane_vector, T1, W, N), L) + + DECL_VARIABLE(vst1_lane_vector, poly, 64, 1); + DECL_VARIABLE(vst1_lane_vector, poly, 64, 2); + + CLEAN(result, poly, 64, 1); + CLEAN(result, poly, 64, 2); + + TEST_VST1_LANE(, poly, p, 64, 1, 0); + TEST_VST1_LANE(q, poly, p, 64, 2, 0); + + CHECK(TEST_MSG, poly, 64, 1, PRIx64, vst1_lane_expected, ""); + CHECK(TEST_MSG, poly, 64, 2, PRIx64, vst1_lane_expected, ""); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms_vfma_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms_vfma_n.c new file mode 100644 index 00000000000..efa9b5f2ece --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfms_vfma_n.c @@ -0,0 +1,490 @@ +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#if defined(__aarch64__) && defined(__ARM_FEATURE_FMA) + +#define A0 123.4f +#define A1 -3.8f +#define A2 -29.4f +#define A3 (__builtin_inff ()) +#define A4 0.0f +#define A5 24.0f +#define A6 124.0f +#define A7 1024.0f + +#define B0 -5.8f +#define B1 -0.0f +#define B2 -10.8f +#define B3 10.0f +#define B4 23.4f +#define B5 -1234.8f +#define B6 8.9f +#define B7 4.0f + +#define E0 9.8f +#define E1 -1024.0f +#define E2 (-__builtin_inff ()) +#define E3 479.0f +float32_t elem0 = E0; +float32_t elem1 = E1; +float32_t elem2 = E2; +float32_t elem3 = E3; + +#define DA0 1231234.4 +#define DA1 -3.8 +#define DA2 -2980.4 +#define DA3 -5.8 +#define DA4 0.01123 +#define DA5 24.0 +#define DA6 124.12345 +#define DA7 1024.0 + +#define DB0 -5.8 +#define DB1 (__builtin_inf ()) +#define DB2 -105.8 +#define DB3 10.0 +#define DB4 (-__builtin_inf ()) +#define DB5 -1234.8 +#define DB6 848.9 +#define DB7 44444.0 + +#define DE0 9.8 +#define DE1 -1024.0 +#define DE2 105.8 +#define DE3 479.0 +float64_t delem0 = DE0; +float64_t delem1 = DE1; +float64_t delem2 = DE2; +float64_t delem3 = DE3; + +/* Expected results for vfms_n. */ + +VECT_VAR_DECL(expectedfms0, float, 32, 2) [] = {A0 + -B0 * E0, A1 + -B1 * E0}; +VECT_VAR_DECL(expectedfms1, float, 32, 2) [] = {A2 + -B2 * E1, A3 + -B3 * E1}; +VECT_VAR_DECL(expectedfms2, float, 32, 2) [] = {A4 + -B4 * E2, A5 + -B5 * E2}; +VECT_VAR_DECL(expectedfms3, float, 32, 2) [] = {A6 + -B6 * E3, A7 + -B7 * E3}; +VECT_VAR_DECL(expectedfma0, float, 32, 2) [] = {A0 + B0 * E0, A1 + B1 * E0}; +VECT_VAR_DECL(expectedfma1, float, 32, 2) [] = {A2 + B2 * E1, A3 + B3 * E1}; +VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; +VECT_VAR_DECL(expectedfma3, float, 32, 2) [] = {A6 + B6 * E3, A7 + B7 * E3}; + +hfloat32_t * VECT_VAR (expectedfms0_static, hfloat, 32, 2) = + (hfloat32_t *) VECT_VAR (expectedfms0, float, 32, 2); +hfloat32_t * VECT_VAR (expectedfms1_static, hfloat, 32, 2) = + (hfloat32_t *) VECT_VAR (expectedfms1, float, 32, 2); +hfloat32_t * VECT_VAR (expectedfms2_static, hfloat, 32, 2) = + (hfloat32_t *) VECT_VAR (expectedfms2, float, 32, 2); +hfloat32_t * VECT_VAR (expectedfms3_static, hfloat, 32, 2) = + (hfloat32_t *) VECT_VAR (expectedfms3, float, 32, 2); +hfloat32_t * VECT_VAR (expectedfma0_static, hfloat, 32, 2) = + (hfloat32_t *) VECT_VAR (expectedfma0, float, 32, 2); +hfloat32_t * VECT_VAR (expectedfma1_static, hfloat, 32, 2) = + (hfloat32_t *) VECT_VAR (expectedfma1, float, 32, 2); +hfloat32_t * VECT_VAR (expectedfma2_static, hfloat, 32, 2) = + (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2); +hfloat32_t * VECT_VAR (expectedfma3_static, hfloat, 32, 2) = + (hfloat32_t *) VECT_VAR (expectedfma3, float, 32, 2); + + +VECT_VAR_DECL(expectedfms0, float, 32, 4) [] = {A0 + -B0 * E0, A1 + -B1 * E0, + A2 + -B2 * E0, A3 + -B3 * E0}; +VECT_VAR_DECL(expectedfms1, float, 32, 4) [] = {A4 + -B4 * E1, A5 + -B5 * E1, + A6 + -B6 * E1, A7 + -B7 * E1}; +VECT_VAR_DECL(expectedfms2, float, 32, 4) [] = {A0 + -B0 * E2, A2 + -B2 * E2, + A4 + -B4 * E2, A6 + -B6 * E2}; +VECT_VAR_DECL(expectedfms3, float, 32, 4) [] = {A1 + -B1 * E3, A3 + -B3 * E3, + A5 + -B5 * E3, A7 + -B7 * E3}; +VECT_VAR_DECL(expectedfma0, float, 32, 4) [] = {A0 + B0 * E0, A1 + B1 * E0, + A2 + B2 * E0, A3 + B3 * E0}; +VECT_VAR_DECL(expectedfma1, float, 32, 4) [] = {A4 + B4 * E1, A5 + B5 * E1, + A6 + B6 * E1, A7 + B7 * E1}; +VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, + A4 + B4 * E2, A6 + B6 * E2}; +VECT_VAR_DECL(expectedfma3, float, 32, 4) [] = {A1 + B1 * E3, A3 + B3 * E3, + A5 + B5 * E3, A7 + B7 * E3}; + +hfloat32_t * VECT_VAR (expectedfms0_static, hfloat, 32, 4) = + (hfloat32_t *) VECT_VAR (expectedfms0, float, 32, 4); +hfloat32_t * VECT_VAR (expectedfms1_static, hfloat, 32, 4) = + (hfloat32_t *) VECT_VAR (expectedfms1, float, 32, 4); +hfloat32_t * VECT_VAR (expectedfms2_static, hfloat, 32, 4) = + (hfloat32_t *) VECT_VAR (expectedfms2, float, 32, 4); +hfloat32_t * VECT_VAR (expectedfms3_static, hfloat, 32, 4) = + (hfloat32_t *) VECT_VAR (expectedfms3, float, 32, 4); +hfloat32_t * VECT_VAR (expectedfma0_static, hfloat, 32, 4) = + (hfloat32_t *) VECT_VAR (expectedfma0, float, 32, 4); +hfloat32_t * VECT_VAR (expectedfma1_static, hfloat, 32, 4) = + (hfloat32_t *) VECT_VAR (expectedfma1, float, 32, 4); +hfloat32_t * VECT_VAR (expectedfma2_static, hfloat, 32, 4) = + (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4); +hfloat32_t * VECT_VAR (expectedfma3_static, hfloat, 32, 4) = + (hfloat32_t *) VECT_VAR (expectedfma3, float, 32, 4); + +VECT_VAR_DECL(expectedfms0, float, 64, 2) [] = {DA0 + -DB0 * DE0, + DA1 + -DB1 * DE0}; +VECT_VAR_DECL(expectedfms1, float, 64, 2) [] = {DA2 + -DB2 * DE1, + DA3 + -DB3 * DE1}; +VECT_VAR_DECL(expectedfms2, float, 64, 2) [] = {DA4 + -DB4 * DE2, + DA5 + -DB5 * DE2}; +VECT_VAR_DECL(expectedfms3, float, 64, 2) [] = {DA6 + -DB6 * DE3, + DA7 + -DB7 * DE3}; +VECT_VAR_DECL(expectedfma0, float, 64, 2) [] = {DA0 + DB0 * DE0, + DA1 + DB1 * DE0}; +VECT_VAR_DECL(expectedfma1, float, 64, 2) [] = {DA2 + DB2 * DE1, + DA3 + DB3 * DE1}; +VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, + DA5 + DB5 * DE2}; +VECT_VAR_DECL(expectedfma3, float, 64, 2) [] = {DA6 + DB6 * DE3, + DA7 + DB7 * DE3}; +hfloat64_t * VECT_VAR (expectedfms0_static, hfloat, 64, 2) = + (hfloat64_t *) VECT_VAR (expectedfms0, float, 64, 2); +hfloat64_t * VECT_VAR (expectedfms1_static, hfloat, 64, 2) = + (hfloat64_t *) VECT_VAR (expectedfms1, float, 64, 2); +hfloat64_t * VECT_VAR (expectedfms2_static, hfloat, 64, 2) = + (hfloat64_t *) VECT_VAR (expectedfms2, float, 64, 2); +hfloat64_t * VECT_VAR (expectedfms3_static, hfloat, 64, 2) = + (hfloat64_t *) VECT_VAR (expectedfms3, float, 64, 2); +hfloat64_t * VECT_VAR (expectedfma0_static, hfloat, 64, 2) = + (hfloat64_t *) VECT_VAR (expectedfma0, float, 64, 2); +hfloat64_t * VECT_VAR (expectedfma1_static, hfloat, 64, 2) = + (hfloat64_t *) VECT_VAR (expectedfma1, float, 64, 2); +hfloat64_t * VECT_VAR (expectedfma2_static, hfloat, 64, 2) = + (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2); +hfloat64_t * VECT_VAR (expectedfma3_static, hfloat, 64, 2) = + (hfloat64_t *) VECT_VAR (expectedfma3, float, 64, 2); + +VECT_VAR_DECL(expectedfms0, float, 64, 1) [] = {DA0 + -DB0 * DE0}; +VECT_VAR_DECL(expectedfms1, float, 64, 1) [] = {DA2 + -DB2 * DE1}; +VECT_VAR_DECL(expectedfms2, float, 64, 1) [] = {DA4 + -DB4 * DE2}; +VECT_VAR_DECL(expectedfms3, float, 64, 1) [] = {DA6 + -DB6 * DE3}; +VECT_VAR_DECL(expectedfma0, float, 64, 1) [] = {DA0 + DB0 * DE0}; +VECT_VAR_DECL(expectedfma1, float, 64, 1) [] = {DA2 + DB2 * DE1}; +VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; +VECT_VAR_DECL(expectedfma3, float, 64, 1) [] = {DA6 + DB6 * DE3}; + +hfloat64_t * VECT_VAR (expectedfms0_static, hfloat, 64, 1) = + (hfloat64_t *) VECT_VAR (expectedfms0, float, 64, 1); +hfloat64_t * VECT_VAR (expectedfms1_static, hfloat, 64, 1) = + (hfloat64_t *) VECT_VAR (expectedfms1, float, 64, 1); +hfloat64_t * VECT_VAR (expectedfms2_static, hfloat, 64, 1) = + (hfloat64_t *) VECT_VAR (expectedfms2, float, 64, 1); +hfloat64_t * VECT_VAR (expectedfms3_static, hfloat, 64, 1) = + (hfloat64_t *) VECT_VAR (expectedfms3, float, 64, 1); +hfloat64_t * VECT_VAR (expectedfma0_static, hfloat, 64, 1) = + (hfloat64_t *) VECT_VAR (expectedfma0, float, 64, 1); +hfloat64_t * VECT_VAR (expectedfma1_static, hfloat, 64, 1) = + (hfloat64_t *) VECT_VAR (expectedfma1, float, 64, 1); +hfloat64_t * VECT_VAR (expectedfma2_static, hfloat, 64, 1) = + (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1); +hfloat64_t * VECT_VAR (expectedfma3_static, hfloat, 64, 1) = + (hfloat64_t *) VECT_VAR (expectedfma3, float, 64, 1); + +void exec_vfma_vfms_n (void) +{ +#undef TEST_MSG +#define TEST_MSG "VFMS_VFMA_N (FP32)" + clean_results (); + + DECL_VARIABLE(vsrc_1, float, 32, 2); + DECL_VARIABLE(vsrc_2, float, 32, 2); + VECT_VAR_DECL (buf_src_1, float, 32, 2) [] = {A0, A1}; + VECT_VAR_DECL (buf_src_2, float, 32, 2) [] = {B0, B1}; + VLOAD (vsrc_1, buf_src_1, , float, f, 32, 2); + VLOAD (vsrc_2, buf_src_2, , float, f, 32, 2); + DECL_VARIABLE (vector_res, float, 32, 2) = + vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2), + VECT_VAR (vsrc_2, float, 32, 2), elem0); + vst1_f32 (VECT_VAR (result, float, 32, 2), + VECT_VAR (vector_res, float, 32, 2)); + CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms0_static, ""); + VECT_VAR (vector_res, float, 32, 2) = + vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2), + VECT_VAR (vsrc_2, float, 32, 2), elem0); + vst1_f32 (VECT_VAR (result, float, 32, 2), + VECT_VAR (vector_res, float, 32, 2)); + CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma0_static, ""); + + VECT_VAR_DECL (buf_src_3, float, 32, 2) [] = {A2, A3}; + VECT_VAR_DECL (buf_src_4, float, 32, 2) [] = {B2, B3}; + VLOAD (vsrc_1, buf_src_3, , float, f, 32, 2); + VLOAD (vsrc_2, buf_src_4, , float, f, 32, 2); + VECT_VAR (vector_res, float, 32, 2) = + vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2), + VECT_VAR (vsrc_2, float, 32, 2), elem1); + vst1_f32 (VECT_VAR (result, float, 32, 2), + VECT_VAR (vector_res, float, 32, 2)); + CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms1_static, ""); + VECT_VAR (vector_res, float, 32, 2) = + vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2), + VECT_VAR (vsrc_2, float, 32, 2), elem1); + vst1_f32 (VECT_VAR (result, float, 32, 2), + VECT_VAR (vector_res, float, 32, 2)); + CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma1_static, ""); + + VECT_VAR_DECL (buf_src_5, float, 32, 2) [] = {A4, A5}; + VECT_VAR_DECL (buf_src_6, float, 32, 2) [] = {B4, B5}; + VLOAD (vsrc_1, buf_src_5, , float, f, 32, 2); + VLOAD (vsrc_2, buf_src_6, , float, f, 32, 2); + VECT_VAR (vector_res, float, 32, 2) = + vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2), + VECT_VAR (vsrc_2, float, 32, 2), elem2); + vst1_f32 (VECT_VAR (result, float, 32, 2), + VECT_VAR (vector_res, float, 32, 2)); + CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms2_static, ""); + VECT_VAR (vector_res, float, 32, 2) = + vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2), + VECT_VAR (vsrc_2, float, 32, 2), elem2); + vst1_f32 (VECT_VAR (result, float, 32, 2), + VECT_VAR (vector_res, float, 32, 2)); + CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma2_static, ""); + + VECT_VAR_DECL (buf_src_7, float, 32, 2) [] = {A6, A7}; + VECT_VAR_DECL (buf_src_8, float, 32, 2) [] = {B6, B7}; + VLOAD (vsrc_1, buf_src_7, , float, f, 32, 2); + VLOAD (vsrc_2, buf_src_8, , float, f, 32, 2); + VECT_VAR (vector_res, float, 32, 2) = + vfms_n_f32 (VECT_VAR (vsrc_1, float, 32, 2), + VECT_VAR (vsrc_2, float, 32, 2), elem3); + vst1_f32 (VECT_VAR (result, float, 32, 2), + VECT_VAR (vector_res, float, 32, 2)); + CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfms3_static, ""); + VECT_VAR (vector_res, float, 32, 2) = + vfma_n_f32 (VECT_VAR (vsrc_1, float, 32, 2), + VECT_VAR (vsrc_2, float, 32, 2), elem3); + vst1_f32 (VECT_VAR (result, float, 32, 2), + VECT_VAR (vector_res, float, 32, 2)); + CHECK_FP (TEST_MSG, float, 32, 2, PRIx16, expectedfma3_static, ""); + +#undef TEST_MSG +#define TEST_MSG "VFMSQ_VFMAQ_N (FP32)" + clean_results (); + + DECL_VARIABLE(vsrc_1, float, 32, 4); + DECL_VARIABLE(vsrc_2, float, 32, 4); + VECT_VAR_DECL (buf_src_1, float, 32, 4) [] = {A0, A1, A2, A3}; + VECT_VAR_DECL (buf_src_2, float, 32, 4) [] = {B0, B1, B2, B3}; + VLOAD (vsrc_1, buf_src_1, q, float, f, 32, 4); + VLOAD (vsrc_2, buf_src_2, q, float, f, 32, 4); + DECL_VARIABLE (vector_res, float, 32, 4) = + vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4), + VECT_VAR (vsrc_2, float, 32, 4), elem0); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms0_static, ""); + VECT_VAR (vector_res, float, 32, 4) = + vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4), + VECT_VAR (vsrc_2, float, 32, 4), elem0); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma0_static, ""); + + VECT_VAR_DECL (buf_src_3, float, 32, 4) [] = {A4, A5, A6, A7}; + VECT_VAR_DECL (buf_src_4, float, 32, 4) [] = {B4, B5, B6, B7}; + VLOAD (vsrc_1, buf_src_3, q, float, f, 32, 4); + VLOAD (vsrc_2, buf_src_4, q, float, f, 32, 4); + VECT_VAR (vector_res, float, 32, 4) = + vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4), + VECT_VAR (vsrc_2, float, 32, 4), elem1); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms1_static, ""); + VECT_VAR (vector_res, float, 32, 4) = + vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4), + VECT_VAR (vsrc_2, float, 32, 4), elem1); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma1_static, ""); + + VECT_VAR_DECL (buf_src_5, float, 32, 4) [] = {A0, A2, A4, A6}; + VECT_VAR_DECL (buf_src_6, float, 32, 4) [] = {B0, B2, B4, B6}; + VLOAD (vsrc_1, buf_src_5, q, float, f, 32, 4); + VLOAD (vsrc_2, buf_src_6, q, float, f, 32, 4); + VECT_VAR (vector_res, float, 32, 4) = + vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4), + VECT_VAR (vsrc_2, float, 32, 4), elem2); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms2_static, ""); + VECT_VAR (vector_res, float, 32, 4) = + vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4), + VECT_VAR (vsrc_2, float, 32, 4), elem2); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma2_static, ""); + + VECT_VAR_DECL (buf_src_7, float, 32, 4) [] = {A1, A3, A5, A7}; + VECT_VAR_DECL (buf_src_8, float, 32, 4) [] = {B1, B3, B5, B7}; + VLOAD (vsrc_1, buf_src_7, q, float, f, 32, 4); + VLOAD (vsrc_2, buf_src_8, q, float, f, 32, 4); + VECT_VAR (vector_res, float, 32, 4) = + vfmsq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4), + VECT_VAR (vsrc_2, float, 32, 4), elem3); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfms3_static, ""); + VECT_VAR (vector_res, float, 32, 4) = + vfmaq_n_f32 (VECT_VAR (vsrc_1, float, 32, 4), + VECT_VAR (vsrc_2, float, 32, 4), elem3); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx16, expectedfma3_static, ""); + +#undef TEST_MSG +#define TEST_MSG "VFMSQ_VFMAQ_N (FP64)" + clean_results (); + + DECL_VARIABLE(vsrc_1, float, 64, 2); + DECL_VARIABLE(vsrc_2, float, 64, 2); + VECT_VAR_DECL (buf_src_1, float, 64, 2) [] = {DA0, DA1}; + VECT_VAR_DECL (buf_src_2, float, 64, 2) [] = {DB0, DB1}; + VLOAD (vsrc_1, buf_src_1, q, float, f, 64, 2); + VLOAD (vsrc_2, buf_src_2, q, float, f, 64, 2); + DECL_VARIABLE (vector_res, float, 64, 2) = + vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2), + VECT_VAR (vsrc_2, float, 64, 2), delem0); + vst1q_f64 (VECT_VAR (result, float, 64, 2), + VECT_VAR (vector_res, float, 64, 2)); + CHECK_FP (TEST_MSG, float, 64, 2, PRIx16, expectedfms0_static, ""); + VECT_VAR (vector_res, float, 64, 2) = + vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2), + VECT_VAR (vsrc_2, float, 64, 2), delem0); + vst1q_f64 (VECT_VAR (result, float, 64, 2), + VECT_VAR (vector_res, float, 64, 2)); + CHECK_FP (TEST_MSG, float, 64, 2, PRIx16, expectedfma0_static, ""); + + VECT_VAR_DECL (buf_src_3, float, 64, 2) [] = {DA2, DA3}; + VECT_VAR_DECL (buf_src_4, float, 64, 2) [] = {DB2, DB3}; + VLOAD (vsrc_1, buf_src_3, q, float, f, 64, 2); + VLOAD (vsrc_2, buf_src_4, q, float, f, 64, 2); + VECT_VAR (vector_res, float, 64, 2) = + vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2), + VECT_VAR (vsrc_2, float, 64, 2), delem1); + vst1q_f64 (VECT_VAR (result, float, 64, 2), + VECT_VAR (vector_res, float, 64, 2)); + CHECK_FP (TEST_MSG, float, 64, 2, PRIx16, expectedfms1_static, ""); + VECT_VAR (vector_res, float, 64, 2) = + vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2), + VECT_VAR (vsrc_2, float, 64, 2), delem1); + vst1q_f64 (VECT_VAR (result, float, 64, 2), + VECT_VAR (vector_res, float, 64, 2)); + CHECK_FP (TEST_MSG, float, 64, 2, PRIx16, expectedfma1_static, ""); + + VECT_VAR_DECL (buf_src_5, float, 64, 2) [] = {DA4, DA5}; + VECT_VAR_DECL (buf_src_6, float, 64, 2) [] = {DB4, DB5}; + VLOAD (vsrc_1, buf_src_5, q, float, f, 64, 2); + VLOAD (vsrc_2, buf_src_6, q, float, f, 64, 2); + VECT_VAR (vector_res, float, 64, 2) = + vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2), + VECT_VAR (vsrc_2, float, 64, 2), delem2); + vst1q_f64 (VECT_VAR (result, float, 64, 2), + VECT_VAR (vector_res, float, 64, 2)); + CHECK_FP (TEST_MSG, float, 64, 2, PRIx16, expectedfms2_static, ""); + VECT_VAR (vector_res, float, 64, 2) = + vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2), + VECT_VAR (vsrc_2, float, 64, 2), delem2); + vst1q_f64 (VECT_VAR (result, float, 64, 2), + VECT_VAR (vector_res, float, 64, 2)); + CHECK_FP (TEST_MSG, float, 64, 2, PRIx16, expectedfma2_static, ""); + + VECT_VAR_DECL (buf_src_7, float, 64, 2) [] = {DA6, DA7}; + VECT_VAR_DECL (buf_src_8, float, 64, 2) [] = {DB6, DB7}; + VLOAD (vsrc_1, buf_src_7, q, float, f, 64, 2); + VLOAD (vsrc_2, buf_src_8, q, float, f, 64, 2); + VECT_VAR (vector_res, float, 64, 2) = + vfmsq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2), + VECT_VAR (vsrc_2, float, 64, 2), delem3); + vst1q_f64 (VECT_VAR (result, float, 64, 2), + VECT_VAR (vector_res, float, 64, 2)); + CHECK_FP (TEST_MSG, float, 64, 2, PRIx16, expectedfms3_static, ""); + VECT_VAR (vector_res, float, 64, 2) = + vfmaq_n_f64 (VECT_VAR (vsrc_1, float, 64, 2), + VECT_VAR (vsrc_2, float, 64, 2), delem3); + vst1q_f64 (VECT_VAR (result, float, 64, 2), + VECT_VAR (vector_res, float, 64, 2)); + CHECK_FP (TEST_MSG, float, 64, 2, PRIx16, expectedfma3_static, ""); + +#undef TEST_MSG +#define TEST_MSG "VFMS_VFMA_N (FP64)" + clean_results (); + + DECL_VARIABLE(vsrc_1, float, 64, 1); + DECL_VARIABLE(vsrc_2, float, 64, 1); + VECT_VAR_DECL (buf_src_1, float, 64, 1) [] = {DA0}; + VECT_VAR_DECL (buf_src_2, float, 64, 1) [] = {DB0}; + VLOAD (vsrc_1, buf_src_1, , float, f, 64, 1); + VLOAD (vsrc_2, buf_src_2, , float, f, 64, 1); + DECL_VARIABLE (vector_res, float, 64, 1) = + vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1), + VECT_VAR (vsrc_2, float, 64, 1), delem0); + vst1_f64 (VECT_VAR (result, float, 64, 1), + VECT_VAR (vector_res, float, 64, 1)); + CHECK_FP (TEST_MSG, float, 64, 1, PRIx16, expectedfms0_static, ""); + VECT_VAR (vector_res, float, 64, 1) = + vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1), + VECT_VAR (vsrc_2, float, 64, 1), delem0); + vst1_f64 (VECT_VAR (result, float, 64, 1), + VECT_VAR (vector_res, float, 64, 1)); + CHECK_FP (TEST_MSG, float, 64, 1, PRIx16, expectedfma0_static, ""); + + VECT_VAR_DECL (buf_src_3, float, 64, 1) [] = {DA2}; + VECT_VAR_DECL (buf_src_4, float, 64, 1) [] = {DB2}; + VLOAD (vsrc_1, buf_src_3, , float, f, 64, 1); + VLOAD (vsrc_2, buf_src_4, , float, f, 64, 1); + VECT_VAR (vector_res, float, 64, 1) = + vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1), + VECT_VAR (vsrc_2, float, 64, 1), delem1); + vst1_f64 (VECT_VAR (result, float, 64, 1), + VECT_VAR (vector_res, float, 64, 1)); + CHECK_FP (TEST_MSG, float, 64, 1, PRIx16, expectedfms1_static, ""); + VECT_VAR (vector_res, float, 64, 1) = + vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1), + VECT_VAR (vsrc_2, float, 64, 1), delem1); + vst1_f64 (VECT_VAR (result, float, 64, 1), + VECT_VAR (vector_res, float, 64, 1)); + CHECK_FP (TEST_MSG, float, 64, 1, PRIx16, expectedfma1_static, ""); + + VECT_VAR_DECL (buf_src_5, float, 64, 1) [] = {DA4}; + VECT_VAR_DECL (buf_src_6, float, 64, 1) [] = {DB4}; + VLOAD (vsrc_1, buf_src_5, , float, f, 64, 1); + VLOAD (vsrc_2, buf_src_6, , float, f, 64, 1); + VECT_VAR (vector_res, float, 64, 1) = + vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1), + VECT_VAR (vsrc_2, float, 64, 1), delem2); + vst1_f64 (VECT_VAR (result, float, 64, 1), + VECT_VAR (vector_res, float, 64, 1)); + CHECK_FP (TEST_MSG, float, 64, 1, PRIx16, expectedfms2_static, ""); + VECT_VAR (vector_res, float, 64, 1) = + vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1), + VECT_VAR (vsrc_2, float, 64, 1), delem2); + vst1_f64 (VECT_VAR (result, float, 64, 1), + VECT_VAR (vector_res, float, 64, 1)); + CHECK_FP (TEST_MSG, float, 64, 1, PRIx16, expectedfma2_static, ""); + + VECT_VAR_DECL (buf_src_7, float, 64, 1) [] = {DA6}; + VECT_VAR_DECL (buf_src_8, float, 64, 1) [] = {DB6}; + VLOAD (vsrc_1, buf_src_7, , float, f, 64, 1); + VLOAD (vsrc_2, buf_src_8, , float, f, 64, 1); + VECT_VAR (vector_res, float, 64, 1) = + vfms_n_f64 (VECT_VAR (vsrc_1, float, 64, 1), + VECT_VAR (vsrc_2, float, 64, 1), delem3); + vst1_f64 (VECT_VAR (result, float, 64, 1), + VECT_VAR (vector_res, float, 64, 1)); + CHECK_FP (TEST_MSG, float, 64, 1, PRIx16, expectedfms3_static, ""); + VECT_VAR (vector_res, float, 64, 1) = + vfma_n_f64 (VECT_VAR (vsrc_1, float, 64, 1), + VECT_VAR (vsrc_2, float, 64, 1), delem3); + vst1_f64 (VECT_VAR (result, float, 64, 1), + VECT_VAR (vector_res, float, 64, 1)); + CHECK_FP (TEST_MSG, float, 64, 1, PRIx16, expectedfma3_static, ""); +} +#endif + +int +main (void) +{ +#if defined(__aarch64__) && defined(__ARM_FEATURE_FMA) + exec_vfma_vfms_n (); +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c new file mode 100644 index 00000000000..808641524c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c @@ -0,0 +1,166 @@ +/* This file contains tests for the vreinterpret *p128 intrinsics. */ + +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results: vreinterpretq_p128_*. */ +VECT_VAR_DECL(vreint_expected_q_p128_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0, + 0xfffefdfcfbfaf9f8 }; +VECT_VAR_DECL(vreint_expected_q_p128_s16,poly,64,2) [] = { 0xfff3fff2fff1fff0, + 0xfff7fff6fff5fff4 }; +VECT_VAR_DECL(vreint_expected_q_p128_s32,poly,64,2) [] = { 0xfffffff1fffffff0, + 0xfffffff3fffffff2 }; +VECT_VAR_DECL(vreint_expected_q_p128_s64,poly,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vreint_expected_q_p128_u8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0, + 0xfffefdfcfbfaf9f8 }; +VECT_VAR_DECL(vreint_expected_q_p128_u16,poly,64,2) [] = { 0xfff3fff2fff1fff0, + 0xfff7fff6fff5fff4 }; +VECT_VAR_DECL(vreint_expected_q_p128_u32,poly,64,2) [] = { 0xfffffff1fffffff0, + 0xfffffff3fffffff2 }; +VECT_VAR_DECL(vreint_expected_q_p128_u64,poly,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vreint_expected_q_p128_p8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0, + 0xfffefdfcfbfaf9f8 }; +VECT_VAR_DECL(vreint_expected_q_p128_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0, + 0xfff7fff6fff5fff4 }; +VECT_VAR_DECL(vreint_expected_q_p128_f32,poly,64,2) [] = { 0xc1700000c1800000, + 0xc1500000c1600000 }; +VECT_VAR_DECL(vreint_expected_q_p128_f16,poly,64,2) [] = { 0xca80cb00cb80cc00, + 0xc880c900c980ca00 }; + +/* Expected results: vreinterpretq_*_p128. */ +VECT_VAR_DECL(vreint_expected_q_s8_p128,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xf1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(vreint_expected_q_s16_p128,int,16,8) [] = { 0xfff0, 0xffff, + 0xffff, 0xffff, + 0xfff1, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL(vreint_expected_q_s32_p128,int,32,4) [] = { 0xfffffff0, 0xffffffff, + 0xfffffff1, 0xffffffff }; +VECT_VAR_DECL(vreint_expected_q_s64_p128,int,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vreint_expected_q_u8_p128,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xf1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(vreint_expected_q_u16_p128,uint,16,8) [] = { 0xfff0, 0xffff, + 0xffff, 0xffff, + 0xfff1, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL(vreint_expected_q_u32_p128,uint,32,4) [] = { 0xfffffff0, 0xffffffff, + 0xfffffff1, 0xffffffff }; +VECT_VAR_DECL(vreint_expected_q_u64_p128,uint,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vreint_expected_q_p8_p128,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xf1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(vreint_expected_q_p16_p128,poly,16,8) [] = { 0xfff0, 0xffff, + 0xffff, 0xffff, + 0xfff1, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL(vreint_expected_q_p64_p128,uint,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vreint_expected_q_f32_p128,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff, + 0xfffffff1, 0xffffffff }; +VECT_VAR_DECL(vreint_expected_q_f16_p128,hfloat,16,8) [] = { 0xfff0, 0xffff, + 0xffff, 0xffff, + 0xfff1, 0xffff, + 0xffff, 0xffff }; + +int main (void) +{ + DECL_VARIABLE_128BITS_VARIANTS(vreint_vector); + DECL_VARIABLE(vreint_vector, poly, 64, 2); + DECL_VARIABLE_128BITS_VARIANTS(vreint_vector_res); + DECL_VARIABLE(vreint_vector_res, poly, 64, 2); + + clean_results (); + + TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vreint_vector, buffer); + VLOAD(vreint_vector, buffer, q, poly, p, 64, 2); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VLOAD(vreint_vector, buffer, q, float, f, 16, 8); +#endif + VLOAD(vreint_vector, buffer, q, float, f, 32, 4); + + /* vreinterpretq_p128_* tests. */ +#undef TEST_MSG +#define TEST_MSG "VREINTERPRETQ_P128_*" + + /* Since there is no way to store a poly128_t value, convert to + poly64x2_t before storing. This means that we are not able to + test vreinterpretq_p128* alone, and that errors in + vreinterpretq_p64_p128 could compensate for errors in + vreinterpretq_p128*. */ +#define TEST_VREINTERPRET128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \ + VECT_VAR(vreint_vector_res, poly, 64, 2) = vreinterpretq_p64_p128( \ + vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS))); \ + vst1##Q##_##T2##64(VECT_VAR(result, poly, 64, 2), \ + VECT_VAR(vreint_vector_res, poly, 64, 2)); \ + CHECK(TEST_MSG, T1, 64, 2, PRIx##64, EXPECTED, ""); + + TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 8, 16, vreint_expected_q_p128_s8); + TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 16, 8, vreint_expected_q_p128_s16); + TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 32, 4, vreint_expected_q_p128_s32); + TEST_VREINTERPRET128(q, poly, p, 128, 1, int, s, 64, 2, vreint_expected_q_p128_s64); + TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 8, 16, vreint_expected_q_p128_u8); + TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 16, 8, vreint_expected_q_p128_u16); + TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 32, 4, vreint_expected_q_p128_u32); + TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 64, 2, vreint_expected_q_p128_u64); + TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 8, 16, vreint_expected_q_p128_p8); + TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 16, 8, vreint_expected_q_p128_p16); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 16, 8, vreint_expected_q_p128_f16); +#endif + TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 32, 4, vreint_expected_q_p128_f32); + + /* vreinterpretq_*_p128 tests. */ +#undef TEST_MSG +#define TEST_MSG "VREINTERPRETQ_*_P128" + + /* Since there is no way to load a poly128_t value, load a + poly64x2_t and convert it to poly128_t. This means that we are + not able to test vreinterpretq_*_p128 alone, and that errors in + vreinterpretq_p128_p64 could compensate for errors in + vreinterpretq_*_p128*. */ +#define TEST_VREINTERPRET_FROM_P128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \ + VECT_VAR(vreint_vector_res, T1, W, N) = \ + vreinterpret##Q##_##T2##W##_##TS2##WS( \ + vreinterpretq_p128_p64(VECT_VAR(vreint_vector, TS1, 64, 2))); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vreint_vector_res, T1, W, N)); \ + CHECK(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, ""); + +#define TEST_VREINTERPRET_FP_FROM_P128(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \ + VECT_VAR(vreint_vector_res, T1, W, N) = \ + vreinterpret##Q##_##T2##W##_##TS2##WS( \ + vreinterpretq_p128_p64(VECT_VAR(vreint_vector, TS1, 64, 2))); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vreint_vector_res, T1, W, N)); \ + CHECK_FP(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, ""); + + TEST_VREINTERPRET_FROM_P128(q, int, s, 8, 16, poly, p, 128, 1, vreint_expected_q_s8_p128); + TEST_VREINTERPRET_FROM_P128(q, int, s, 16, 8, poly, p, 128, 1, vreint_expected_q_s16_p128); + TEST_VREINTERPRET_FROM_P128(q, int, s, 32, 4, poly, p, 128, 1, vreint_expected_q_s32_p128); + TEST_VREINTERPRET_FROM_P128(q, int, s, 64, 2, poly, p, 128, 1, vreint_expected_q_s64_p128); + TEST_VREINTERPRET_FROM_P128(q, uint, u, 8, 16, poly, p, 128, 1, vreint_expected_q_u8_p128); + TEST_VREINTERPRET_FROM_P128(q, uint, u, 16, 8, poly, p, 128, 1, vreint_expected_q_u16_p128); + TEST_VREINTERPRET_FROM_P128(q, uint, u, 32, 4, poly, p, 128, 1, vreint_expected_q_u32_p128); + TEST_VREINTERPRET_FROM_P128(q, uint, u, 64, 2, poly, p, 128, 1, vreint_expected_q_u64_p128); + TEST_VREINTERPRET_FROM_P128(q, poly, p, 8, 16, poly, p, 128, 1, vreint_expected_q_p8_p128); + TEST_VREINTERPRET_FROM_P128(q, poly, p, 16, 8, poly, p, 128, 1, vreint_expected_q_p16_p128); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 16, 8, poly, p, 128, 1, vreint_expected_q_f16_p128); +#endif + TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 32, 4, poly, p, 128, 1, vreint_expected_q_f32_p128); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c new file mode 100644 index 00000000000..1d8cf9aa69f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c @@ -0,0 +1,212 @@ +/* This file contains tests for the vreinterpret *p64 intrinsics. */ + +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-add-options arm_crypto } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results: vreinterpret_p64_*. */ +VECT_VAR_DECL(vreint_expected_p64_s8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 }; +VECT_VAR_DECL(vreint_expected_p64_s16,poly,64,1) [] = { 0xfff3fff2fff1fff0 }; +VECT_VAR_DECL(vreint_expected_p64_s32,poly,64,1) [] = { 0xfffffff1fffffff0 }; +VECT_VAR_DECL(vreint_expected_p64_s64,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vreint_expected_p64_u8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 }; +VECT_VAR_DECL(vreint_expected_p64_u16,poly,64,1) [] = { 0xfff3fff2fff1fff0 }; +VECT_VAR_DECL(vreint_expected_p64_u32,poly,64,1) [] = { 0xfffffff1fffffff0 }; +VECT_VAR_DECL(vreint_expected_p64_u64,poly,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vreint_expected_p64_p8,poly,64,1) [] = { 0xf7f6f5f4f3f2f1f0 }; +VECT_VAR_DECL(vreint_expected_p64_p16,poly,64,1) [] = { 0xfff3fff2fff1fff0 }; +VECT_VAR_DECL(vreint_expected_p64_f32,poly,64,1) [] = { 0xc1700000c1800000 }; +VECT_VAR_DECL(vreint_expected_p64_f16,poly,64,1) [] = { 0xca80cb00cb80cc00 }; + +/* Expected results: vreinterpretq_p64_*. */ +VECT_VAR_DECL(vreint_expected_q_p64_s8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0, + 0xfffefdfcfbfaf9f8 }; +VECT_VAR_DECL(vreint_expected_q_p64_s16,poly,64,2) [] = { 0xfff3fff2fff1fff0, + 0xfff7fff6fff5fff4 }; +VECT_VAR_DECL(vreint_expected_q_p64_s32,poly,64,2) [] = { 0xfffffff1fffffff0, + 0xfffffff3fffffff2 }; +VECT_VAR_DECL(vreint_expected_q_p64_s64,poly,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vreint_expected_q_p64_u8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0, + 0xfffefdfcfbfaf9f8 }; +VECT_VAR_DECL(vreint_expected_q_p64_u16,poly,64,2) [] = { 0xfff3fff2fff1fff0, + 0xfff7fff6fff5fff4 }; +VECT_VAR_DECL(vreint_expected_q_p64_u32,poly,64,2) [] = { 0xfffffff1fffffff0, + 0xfffffff3fffffff2 }; +VECT_VAR_DECL(vreint_expected_q_p64_u64,poly,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vreint_expected_q_p64_p8,poly,64,2) [] = { 0xf7f6f5f4f3f2f1f0, + 0xfffefdfcfbfaf9f8 }; +VECT_VAR_DECL(vreint_expected_q_p64_p16,poly,64,2) [] = { 0xfff3fff2fff1fff0, + 0xfff7fff6fff5fff4 }; +VECT_VAR_DECL(vreint_expected_q_p64_f32,poly,64,2) [] = { 0xc1700000c1800000, + 0xc1500000c1600000 }; +VECT_VAR_DECL(vreint_expected_q_p64_f16,poly,64,2) [] = { 0xca80cb00cb80cc00, + 0xc880c900c980ca00 }; + +/* Expected results: vreinterpret_*_p64. */ +VECT_VAR_DECL(vreint_expected_s8_p64,int,8,8) [] = { 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(vreint_expected_s16_p64,int,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff }; +VECT_VAR_DECL(vreint_expected_s32_p64,int,32,2) [] = { 0xfffffff0, 0xffffffff }; +VECT_VAR_DECL(vreint_expected_s64_p64,int,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vreint_expected_u8_p64,uint,8,8) [] = { 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(vreint_expected_u16_p64,uint,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff }; +VECT_VAR_DECL(vreint_expected_u32_p64,uint,32,2) [] = { 0xfffffff0, 0xffffffff }; +VECT_VAR_DECL(vreint_expected_u64_p64,uint,64,1) [] = { 0xfffffffffffffff0 }; +VECT_VAR_DECL(vreint_expected_p8_p64,poly,8,8) [] = { 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(vreint_expected_p16_p64,poly,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff }; +VECT_VAR_DECL(vreint_expected_f32_p64,hfloat,32,2) [] = { 0xfffffff0, 0xffffffff }; +VECT_VAR_DECL(vreint_expected_f16_p64,hfloat,16,4) [] = { 0xfff0, 0xffff, 0xffff, 0xffff }; + +/* Expected results: vreinterpretq_*_p64. */ +VECT_VAR_DECL(vreint_expected_q_s8_p64,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xf1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(vreint_expected_q_s16_p64,int,16,8) [] = { 0xfff0, 0xffff, + 0xffff, 0xffff, + 0xfff1, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL(vreint_expected_q_s32_p64,int,32,4) [] = { 0xfffffff0, 0xffffffff, + 0xfffffff1, 0xffffffff }; +VECT_VAR_DECL(vreint_expected_q_s64_p64,int,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vreint_expected_q_u8_p64,uint,8,16) [] = { 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xf1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(vreint_expected_q_u16_p64,uint,16,8) [] = { 0xfff0, 0xffff, + 0xffff, 0xffff, + 0xfff1, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL(vreint_expected_q_u32_p64,uint,32,4) [] = { 0xfffffff0, 0xffffffff, + 0xfffffff1, 0xffffffff }; +VECT_VAR_DECL(vreint_expected_q_u64_p64,uint,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(vreint_expected_q_p8_p64,poly,8,16) [] = { 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xf1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(vreint_expected_q_p16_p64,poly,16,8) [] = { 0xfff0, 0xffff, + 0xffff, 0xffff, + 0xfff1, 0xffff, + 0xffff, 0xffff }; +VECT_VAR_DECL(vreint_expected_q_f32_p64,hfloat,32,4) [] = { 0xfffffff0, 0xffffffff, + 0xfffffff1, 0xffffffff }; +VECT_VAR_DECL(vreint_expected_q_f16_p64,hfloat,16,8) [] = { 0xfff0, 0xffff, + 0xffff, 0xffff, + 0xfff1, 0xffff, + 0xffff, 0xffff }; + +int main (void) +{ +#define TEST_VREINTERPRET(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \ + VECT_VAR(vreint_vector_res, T1, W, N) = \ + vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS)); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vreint_vector_res, T1, W, N)); \ + CHECK(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, ""); + +#define TEST_VREINTERPRET_FP(Q, T1, T2, W, N, TS1, TS2, WS, NS, EXPECTED) \ + VECT_VAR(vreint_vector_res, T1, W, N) = \ + vreinterpret##Q##_##T2##W##_##TS2##WS(VECT_VAR(vreint_vector, TS1, WS, NS)); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vreint_vector_res, T1, W, N)); \ + CHECK_FP(TEST_MSG, T1, W, N, PRIx##W, EXPECTED, ""); + + DECL_VARIABLE_ALL_VARIANTS(vreint_vector); + DECL_VARIABLE(vreint_vector, poly, 64, 1); + DECL_VARIABLE(vreint_vector, poly, 64, 2); + DECL_VARIABLE_ALL_VARIANTS(vreint_vector_res); + DECL_VARIABLE(vreint_vector_res, poly, 64, 1); + DECL_VARIABLE(vreint_vector_res, poly, 64, 2); + + clean_results (); + + TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vreint_vector, buffer); + VLOAD(vreint_vector, buffer, , poly, p, 64, 1); + VLOAD(vreint_vector, buffer, q, poly, p, 64, 2); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VLOAD(vreint_vector, buffer, , float, f, 16, 4); + VLOAD(vreint_vector, buffer, q, float, f, 16, 8); +#endif + VLOAD(vreint_vector, buffer, , float, f, 32, 2); + VLOAD(vreint_vector, buffer, q, float, f, 32, 4); + + /* vreinterpret_p64_* tests. */ +#undef TEST_MSG +#define TEST_MSG "VREINTERPRET_P64_*" + TEST_VREINTERPRET(, poly, p, 64, 1, int, s, 8, 8, vreint_expected_p64_s8); + TEST_VREINTERPRET(, poly, p, 64, 1, int, s, 16, 4, vreint_expected_p64_s16); + TEST_VREINTERPRET(, poly, p, 64, 1, int, s, 32, 2, vreint_expected_p64_s32); + TEST_VREINTERPRET(, poly, p, 64, 1, int, s, 64, 1, vreint_expected_p64_s64); + TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 8, 8, vreint_expected_p64_u8); + TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 16, 4, vreint_expected_p64_u16); + TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 32, 2, vreint_expected_p64_u32); + TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 64, 1, vreint_expected_p64_u64); + TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 8, 8, vreint_expected_p64_p8); + TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 16, 4, vreint_expected_p64_p16); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 16, 4, vreint_expected_p64_f16); +#endif + TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 32, 2, vreint_expected_p64_f32); + + /* vreinterpretq_p64_* tests. */ +#undef TEST_MSG +#define TEST_MSG "VREINTERPRETQ_P64_*" + TEST_VREINTERPRET(q, poly, p, 64, 2, int, s, 8, 16, vreint_expected_q_p64_s8); + TEST_VREINTERPRET(q, poly, p, 64, 2, int, s, 16, 8, vreint_expected_q_p64_s16); + TEST_VREINTERPRET(q, poly, p, 64, 2, int, s, 32, 4, vreint_expected_q_p64_s32); + TEST_VREINTERPRET(q, poly, p, 64, 2, int, s, 64, 2, vreint_expected_q_p64_s64); + TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 8, 16, vreint_expected_q_p64_u8); + TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 16, 8, vreint_expected_q_p64_u16); + TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 32, 4, vreint_expected_q_p64_u32); + TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 64, 2, vreint_expected_q_p64_u64); + TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 8, 16, vreint_expected_q_p64_p8); + TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 16, 8, vreint_expected_q_p64_p16); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 16, 8, vreint_expected_q_p64_f16); +#endif + TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 32, 4, vreint_expected_q_p64_f32); + + /* vreinterpret_*_p64 tests. */ +#undef TEST_MSG +#define TEST_MSG "VREINTERPRET_*_P64" + + TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 64, 1, vreint_expected_s8_p64); + TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 64, 1, vreint_expected_s16_p64); + TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 64, 1, vreint_expected_s32_p64); + TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 64, 1, vreint_expected_s64_p64); + TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 64, 1, vreint_expected_u8_p64); + TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 64, 1, vreint_expected_u16_p64); + TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 64, 1, vreint_expected_u32_p64); + TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 64, 1, vreint_expected_u64_p64); + TEST_VREINTERPRET(, poly, p, 8, 8, poly, p, 64, 1, vreint_expected_p8_p64); + TEST_VREINTERPRET(, poly, p, 16, 4, poly, p, 64, 1, vreint_expected_p16_p64); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 64, 1, vreint_expected_f16_p64); +#endif + TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 64, 1, vreint_expected_f32_p64); + TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 64, 2, vreint_expected_q_s8_p64); + TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 64, 2, vreint_expected_q_s16_p64); + TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 64, 2, vreint_expected_q_s32_p64); + TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 64, 2, vreint_expected_q_s64_p64); + TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 64, 2, vreint_expected_q_u8_p64); + TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 64, 2, vreint_expected_q_u16_p64); + TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 64, 2, vreint_expected_q_u32_p64); + TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 64, 2, vreint_expected_q_u64_p64); + TEST_VREINTERPRET(q, poly, p, 8, 16, poly, p, 64, 2, vreint_expected_q_p8_p64); + TEST_VREINTERPRET(q, poly, p, 16, 8, poly, p, 64, 2, vreint_expected_q_p16_p64); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 64, 2, vreint_expected_q_f16_p64); +#endif + TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 64, 2, vreint_expected_q_f32_p64); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c new file mode 100644 index 00000000000..d97a3a25ee5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_hw } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrnd +#define TEST_MSG "VRND" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc new file mode 100644 index 00000000000..629240d3a23 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc @@ -0,0 +1,43 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1 (NAME) + +void FNNAME (INSN) (void) +{ + /* vector_res = vrndX (vector), then store the result. */ +#define TEST_VRND2(INSN, Q, T1, T2, W, N) \ + VECT_VAR (vector_res, T1, W, N) = \ + INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N)); \ + vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N), \ + VECT_VAR (vector_res, T1, W, N)) + + /* Two auxliary macros are necessary to expand INSN. */ +#define TEST_VRND1(INSN, Q, T1, T2, W, N) \ + TEST_VRND2 (INSN, Q, T1, T2, W, N) + +#define TEST_VRND(Q, T1, T2, W, N) \ + TEST_VRND1 (INSN, Q, T1, T2, W, N) + + DECL_VARIABLE (vector, float, 32, 2); + DECL_VARIABLE (vector, float, 32, 4); + + DECL_VARIABLE (vector_res, float, 32, 2); + DECL_VARIABLE (vector_res, float, 32, 4); + + clean_results (); + + VLOAD (vector, buffer, , float, f, 32, 2); + VLOAD (vector, buffer, q, float, f, 32, 4); + + TEST_VRND ( , float, f, 32, 2); + TEST_VRND (q, float, f, 32, 4); + + CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, ""); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, ""); +} + +int +main (void) +{ + FNNAME (INSN) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c new file mode 100644 index 00000000000..ff2bdc0563f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_hw } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrnda +#define TEST_MSG "VRNDA" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c new file mode 100644 index 00000000000..eae9f61c585 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_hw } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrndm +#define TEST_MSG "VRNDM" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c new file mode 100644 index 00000000000..c6c707d6765 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_hw } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrndn +#define TEST_MSG "VRNDN" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c new file mode 100644 index 00000000000..e94eb6b7622 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_hw } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrndp +#define TEST_MSG "VRNDP" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c new file mode 100644 index 00000000000..0d2a63ef26c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_hw } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrndx +#define TEST_MSG "VRNDX" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/ands_3.c b/gcc/testsuite/gcc.target/aarch64/ands_3.c new file mode 100644 index 00000000000..42cb7f0f0bc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ands_3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +f9 (unsigned char x, int y) +{ + if (y > 1 && x == 0) + return 10; + return x; +} + +/* { dg-final { scan-assembler "ands\t(x|w)\[0-9\]+,\[ \t\]*(x|w)\[0-9\]+,\[ \t\]*255" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_subreg_1.c b/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_subreg_1.c new file mode 100644 index 00000000000..ac6ffdcf8de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_subreg_1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-rtl-ce1" } */ + +/* Check that the inner if is transformed into CSELs. */ + +int +foo (int *x, int *z, int a) +{ + int b = 0; + int c = 0; + int d = 0; + int i; + + for (i = 0; i < a; i++) + { + if (x[i] < c) + { + b = z[i]; + if (c < b) + { + c = b; + d = i; + } + } + } + + return c + d; +} + +/* { dg-final { scan-rtl-dump "if-conversion succeeded through noce_convert_multiple_sets" "ce1" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_1.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_1.c new file mode 100644 index 00000000000..a70f92100fb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_1.c @@ -0,0 +1,20 @@ +/* { dg-options "-O2" } */ + +/* Check that we can use a REG + IMM addressing mode when moving an unaligned + TImode value to and from memory. */ + +struct foo +{ + long long b; + __int128 a; +} __attribute__ ((packed)); + +void +bar (struct foo *p, struct foo *q) +{ + p->a = q->a; +} + +/* { dg-final { scan-assembler-not "add\tx\[0-9\]+, x\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "ldp\tx\[0-9\]+, x\[0-9\], .*8" 1 } } */ +/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\], .*8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr37780_1.c b/gcc/testsuite/gcc.target/aarch64/pr37780_1.c new file mode 100644 index 00000000000..97027e7479c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr37780_1.c @@ -0,0 +1,46 @@ +/* Test that we can remove the conditional move due to CLZ + and CTZ being defined at zero. */ + +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +fooctz (int i) +{ + return (i == 0) ? 32 : __builtin_ctz (i); +} + +int +fooctz2 (int i) +{ + return (i != 0) ? __builtin_ctz (i) : 32; +} + +unsigned int +fooctz3 (unsigned int i) +{ + return (i > 0) ? __builtin_ctz (i) : 32; +} + +/* { dg-final { scan-assembler-times "rbit\t*" 3 } } */ + +int +fooclz (int i) +{ + return (i == 0) ? 32 : __builtin_clz (i); +} + +int +fooclz2 (int i) +{ + return (i != 0) ? __builtin_clz (i) : 32; +} + +unsigned int +fooclz3 (unsigned int i) +{ + return (i > 0) ? __builtin_clz (i) : 32; +} + +/* { dg-final { scan-assembler-times "clz\t" 6 } } */ +/* { dg-final { scan-assembler-not "cmp\t.*0" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr63874.c b/gcc/testsuite/gcc.target/aarch64/pr63874.c new file mode 100644 index 00000000000..1a745a038a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr63874.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "Not applicable for mcmodel=large" { aarch64*-*-* } { "-mcmodel=large" } { "" } } */ + +extern void __attribute__((weak)) foo_weakref (void); +void __attribute__((weak, noinline)) bar (void) +{ + return; +} +void (*f) (void); +void (*g) (void); + +int +main (void) +{ + f = &foo_weakref; + g = &bar; + return 0; +} + +/* { dg-final { scan-assembler-not "adr*foo_weakref" } } */ +/* { dg-final { scan-assembler-not "\\.(word|xword)\tbar" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr70809_1.c b/gcc/testsuite/gcc.target/aarch64/pr70809_1.c new file mode 100644 index 00000000000..df88c71c42a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr70809_1.c @@ -0,0 +1,18 @@ +/* PR target/70809. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -ffp-contract=off -mtune=xgene1" } */ + +/* Check that vector FMLS is not generated when contraction is disabled. */ + +void +foo (float *__restrict__ __attribute__ ((aligned (16))) a, + float *__restrict__ __attribute__ ((aligned (16))) x, + float *__restrict__ __attribute__ ((aligned (16))) y, + float *__restrict__ __attribute__ ((aligned (16))) z) +{ + unsigned i = 0; + for (i = 0; i < 256; i++) + a[i] = x[i] - (y[i] * z[i]); +} + +/* { dg-final { scan-assembler-not "fmls\tv.*" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c new file mode 100644 index 00000000000..192bad9879b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c @@ -0,0 +1,127 @@ +/* Test the `v[min|max]{nm}{q}_f*' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include "arm_neon.h" + +extern void abort (); + +#define CHECK(T, N, R, E) \ + {\ + int i = 0;\ + for (; i < N; i++)\ + if (* (T *) &R[i] != * (T *) &E[i])\ + abort ();\ + } + +int +main (int argc, char **argv) +{ + /* v{min|max}nm_f32 normal. */ + float32x2_t f32x2_input1 = vdup_n_f32 (-1.0); + float32x2_t f32x2_input2 = vdup_n_f32 (0.0); + float32x2_t f32x2_exp_minnm = vdup_n_f32 (-1.0); + float32x2_t f32x2_exp_maxnm = vdup_n_f32 (0.0); + float32x2_t f32x2_ret_minnm = vminnm_f32 (f32x2_input1, f32x2_input2); + float32x2_t f32x2_ret_maxnm = vmaxnm_f32 (f32x2_input1, f32x2_input2); + + CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm); + CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm); + + /* v{min|max}nm_f32 NaN. */ + f32x2_input1 = vdup_n_f32 (__builtin_nanf ("")); + f32x2_input2 = vdup_n_f32 (1.0); + f32x2_exp_minnm = vdup_n_f32 (1.0); + f32x2_exp_maxnm = vdup_n_f32 (1.0); + f32x2_ret_minnm = vminnm_f32 (f32x2_input1, f32x2_input2); + f32x2_ret_maxnm = vmaxnm_f32 (f32x2_input1, f32x2_input2); + + CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm); + CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm); + + /* v{min|max}nmq_f32 normal. */ + float32x4_t f32x4_input1 = vdupq_n_f32 (-1024.0); + float32x4_t f32x4_input2 = vdupq_n_f32 (77.0); + float32x4_t f32x4_exp_minnm = vdupq_n_f32 (-1024.0); + float32x4_t f32x4_exp_maxnm = vdupq_n_f32 (77.0); + float32x4_t f32x4_ret_minnm = vminnmq_f32 (f32x4_input1, f32x4_input2); + float32x4_t f32x4_ret_maxnm = vmaxnmq_f32 (f32x4_input1, f32x4_input2); + + CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm); + CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm); + + /* v{min|max}nmq_f32 NaN. */ + f32x4_input1 = vdupq_n_f32 (-__builtin_nanf ("")); + f32x4_input2 = vdupq_n_f32 (-1.0); + f32x4_exp_minnm = vdupq_n_f32 (-1.0); + f32x4_exp_maxnm = vdupq_n_f32 (-1.0); + f32x4_ret_minnm = vminnmq_f32 (f32x4_input1, f32x4_input2); + f32x4_ret_maxnm = vmaxnmq_f32 (f32x4_input1, f32x4_input2); + + CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm); + CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm); + + /* v{min|max}nm_f64 normal. */ + float64x1_t f64x1_input1 = vdup_n_f64 (1.23); + float64x1_t f64x1_input2 = vdup_n_f64 (4.56); + float64x1_t f64x1_exp_minnm = vdup_n_f64 (1.23); + float64x1_t f64x1_exp_maxnm = vdup_n_f64 (4.56); + float64x1_t f64x1_ret_minnm = vminnm_f64 (f64x1_input1, f64x1_input2); + float64x1_t f64x1_ret_maxnm = vmaxnm_f64 (f64x1_input1, f64x1_input2); + CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm); + CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm); + + /* v{min|max}_f64 normal. */ + float64x1_t f64x1_exp_min = vdup_n_f64 (1.23); + float64x1_t f64x1_exp_max = vdup_n_f64 (4.56); + float64x1_t f64x1_ret_min = vmin_f64 (f64x1_input1, f64x1_input2); + float64x1_t f64x1_ret_max = vmax_f64 (f64x1_input1, f64x1_input2); + CHECK (uint64_t, 1, f64x1_ret_min, f64x1_exp_min); + CHECK (uint64_t, 1, f64x1_ret_max, f64x1_exp_max); + + /* v{min|max}nmq_f64 normal. */ + float64x2_t f64x2_input1 = vdupq_n_f64 (1.23); + float64x2_t f64x2_input2 = vdupq_n_f64 (4.56); + float64x2_t f64x2_exp_minnm = vdupq_n_f64 (1.23); + float64x2_t f64x2_exp_maxnm = vdupq_n_f64 (4.56); + float64x2_t f64x2_ret_minnm = vminnmq_f64 (f64x2_input1, f64x2_input2); + float64x2_t f64x2_ret_maxnm = vmaxnmq_f64 (f64x2_input1, f64x2_input2); + CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm); + CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm); + + /* v{min|max}nm_f64 NaN. */ + f64x1_input1 = vdup_n_f64 (-__builtin_nanf ("")); + f64x1_input2 = vdup_n_f64 (1.0); + f64x1_exp_minnm = vdup_n_f64 (1.0); + f64x1_exp_maxnm = vdup_n_f64 (1.0); + f64x1_ret_minnm = vminnm_f64 (f64x1_input1, f64x1_input2); + f64x1_ret_maxnm = vmaxnm_f64 (f64x1_input1, f64x1_input2); + + CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm); + CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm); + + /* v{min|max}_f64 NaN. */ + f64x1_input1 = vdup_n_f64 (-__builtin_nanf ("")); + f64x1_input2 = vdup_n_f64 (1.0); + f64x1_exp_minnm = vdup_n_f64 (-__builtin_nanf ("")); + f64x1_exp_maxnm = vdup_n_f64 (-__builtin_nanf ("")); + f64x1_ret_minnm = vmin_f64 (f64x1_input1, f64x1_input2); + f64x1_ret_maxnm = vmax_f64 (f64x1_input1, f64x1_input2); + + CHECK (uint64_t, 1, f64x1_ret_minnm, f64x1_exp_minnm); + CHECK (uint64_t, 1, f64x1_ret_maxnm, f64x1_exp_maxnm); + + /* v{min|max}nmq_f64 NaN. */ + f64x2_input1 = vdupq_n_f64 (-__builtin_nan ("")); + f64x2_input2 = vdupq_n_f64 (1.0); + f64x2_exp_minnm = vdupq_n_f64 (1.0); + f64x2_exp_maxnm = vdupq_n_f64 (1.0); + f64x2_ret_minnm = vminnmq_f64 (f64x2_input1, f64x2_input2); + f64x2_ret_maxnm = vmaxnmq_f64 (f64x2_input1, f64x2_input2); + + CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm); + CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vmul_elem_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vmul_elem_1.c new file mode 100644 index 00000000000..a1faefd88ba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vmul_elem_1.c @@ -0,0 +1,541 @@ +/* Test the vmul_n_f64 AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps" } */ + +#include "arm_neon.h" + +extern void abort (void); + +#define A (132.4f) +#define B (-0.0f) +#define C (-34.8f) +#define D (289.34f) +float32_t expected2_1[2] = {A * A, B * A}; +float32_t expected2_2[2] = {A * B, B * B}; +float32_t expected4_1[4] = {A * A, B * A, C * A, D * A}; +float32_t expected4_2[4] = {A * B, B * B, C * B, D * B}; +float32_t expected4_3[4] = {A * C, B * C, C * C, D * C}; +float32_t expected4_4[4] = {A * D, B * D, C * D, D * D}; +float32_t _elemA = A; +float32_t _elemB = B; +float32_t _elemC = C; +float32_t _elemD = D; + +#define AD (1234.5) +#define BD (-0.0) +#define CD (71.3) +#define DD (-1024.4) +float64_t expectedd2_1[2] = {AD * CD, BD * CD}; +float64_t expectedd2_2[2] = {AD * DD, BD * DD}; +float64_t _elemdC = CD; +float64_t _elemdD = DD; + + +#define AS (1024) +#define BS (-31) +#define CS (0) +#define DS (655) +int32_t expecteds2_1[2] = {AS * AS, BS * AS}; +int32_t expecteds2_2[2] = {AS * BS, BS * BS}; +int32_t expecteds4_1[4] = {AS * AS, BS * AS, CS * AS, DS * AS}; +int32_t expecteds4_2[4] = {AS * BS, BS * BS, CS * BS, DS * BS}; +int32_t expecteds4_3[4] = {AS * CS, BS * CS, CS * CS, DS * CS}; +int32_t expecteds4_4[4] = {AS * DS, BS * DS, CS * DS, DS * DS}; +int32_t _elemsA = AS; +int32_t _elemsB = BS; +int32_t _elemsC = CS; +int32_t _elemsD = DS; + +#define AH ((int16_t) 0) +#define BH ((int16_t) -32) +#define CH ((int16_t) 102) +#define DH ((int16_t) -51) +#define EH ((int16_t) 71) +#define FH ((int16_t) -91) +#define GH ((int16_t) 48) +#define HH ((int16_t) 255) +int16_t expectedh4_1[4] = {AH * AH, BH * AH, CH * AH, DH * AH}; +int16_t expectedh4_2[4] = {AH * BH, BH * BH, CH * BH, DH * BH}; +int16_t expectedh4_3[4] = {AH * CH, BH * CH, CH * CH, DH * CH}; +int16_t expectedh4_4[4] = {AH * DH, BH * DH, CH * DH, DH * DH}; +int16_t expectedh8_1[8] = {AH * AH, BH * AH, CH * AH, DH * AH, + EH * AH, FH * AH, GH * AH, HH * AH}; +int16_t expectedh8_2[8] = {AH * BH, BH * BH, CH * BH, DH * BH, + EH * BH, FH * BH, GH * BH, HH * BH}; +int16_t expectedh8_3[8] = {AH * CH, BH * CH, CH * CH, DH * CH, + EH * CH, FH * CH, GH * CH, HH * CH}; +int16_t expectedh8_4[8] = {AH * DH, BH * DH, CH * DH, DH * DH, + EH * DH, FH * DH, GH * DH, HH * DH}; +int16_t expectedh8_5[8] = {AH * EH, BH * EH, CH * EH, DH * EH, + EH * EH, FH * EH, GH * EH, HH * EH}; +int16_t expectedh8_6[8] = {AH * FH, BH * FH, CH * FH, DH * FH, + EH * FH, FH * FH, GH * FH, HH * FH}; +int16_t expectedh8_7[8] = {AH * GH, BH * GH, CH * GH, DH * GH, + EH * GH, FH * GH, GH * GH, HH * GH}; +int16_t expectedh8_8[8] = {AH * HH, BH * HH, CH * HH, DH * HH, + EH * HH, FH * HH, GH * HH, HH * HH}; +int16_t _elemhA = AH; +int16_t _elemhB = BH; +int16_t _elemhC = CH; +int16_t _elemhD = DH; +int16_t _elemhE = EH; +int16_t _elemhF = FH; +int16_t _elemhG = GH; +int16_t _elemhH = HH; + +#define AUS (1024) +#define BUS (31) +#define CUS (0) +#define DUS (655) +uint32_t expectedus2_1[2] = {AUS * AUS, BUS * AUS}; +uint32_t expectedus2_2[2] = {AUS * BUS, BUS * BUS}; +uint32_t expectedus4_1[4] = {AUS * AUS, BUS * AUS, CUS * AUS, DUS * AUS}; +uint32_t expectedus4_2[4] = {AUS * BUS, BUS * BUS, CUS * BUS, DUS * BUS}; +uint32_t expectedus4_3[4] = {AUS * CUS, BUS * CUS, CUS * CUS, DUS * CUS}; +uint32_t expectedus4_4[4] = {AUS * DUS, BUS * DUS, CUS * DUS, DUS * DUS}; +uint32_t _elemusA = AUS; +uint32_t _elemusB = BUS; +uint32_t _elemusC = CUS; +uint32_t _elemusD = DUS; + +#define AUH ((uint16_t) 0) +#define BUH ((uint16_t) 32) +#define CUH ((uint16_t) 102) +#define DUH ((uint16_t) 51) +#define EUH ((uint16_t) 71) +#define FUH ((uint16_t) 91) +#define GUH ((uint16_t) 48) +#define HUH ((uint16_t) 255) +uint16_t expecteduh4_1[4] = {AUH * AUH, BUH * AUH, CUH * AUH, DUH * AUH}; +uint16_t expecteduh4_2[4] = {AUH * BUH, BUH * BUH, CUH * BUH, DUH * BUH}; +uint16_t expecteduh4_3[4] = {AUH * CUH, BUH * CUH, CUH * CUH, DUH * CUH}; +uint16_t expecteduh4_4[4] = {AUH * DUH, BUH * DUH, CUH * DUH, DUH * DUH}; +uint16_t expecteduh8_1[8] = {AUH * AUH, BUH * AUH, CUH * AUH, DUH * AUH, + EUH * AUH, FUH * AUH, GUH * AUH, HUH * AUH}; +uint16_t expecteduh8_2[8] = {AUH * BUH, BUH * BUH, CUH * BUH, DUH * BUH, + EUH * BUH, FUH * BUH, GUH * BUH, HUH * BUH}; +uint16_t expecteduh8_3[8] = {AUH * CUH, BUH * CUH, CUH * CUH, DUH * CUH, + EUH * CUH, FUH * CUH, GUH * CUH, HUH * CUH}; +uint16_t expecteduh8_4[8] = {AUH * DUH, BUH * DUH, CUH * DUH, DUH * DUH, + EUH * DUH, FUH * DUH, GUH * DUH, HUH * DUH}; +uint16_t expecteduh8_5[8] = {AUH * EUH, BUH * EUH, CUH * EUH, DUH * EUH, + EUH * EUH, FUH * EUH, GUH * EUH, HUH * EUH}; +uint16_t expecteduh8_6[8] = {AUH * FUH, BUH * FUH, CUH * FUH, DUH * FUH, + EUH * FUH, FUH * FUH, GUH * FUH, HUH * FUH}; +uint16_t expecteduh8_7[8] = {AUH * GUH, BUH * GUH, CUH * GUH, DUH * GUH, + EUH * GUH, FUH * GUH, GUH * GUH, HUH * GUH}; +uint16_t expecteduh8_8[8] = {AUH * HUH, BUH * HUH, CUH * HUH, DUH * HUH, + EUH * HUH, FUH * HUH, GUH * HUH, HUH * HUH}; +uint16_t _elemuhA = AUH; +uint16_t _elemuhB = BUH; +uint16_t _elemuhC = CUH; +uint16_t _elemuhD = DUH; +uint16_t _elemuhE = EUH; +uint16_t _elemuhF = FUH; +uint16_t _elemuhG = GUH; +uint16_t _elemuhH = HUH; + +void +check_v2sf (float32_t elemA, float32_t elemB) +{ + int32_t indx; + const float32_t vec32x2_buf[2] = {A, B}; + float32x2_t vec32x2_src = vld1_f32 (vec32x2_buf); + float32_t vec32x2_res[2]; + + vst1_f32 (vec32x2_res, vmul_n_f32 (vec32x2_src, elemA)); + + for (indx = 0; indx < 2; indx++) + if (* (uint32_t *) &vec32x2_res[indx] != * (uint32_t *) &expected2_1[indx]) + abort (); + + vst1_f32 (vec32x2_res, vmul_n_f32 (vec32x2_src, elemB)); + + for (indx = 0; indx < 2; indx++) + if (* (uint32_t *) &vec32x2_res[indx] != * (uint32_t *) &expected2_2[indx]) + abort (); + +/* { dg-final { scan-assembler-times "fmul\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[0\\\]" 2 } } */ +} + +void +check_v4sf (float32_t elemA, float32_t elemB, float32_t elemC, float32_t elemD) +{ + int32_t indx; + const float32_t vec32x4_buf[4] = {A, B, C, D}; + float32x4_t vec32x4_src = vld1q_f32 (vec32x4_buf); + float32_t vec32x4_res[4]; + + vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemA)); + + for (indx = 0; indx < 4; indx++) + if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_1[indx]) + abort (); + + vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemB)); + + for (indx = 0; indx < 4; indx++) + if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_2[indx]) + abort (); + + vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemC)); + + for (indx = 0; indx < 4; indx++) + if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_3[indx]) + abort (); + + vst1q_f32 (vec32x4_res, vmulq_n_f32 (vec32x4_src, elemD)); + + for (indx = 0; indx < 4; indx++) + if (* (uint32_t *) &vec32x4_res[indx] != * (uint32_t *) &expected4_4[indx]) + abort (); + +/* { dg-final { scan-assembler-times "fmul\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" 4 } } */ +} + +void +check_v2df (float64_t elemdC, float64_t elemdD) +{ + int32_t indx; + const float64_t vec64x2_buf[2] = {AD, BD}; + float64x2_t vec64x2_src = vld1q_f64 (vec64x2_buf); + float64_t vec64x2_res[2]; + + vst1q_f64 (vec64x2_res, vmulq_n_f64 (vec64x2_src, elemdC)); + + for (indx = 0; indx < 2; indx++) + if (* (uint64_t *) &vec64x2_res[indx] != * (uint64_t *) &expectedd2_1[indx]) + abort (); + + vst1q_f64 (vec64x2_res, vmulq_n_f64 (vec64x2_src, elemdD)); + + for (indx = 0; indx < 2; indx++) + if (* (uint64_t *) &vec64x2_res[indx] != * (uint64_t *) &expectedd2_2[indx]) + abort (); + +/* { dg-final { scan-assembler-times "fmul\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[0\\\]" 2 } } */ +} + +void +check_v2si (int32_t elemsA, int32_t elemsB) +{ + int32_t indx; + const int32_t vecs32x2_buf[2] = {AS, BS}; + int32x2_t vecs32x2_src = vld1_s32 (vecs32x2_buf); + int32_t vecs32x2_res[2]; + + vst1_s32 (vecs32x2_res, vmul_n_s32 (vecs32x2_src, elemsA)); + + for (indx = 0; indx < 2; indx++) + if (vecs32x2_res[indx] != expecteds2_1[indx]) + abort (); + + vst1_s32 (vecs32x2_res, vmul_n_s32 (vecs32x2_src, elemsB)); + + for (indx = 0; indx < 2; indx++) + if (vecs32x2_res[indx] != expecteds2_2[indx]) + abort (); +} + +void +check_v2si_unsigned (uint32_t elemusA, uint32_t elemusB) +{ + int indx; + const uint32_t vecus32x2_buf[2] = {AUS, BUS}; + uint32x2_t vecus32x2_src = vld1_u32 (vecus32x2_buf); + uint32_t vecus32x2_res[2]; + + vst1_u32 (vecus32x2_res, vmul_n_u32 (vecus32x2_src, elemusA)); + + for (indx = 0; indx < 2; indx++) + if (vecus32x2_res[indx] != expectedus2_1[indx]) + abort (); + + vst1_u32 (vecus32x2_res, vmul_n_u32 (vecus32x2_src, elemusB)); + + for (indx = 0; indx < 2; indx++) + if (vecus32x2_res[indx] != expectedus2_2[indx]) + abort (); + +/* { dg-final { scan-assembler-times "\tmul\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[0\\\]" 4 } } */ +} + +void +check_v4si (int32_t elemsA, int32_t elemsB, int32_t elemsC, int32_t elemsD) +{ + int32_t indx; + const int32_t vecs32x4_buf[4] = {AS, BS, CS, DS}; + int32x4_t vecs32x4_src = vld1q_s32 (vecs32x4_buf); + int32_t vecs32x4_res[4]; + + vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsA)); + + for (indx = 0; indx < 4; indx++) + if (vecs32x4_res[indx] != expecteds4_1[indx]) + abort (); + + vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsB)); + + for (indx = 0; indx < 4; indx++) + if (vecs32x4_res[indx] != expecteds4_2[indx]) + abort (); + + vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsC)); + + for (indx = 0; indx < 4; indx++) + if (vecs32x4_res[indx] != expecteds4_3[indx]) + abort (); + + vst1q_s32 (vecs32x4_res, vmulq_n_s32 (vecs32x4_src, elemsD)); + + for (indx = 0; indx < 4; indx++) + if (vecs32x4_res[indx] != expecteds4_4[indx]) + abort (); +} + +void +check_v4si_unsigned (uint32_t elemusA, uint32_t elemusB, uint32_t elemusC, + uint32_t elemusD) +{ + int indx; + const uint32_t vecus32x4_buf[4] = {AUS, BUS, CUS, DUS}; + uint32x4_t vecus32x4_src = vld1q_u32 (vecus32x4_buf); + uint32_t vecus32x4_res[4]; + + vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusA)); + + for (indx = 0; indx < 4; indx++) + if (vecus32x4_res[indx] != expectedus4_1[indx]) + abort (); + + vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusB)); + + for (indx = 0; indx < 4; indx++) + if (vecus32x4_res[indx] != expectedus4_2[indx]) + abort (); + + vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusC)); + + for (indx = 0; indx < 4; indx++) + if (vecus32x4_res[indx] != expectedus4_3[indx]) + abort (); + + vst1q_u32 (vecus32x4_res, vmulq_n_u32 (vecus32x4_src, elemusD)); + + for (indx = 0; indx < 4; indx++) + if (vecus32x4_res[indx] != expectedus4_4[indx]) + abort (); + +/* { dg-final { scan-assembler-times "\tmul\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" 8 } } */ +} + + +void +check_v4hi (int16_t elemhA, int16_t elemhB, int16_t elemhC, int16_t elemhD) +{ + int32_t indx; + const int16_t vech16x4_buf[4] = {AH, BH, CH, DH}; + int16x4_t vech16x4_src = vld1_s16 (vech16x4_buf); + int16_t vech16x4_res[4]; + + vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhA)); + + for (indx = 0; indx < 4; indx++) + if (vech16x4_res[indx] != expectedh4_1[indx]) + abort (); + + vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhB)); + + for (indx = 0; indx < 4; indx++) + if (vech16x4_res[indx] != expectedh4_2[indx]) + abort (); + + vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhC)); + + for (indx = 0; indx < 4; indx++) + if (vech16x4_res[indx] != expectedh4_3[indx]) + abort (); + + vst1_s16 (vech16x4_res, vmul_n_s16 (vech16x4_src, elemhD)); + + for (indx = 0; indx < 4; indx++) + if (vech16x4_res[indx] != expectedh4_4[indx]) + abort (); +} + +void +check_v4hi_unsigned (uint16_t elemuhA, uint16_t elemuhB, uint16_t elemuhC, + uint16_t elemuhD) +{ + int indx; + const uint16_t vecuh16x4_buf[4] = {AUH, BUH, CUH, DUH}; + uint16x4_t vecuh16x4_src = vld1_u16 (vecuh16x4_buf); + uint16_t vecuh16x4_res[4]; + + vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhA)); + + for (indx = 0; indx < 4; indx++) + if (vecuh16x4_res[indx] != expecteduh4_1[indx]) + abort (); + + vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhB)); + + for (indx = 0; indx < 4; indx++) + if (vecuh16x4_res[indx] != expecteduh4_2[indx]) + abort (); + + vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhC)); + + for (indx = 0; indx < 4; indx++) + if (vecuh16x4_res[indx] != expecteduh4_3[indx]) + abort (); + + vst1_u16 (vecuh16x4_res, vmul_n_u16 (vecuh16x4_src, elemuhD)); + + for (indx = 0; indx < 4; indx++) + if (vecuh16x4_res[indx] != expecteduh4_4[indx]) + abort (); + +/* { dg-final { scan-assembler-times "mul\tv\[0-9\]+\.4h, v\[0-9\]+\.4h, v\[0-9\]+\.h\\\[0\\\]" 8 } } */ +} + +void +check_v8hi (int16_t elemhA, int16_t elemhB, int16_t elemhC, int16_t elemhD, + int16_t elemhE, int16_t elemhF, int16_t elemhG, int16_t elemhH) +{ + int32_t indx; + const int16_t vech16x8_buf[8] = {AH, BH, CH, DH, EH, FH, GH, HH}; + int16x8_t vech16x8_src = vld1q_s16 (vech16x8_buf); + int16_t vech16x8_res[8]; + + vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhA)); + + for (indx = 0; indx < 8; indx++) + if (vech16x8_res[indx] != expectedh8_1[indx]) + abort (); + + vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhB)); + + for (indx = 0; indx < 8; indx++) + if (vech16x8_res[indx] != expectedh8_2[indx]) + abort (); + + vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhC)); + + for (indx = 0; indx < 8; indx++) + if (vech16x8_res[indx] != expectedh8_3[indx]) + abort (); + + vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhD)); + + for (indx = 0; indx < 8; indx++) + if (vech16x8_res[indx] != expectedh8_4[indx]) + abort (); + + vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhE)); + + for (indx = 0; indx < 8; indx++) + if (vech16x8_res[indx] != expectedh8_5[indx]) + abort (); + + vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhF)); + + for (indx = 0; indx < 8; indx++) + if (vech16x8_res[indx] != expectedh8_6[indx]) + abort (); + + vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhG)); + + for (indx = 0; indx < 8; indx++) + if (vech16x8_res[indx] != expectedh8_7[indx]) + abort (); + + vst1q_s16 (vech16x8_res, vmulq_n_s16 (vech16x8_src, elemhH)); + + for (indx = 0; indx < 8; indx++) + if (vech16x8_res[indx] != expectedh8_8[indx]) + abort (); +} + +void +check_v8hi_unsigned (uint16_t elemuhA, uint16_t elemuhB, uint16_t elemuhC, + uint16_t elemuhD, uint16_t elemuhE, uint16_t elemuhF, + uint16_t elemuhG, uint16_t elemuhH) +{ + int indx; + const uint16_t vecuh16x8_buf[8] = {AUH, BUH, CUH, DUH, EUH, FUH, GUH, HUH}; + uint16x8_t vecuh16x8_src = vld1q_u16 (vecuh16x8_buf); + uint16_t vecuh16x8_res[8]; + + vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhA)); + + for (indx = 0; indx < 8; indx++) + if (vecuh16x8_res[indx] != expecteduh8_1[indx]) + abort (); + + vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhB)); + + for (indx = 0; indx < 8; indx++) + if (vecuh16x8_res[indx] != expecteduh8_2[indx]) + abort (); + + vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhC)); + + for (indx = 0; indx < 8; indx++) + if (vecuh16x8_res[indx] != expecteduh8_3[indx]) + abort (); + + vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhD)); + + for (indx = 0; indx < 8; indx++) + if (vecuh16x8_res[indx] != expecteduh8_4[indx]) + abort (); + + vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhE)); + + for (indx = 0; indx < 8; indx++) + if (vecuh16x8_res[indx] != expecteduh8_5[indx]) + abort (); + + vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhF)); + + for (indx = 0; indx < 8; indx++) + if (vecuh16x8_res[indx] != expecteduh8_6[indx]) + abort (); + + vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhG)); + + for (indx = 0; indx < 8; indx++) + if (vecuh16x8_res[indx] != expecteduh8_7[indx]) + abort (); + + vst1q_u16 (vecuh16x8_res, vmulq_n_u16 (vecuh16x8_src, elemuhH)); + + for (indx = 0; indx < 8; indx++) + if (vecuh16x8_res[indx] != expecteduh8_8[indx]) + abort (); + +/* { dg-final { scan-assembler-times "mul\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[0\\\]" 16 } } */ +} + +int +main (void) +{ + check_v2sf (_elemA, _elemB); + check_v4sf (_elemA, _elemB, _elemC, _elemD); + check_v2df (_elemdC, _elemdD); + check_v2si (_elemsA, _elemsB); + check_v4si (_elemsA, _elemsB, _elemsC, _elemsD); + check_v4hi (_elemhA, _elemhB, _elemhC, _elemhD); + check_v8hi (_elemhA, _elemhB, _elemhC, _elemhD, + _elemhE, _elemhF, _elemhG, _elemhH); + check_v2si_unsigned (_elemusA, _elemusB); + check_v4si_unsigned (_elemusA, _elemusB, _elemusC, _elemusD); + check_v4hi_unsigned (_elemuhA, _elemuhB, _elemuhC, _elemuhD); + check_v8hi_unsigned (_elemuhA, _elemuhB, _elemuhC, _elemuhD, + _elemuhE, _elemuhF, _elemuhG, _elemuhH); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/aarch64/struct_return.c b/gcc/testsuite/gcc.target/aarch64/struct_return.c new file mode 100644 index 00000000000..6d90b7e5953 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/struct_return.c @@ -0,0 +1,31 @@ +/* Test the absence of a spurious move from x8 to x0 for functions + return structures. */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct s +{ + long x; + long y; + long z; +}; + +struct s __attribute__((noinline)) +foo (long a, long d, long c) +{ + struct s b; + b.x = a; + b.y = d; + b.z = c; + return b; +} + +int +main (void) +{ + struct s x; + x = foo ( 10, 20, 30); + return x.x + x.y + x.z; +} + +/* { dg-final { scan-assembler-not "mov\tx0, x8" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_16.c b/gcc/testsuite/gcc.target/aarch64/test_frame_16.c new file mode 100644 index 00000000000..28f3826adad --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/test_frame_16.c @@ -0,0 +1,25 @@ +/* Verify: + * with outgoing. + * single int register push. + * varargs and callee-save size >= 256 + * Use 2 stack adjustments. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -fomit-frame-pointer --save-temps" } */ + +#define REP8(X) X,X,X,X,X,X,X,X +#define REP64(X) REP8(REP8(X)) + +void outgoing (__builtin_va_list, ...); + +double vararg_outgoing (int x1, ...) +{ + double a1 = x1, a2 = x1 * 2, a3 = x1 * 3, a4 = x1 * 4, a5 = x1 * 5, a6 = x1 * 6; + __builtin_va_list vl; + __builtin_va_start (vl, x1); + outgoing (vl, a1, a2, a3, a4, a5, a6, REP64 (1)); + __builtin_va_end (vl); + return a1 + a2 + a3 + a4 + a5 + a6; +} + +/* { dg-final { scan-assembler-times "sub\tsp, sp, #\[0-9\]+" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c b/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c new file mode 100644 index 00000000000..14b1f736093 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=thunderx" } */ + +struct ldp +{ + long long c; + int a, b; +}; + + +int f(struct ldp *a) +{ + return a->a + a->b; +} + + +/* We know the alignement of a->a to be 8 byte aligned so it is profitable + to do ldp. */ +/* { dg-final { scan-assembler-times "ldp\tw\[0-9\]+, w\[0-9\]" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c b/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c new file mode 100644 index 00000000000..3093ad0e1f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=thunderx" } */ + +struct noldp +{ + int a, b; +}; + + +int f(struct noldp *a) +{ + return a->a + a->b; +} + +/* We know the alignement of a->a to be 4 byte aligned so it is not profitable + to do ldp. */ +/* { dg-final { scan-assembler-not "ldp\tw\[0-9\]+, w\[0-9\]" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/va_arg_1.c b/gcc/testsuite/gcc.target/aarch64/va_arg_1.c new file mode 100644 index 00000000000..e8e3cdac513 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/va_arg_1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 --save-temps" } */ + +int +f (int a, ...) +{ + /* { dg-final { scan-assembler-not "str" } } */ + return a; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/va_arg_2.c b/gcc/testsuite/gcc.target/aarch64/va_arg_2.c new file mode 100644 index 00000000000..f5c46cbd67f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/va_arg_2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 --save-temps" } */ + +int +foo (char *fmt, ...) +{ + int d; + __builtin_va_list ap; + + __builtin_va_start (ap, fmt); + d = __builtin_va_arg (ap, int); + __builtin_va_end (ap); + + /* { dg-final { scan-assembler-not "x7" } } */ + return d; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/va_arg_3.c b/gcc/testsuite/gcc.target/aarch64/va_arg_3.c new file mode 100644 index 00000000000..7f7601a8070 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/va_arg_3.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 --save-temps" } */ + +int d2i (double a); + +int +foo (char *fmt, ...) +{ + int d, e; + double f, g; + __builtin_va_list ap; + + __builtin_va_start (ap, fmt); + d = __builtin_va_arg (ap, int); + f = __builtin_va_arg (ap, double); + g = __builtin_va_arg (ap, double); + d += d2i (f); + d += d2i (g); + __builtin_va_end (ap); + + /* { dg-final { scan-assembler-not "x7" } } */ + /* { dg-final { scan-assembler-not "q7" } } */ + return d; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c b/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c new file mode 100644 index 00000000000..e144def8386 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c @@ -0,0 +1,86 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#include "arm_neon.h" + +#define BUILD_TEST(TYPE1, TYPE2, Q1, Q2, SUFFIX, INDEX1, INDEX2) \ +TYPE1 __attribute__((noinline,noclone)) \ +test_copy##Q1##_lane##Q2##_##SUFFIX (TYPE1 a, TYPE2 b) \ +{ \ + return vcopy##Q1##_lane##Q2##_##SUFFIX (a, INDEX1, b, INDEX2); \ +} + +/* vcopy_lane. */ +BUILD_TEST (poly8x8_t, poly8x8_t, , , p8, 7, 6) +BUILD_TEST (int8x8_t, int8x8_t, , , s8, 7, 6) +BUILD_TEST (uint8x8_t, uint8x8_t, , , u8, 7, 6) +/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[6\\\]" 3 } } */ +BUILD_TEST (poly16x4_t, poly16x4_t, , , p16, 3, 2) +BUILD_TEST (int16x4_t, int16x4_t, , , s16, 3, 2) +BUILD_TEST (uint16x4_t, uint16x4_t, , , u16, 3, 2) +/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[2\\\]" 3 } } */ +BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0) +BUILD_TEST (int32x2_t, int32x2_t, , , s32, 1, 0) +BUILD_TEST (uint32x2_t, uint32x2_t, , , u32, 1, 0) +/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[0\\\]" 3 } } */ +BUILD_TEST (int64x1_t, int64x1_t, , , s64, 0, 0) +BUILD_TEST (uint64x1_t, uint64x1_t, , , u64, 0, 0) +BUILD_TEST (float64x1_t, float64x1_t, , , f64, 0, 0) +/* { dg-final { scan-assembler-times "fmov\\td0, d1" 3 } } */ + +/* vcopy_laneq. */ + +BUILD_TEST (poly8x8_t, poly8x16_t, , q, p8, 7, 15) +BUILD_TEST (int8x8_t, int8x16_t, , q, s8, 7, 15) +BUILD_TEST (uint8x8_t, uint8x16_t, , q, u8, 7, 15) +/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[15\\\]" 3 } } */ +BUILD_TEST (poly16x4_t, poly16x8_t, , q, p16, 3, 7) +BUILD_TEST (int16x4_t, int16x8_t, , q, s16, 3, 7) +BUILD_TEST (uint16x4_t, uint16x8_t, , q, u16, 3, 7) +/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[7\\\]" 3 } } */ +BUILD_TEST (float32x2_t, float32x4_t, , q, f32, 1, 3) +BUILD_TEST (int32x2_t, int32x4_t, , q, s32, 1, 3) +BUILD_TEST (uint32x2_t, uint32x4_t, , q, u32, 1, 3) +/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[3\\\]" 3 } } */ +BUILD_TEST (float64x1_t, float64x2_t, , q, f64, 0, 1) +BUILD_TEST (int64x1_t, int64x2_t, , q, s64, 0, 1) +BUILD_TEST (uint64x1_t, uint64x2_t, , q, u64, 0, 1) +/* XFAIL due to PR 71307. */ +/* { dg-final { scan-assembler-times "dup\\td0, v1.d\\\[1\\\]" 3 { xfail *-*-* } } } */ + +/* vcopyq_lane. */ +BUILD_TEST (poly8x16_t, poly8x8_t, q, , p8, 15, 7) +BUILD_TEST (int8x16_t, int8x8_t, q, , s8, 15, 7) +BUILD_TEST (uint8x16_t, uint8x8_t, q, , u8, 15, 7) +/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[15\\\], v1.b\\\[7\\\]" 3 } } */ +BUILD_TEST (poly16x8_t, poly16x4_t, q, , p16, 7, 3) +BUILD_TEST (int16x8_t, int16x4_t, q, , s16, 7, 3) +BUILD_TEST (uint16x8_t, uint16x4_t, q, , u16, 7, 3) +/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[7\\\], v1.h\\\[3\\\]" 3 } } */ +BUILD_TEST (float32x4_t, float32x2_t, q, , f32, 3, 1) +BUILD_TEST (int32x4_t, int32x2_t, q, , s32, 3, 1) +BUILD_TEST (uint32x4_t, uint32x2_t, q, , u32, 3, 1) +/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[3\\\], v1.s\\\[1\\\]" 3 } } */ +BUILD_TEST (float64x2_t, float64x1_t, q, , f64, 1, 0) +BUILD_TEST (int64x2_t, int64x1_t, q, , s64, 1, 0) +BUILD_TEST (uint64x2_t, uint64x1_t, q, , u64, 1, 0) +/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[0\\\]" 3 } } */ + +/* vcopyq_laneq. */ + +BUILD_TEST (poly8x16_t, poly8x16_t, q, q, p8, 14, 15) +BUILD_TEST (int8x16_t, int8x16_t, q, q, s8, 14, 15) +BUILD_TEST (uint8x16_t, uint8x16_t, q, q, u8, 14, 15) +/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[14\\\], v1.b\\\[15\\\]" 3 } } */ +BUILD_TEST (poly16x8_t, poly16x8_t, q, q, p16, 6, 7) +BUILD_TEST (int16x8_t, int16x8_t, q, q, s16, 6, 7) +BUILD_TEST (uint16x8_t, uint16x8_t, q, q, u16, 6, 7) +/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[6\\\], v1.h\\\[7\\\]" 3 } } */ +BUILD_TEST (float32x4_t, float32x4_t, q, q, f32, 2, 3) +BUILD_TEST (int32x4_t, int32x4_t, q, q, s32, 2, 3) +BUILD_TEST (uint32x4_t, uint32x4_t, q, q, u32, 2, 3) +/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[2\\\], v1.s\\\[3\\\]" 3 } } */ +BUILD_TEST (float64x2_t, float64x2_t, q, q, f64, 1, 1) +BUILD_TEST (int64x2_t, int64x2_t, q, q, s64, 1, 1) +BUILD_TEST (uint64x2_t, uint64x2_t, q, q, u64, 1, 1) +/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[1\\\]" 3 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c b/gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c new file mode 100644 index 00000000000..07a77de3192 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include "arm_neon.h" + +#define BUILD_TEST(TYPE1, TYPE2, Q1, Q2, SUFFIX, INDEX1, INDEX2) \ +TYPE1 __attribute__((noinline,noclone)) \ +test_copy##Q1##_lane##Q2##_##SUFFIX (TYPE1 a, TYPE2 b) \ +{ \ + return vset##Q1##_lane_##SUFFIX (vget##Q2##_lane_##SUFFIX (b, INDEX2),\ + a, INDEX1); \ +} + +BUILD_TEST (poly8x8_t, poly8x8_t, , , p8, 7, 6) +BUILD_TEST (int8x8_t, int8x8_t, , , s8, 7, 6) +BUILD_TEST (uint8x8_t, uint8x8_t, , , u8, 7, 6) +/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[6\\\]" 3 } } */ +BUILD_TEST (poly16x4_t, poly16x4_t, , , p16, 3, 2) +BUILD_TEST (int16x4_t, int16x4_t, , , s16, 3, 2) +BUILD_TEST (uint16x4_t, uint16x4_t, , , u16, 3, 2) +/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[2\\\]" 3 } } */ +BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0) +BUILD_TEST (int32x2_t, int32x2_t, , , s32, 1, 0) +BUILD_TEST (uint32x2_t, uint32x2_t, , , u32, 1, 0) +/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[0\\\]" 3 } } */ + +BUILD_TEST (poly8x8_t, poly8x16_t, , q, p8, 7, 15) +BUILD_TEST (int8x8_t, int8x16_t, , q, s8, 7, 15) +BUILD_TEST (uint8x8_t, uint8x16_t, , q, u8, 7, 15) +/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[7\\\], v1.b\\\[15\\\]" 3 } } */ +BUILD_TEST (poly16x4_t, poly16x8_t, , q, p16, 3, 7) +BUILD_TEST (int16x4_t, int16x8_t, , q, s16, 3, 7) +BUILD_TEST (uint16x4_t, uint16x8_t, , q, u16, 3, 7) +/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[3\\\], v1.h\\\[7\\\]" 3 } } */ +BUILD_TEST (float32x2_t, float32x4_t, , q, f32, 1, 3) +BUILD_TEST (int32x2_t, int32x4_t, , q, s32, 1, 3) +BUILD_TEST (uint32x2_t, uint32x4_t, , q, u32, 1, 3) +/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[3\\\]" 3 } } */ + +BUILD_TEST (poly8x16_t, poly8x8_t, q, , p8, 15, 7) +BUILD_TEST (int8x16_t, int8x8_t, q, , s8, 15, 7) +BUILD_TEST (uint8x16_t, uint8x8_t, q, , u8, 15, 7) +/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[15\\\], v1.b\\\[7\\\]" 3 } } */ +BUILD_TEST (poly16x8_t, poly16x4_t, q, , p16, 7, 3) +BUILD_TEST (int16x8_t, int16x4_t, q, , s16, 7, 3) +BUILD_TEST (uint16x8_t, uint16x4_t, q, , u16, 7, 3) +/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[7\\\], v1.h\\\[3\\\]" 3 } } */ +BUILD_TEST (float32x4_t, float32x2_t, q, , f32, 3, 1) +BUILD_TEST (int32x4_t, int32x2_t, q, , s32, 3, 1) +BUILD_TEST (uint32x4_t, uint32x2_t, q, , u32, 3, 1) +/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[3\\\], v1.s\\\[1\\\]" 3 } } */ +BUILD_TEST (float64x2_t, float64x1_t, q, , f64, 1, 0) +BUILD_TEST (int64x2_t, int64x1_t, q, , s64, 1, 0) +BUILD_TEST (uint64x2_t, uint64x1_t, q, , u64, 1, 0) +/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[0\\\]" 3 } } */ + +BUILD_TEST (poly8x16_t, poly8x16_t, q, q, p8, 14, 15) +BUILD_TEST (int8x16_t, int8x16_t, q, q, s8, 14, 15) +BUILD_TEST (uint8x16_t, uint8x16_t, q, q, u8, 14, 15) +/* { dg-final { scan-assembler-times "ins\\tv0.b\\\[14\\\], v1.b\\\[15\\\]" 3 } } */ +BUILD_TEST (poly16x8_t, poly16x8_t, q, q, p16, 6, 7) +BUILD_TEST (int16x8_t, int16x8_t, q, q, s16, 6, 7) +BUILD_TEST (uint16x8_t, uint16x8_t, q, q, u16, 6, 7) +/* { dg-final { scan-assembler-times "ins\\tv0.h\\\[6\\\], v1.h\\\[7\\\]" 3 } } */ +BUILD_TEST (float32x4_t, float32x4_t, q, q, f32, 2, 3) +BUILD_TEST (int32x4_t, int32x4_t, q, q, s32, 2, 3) +BUILD_TEST (uint32x4_t, uint32x4_t, q, q, u32, 2, 3) +/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[2\\\], v1.s\\\[3\\\]" 3 } } */ +BUILD_TEST (float64x2_t, float64x2_t, q, q, f64, 1, 1) +BUILD_TEST (int64x2_t, int64x2_t, q, q, s64, 1, 1) +BUILD_TEST (uint64x2_t, uint64x2_t, q, q, u64, 1, 1) +/* { dg-final { scan-assembler-times "ins\\tv0.d\\\[1\\\], v1.d\\\[1\\\]" 3 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vminmaxnm.c b/gcc/testsuite/gcc.target/aarch64/vminmaxnm.c new file mode 100644 index 00000000000..bdaa5649971 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vminmaxnm.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include "arm_neon.h" + +/* For each of these intrinsics, we map directly to an unspec in RTL. + We're just using the argument directly and returning the result, so we + can precisely specify the exact instruction pattern and register + allocations we expect. */ + +float64x1_t +test_vmaxnm_f64 (float64x1_t a, float64x1_t b) +{ + /* { dg-final { scan-assembler-times "fmaxnm\td0, d0, d1" 1 } } */ + return vmaxnm_f64 (a, b); +} + +float64x1_t +test_vminnm_f64 (float64x1_t a, float64x1_t b) +{ + /* { dg-final { scan-assembler-times "fminnm\td0, d0, d1" 1 } } */ + return vminnm_f64 (a, b); +} + +float64x1_t +test_vmax_f64 (float64x1_t a, float64x1_t b) +{ + /* { dg-final { scan-assembler-times "fmax\td0, d0, d1" 1 } } */ + return vmax_f64 (a, b); +} + +float64x1_t +test_vmin_f64 (float64x1_t a, float64x1_t b) +{ + /* { dg-final { scan-assembler-times "fmin\td0, d0, d1" 1 } } */ + return vmin_f64 (a, b); +}
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c new file mode 100644 index 00000000000..788079bc104 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c @@ -0,0 +1,32 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_fp16_hw } */ +/* { dg-add-options arm_neon_fp16 } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect10.c" +#include "neon-constants.h" + +#include "abitest.h" +#else + +ARG (int32x4_t, i32x4_constvec2, Q0) /* D0, D1. */ +#if defined (__ARM_BIG_ENDIAN) +ARG (__fp16, 3.0f, S4 + 2) /* D2, Q1. */ +#else +ARG (__fp16, 3.0f, S4) /* D2, Q1. */ +#endif +ARG (int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12. */ +ARG (double, 12.0, D3) /* Backfill this particular argument. */ +#if defined (__ARM_BIG_ENDIAN) +ARG (__fp16, 5.0f, S5 + 2) /* Backfill in S5. */ +#else +ARG (__fp16, 5.0f, S5) /* Backfill in S5. */ +#endif +ARG (int32x4x2_t, i32x4x2_constvec2, STACK) +LAST_ARG (int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c new file mode 100644 index 00000000000..b42fdd23926 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c @@ -0,0 +1,24 @@ +/* Test AAPCS layout (VFP variant for Neon types) */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_neon_fp16_hw } */ +/* { dg-add-options arm_neon_fp16 } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define NEON +#define TESTFILE "neon-vect9.c" +#include "neon-constants.h" + +#include "abitest.h" +#else + +ARG (int32x4_t, i32x4_constvec2, Q0) /* D0, D1. */ +#if defined (__ARM_BIG_ENDIAN) +ARG (__fp16, 3.0f, S4 + 2) /* D2, Q1 occupied. */ +#else +ARG (__fp16, 3.0f, S4) /* D2, Q1 occupied. */ +#endif +LAST_ARG (int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c new file mode 100644 index 00000000000..0745a82f5e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c @@ -0,0 +1,28 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_fp16_hw } */ +/* { dg-add-options arm_fp16_ieee } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp18.c" +#include "abitest.h" + +#else +#if defined (__ARM_BIG_ENDIAN) +ARG (__fp16, 1.0f, S0 + 2) +#else +ARG (__fp16, 1.0f, S0) +#endif +ARG (float, 2.0f, S1) +ARG (double, 4.0, D1) +ARG (float, 2.0f, S4) +#if defined (__ARM_BIG_ENDIAN) +ARG (__fp16, 1.0f, S5 + 2) +#else +ARG (__fp16, 1.0f, S5) +#endif +LAST_ARG (int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c new file mode 100644 index 00000000000..950c1f6a6d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c @@ -0,0 +1,30 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_fp16_hw } */ +/* { dg-add-options arm_fp16_ieee } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp19.c" + +__complex__ x = 1.0+2.0i; + +#include "abitest.h" +#else +#if defined (__ARM_BIG_ENDIAN) +ARG (__fp16, 1.0f, S0 + 2) +#else +ARG (__fp16, 1.0f, S0) +#endif +ARG (float, 2.0f, S1) +ARG (__complex__ double, x, D1) +ARG (float, 3.0f, S6) +#if defined (__ARM_BIG_ENDIAN) +ARG (__fp16, 2.0f, S7 + 2) +#else +ARG (__fp16, 2.0f, S7) +#endif +LAST_ARG (int, 3, R0) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c new file mode 100644 index 00000000000..f898d4cebd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c @@ -0,0 +1,22 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_fp16_hw } */ +/* { dg-add-options arm_fp16_ieee } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp20.c" + +#define PCSATTR __attribute__((pcs("aapcs"))) + +#include "abitest.h" +#else +ARG (float, 1.0f, R0) +ARG (double, 2.0, R2) +ARG (float, 3.0f, STACK) +ARG (__fp16, 2.0f, STACK+4) +LAST_ARG (double, 4.0, STACK+8) +#endif + diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c new file mode 100644 index 00000000000..48bb59856e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c @@ -0,0 +1,26 @@ +/* Test AAPCS layout (VFP variant) */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_fp16_hw } */ +/* { dg-add-options arm_fp16_ieee } */ + +#ifndef IN_FRAMEWORK +#define VFP +#define TESTFILE "vfp21.c" + +#define PCSATTR __attribute__((pcs("aapcs"))) + +#include "abitest.h" +#else +#if defined (__ARM_BIG_ENDIAN) +ARG (__fp16, 1.0f, R0 + 2) +#else +ARG (__fp16, 1.0f, R0) +#endif +ARG (double, 2.0, R2) +ARG (__fp16, 3.0f, STACK) +ARG (float, 2.0f, STACK+4) +LAST_ARG (double, 4.0, STACK+8) +#endif + diff --git a/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c b/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c new file mode 100644 index 00000000000..80a00aec978 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c @@ -0,0 +1,8 @@ +/* { dg-require-effective-target arm_arch_v5_ok } */ +/* { dg-add-options arm_arch_v5 } */ + +#if __ARM_ARCH_ISA_THUMB +#error "__ARM_ARCH_ISA_THUMB defined for ARMv5" +#endif + +int foo; diff --git a/gcc/testsuite/gcc.target/arm/builtin_saddl.c b/gcc/testsuite/gcc.target/arm/builtin_saddl.c new file mode 100644 index 00000000000..af85594b9d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/builtin_saddl.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +extern void overflow_handler (); + +long overflow_add (long x, long y) +{ + long r; + + int ovr = __builtin_saddl_overflow (x, y, &r); + if (ovr) + overflow_handler (); + + return r; +} + +/* { dg-final { scan-assembler "adds" } } */ diff --git a/gcc/testsuite/gcc.target/arm/builtin_saddll.c b/gcc/testsuite/gcc.target/arm/builtin_saddll.c new file mode 100644 index 00000000000..62fe6eff01f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/builtin_saddll.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +extern void overflow_handler (); + +long long overflow_add (long long x, long long y) +{ + long long r; + + int ovr = __builtin_saddll_overflow (x, y, &r); + if (ovr) + overflow_handler (); + + return r; +} + +/* { dg-final { scan-assembler "adds" } } */ +/* { dg-final { scan-assembler "adcs" } } */ diff --git a/gcc/testsuite/gcc.target/arm/builtin_ssubl.c b/gcc/testsuite/gcc.target/arm/builtin_ssubl.c new file mode 100644 index 00000000000..8c5a4c92168 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/builtin_ssubl.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +extern void overflow_handler (); + +long overflow_sub (long x, long y) +{ + long r; + + int ovr = __builtin_ssubl_overflow (x, y, &r); + if (ovr) + overflow_handler (); + + return r; +} + +/* { dg-final { scan-assembler "subs" } } */ diff --git a/gcc/testsuite/gcc.target/arm/builtin_ssubll.c b/gcc/testsuite/gcc.target/arm/builtin_ssubll.c new file mode 100644 index 00000000000..2048d7915ea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/builtin_ssubll.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +extern void overflow_handler (); + +long long overflow_sub (long long x, long long y) +{ + long long r; + + int ovr = __builtin_ssubll_overflow (x, y, &r); + if (ovr) + overflow_handler (); + + return r; +} + +/* { dg-final { scan-assembler "subs" } } */ +/* { dg-final { scan-assembler "sbcs" } } */ diff --git a/gcc/testsuite/gcc.target/arm/builtin_uaddl.c b/gcc/testsuite/gcc.target/arm/builtin_uaddl.c new file mode 100644 index 00000000000..ac25766c157 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/builtin_uaddl.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +extern void overflow_handler (); + +unsigned long overflow_add (unsigned long x, unsigned long y) +{ + unsigned long r; + + int ovr = __builtin_uaddl_overflow (x, y, &r); + if (ovr) + overflow_handler (); + + return r; +} + +/* { dg-final { scan-assembler "adds" } } */ diff --git a/gcc/testsuite/gcc.target/arm/builtin_uaddll.c b/gcc/testsuite/gcc.target/arm/builtin_uaddll.c new file mode 100644 index 00000000000..ec3188e9067 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/builtin_uaddll.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +extern void overflow_handler (); + +unsigned long long overflow_add (unsigned long long x, unsigned long long y) +{ + unsigned long long r; + + int ovr = __builtin_uaddll_overflow (x, y, &r); + if (ovr) + overflow_handler (); + + return r; +} + +/* { dg-final { scan-assembler "adds" } } */ +/* { dg-final { scan-assembler "adcs" } } */ diff --git a/gcc/testsuite/gcc.target/arm/builtin_usubl.c b/gcc/testsuite/gcc.target/arm/builtin_usubl.c new file mode 100644 index 00000000000..99782083d45 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/builtin_usubl.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +extern void overflow_handler (); + +unsigned long overflow_sub (unsigned long x, unsigned long y) +{ + unsigned long r; + + int ovr = __builtin_usubl_overflow (x, y, &r); + if (ovr) + overflow_handler (); + + return r; +} + +/* { dg-final { scan-assembler "subs" } } */ diff --git a/gcc/testsuite/gcc.target/arm/builtin_usubll.c b/gcc/testsuite/gcc.target/arm/builtin_usubll.c new file mode 100644 index 00000000000..8d64660a813 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/builtin_usubll.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ +extern void overflow_handler (); + +unsigned long long overflow_sub (unsigned long long x, unsigned long long y) +{ + unsigned long long r; + + int ovr = __builtin_usubll_overflow (x, y, &r); + if (ovr) + overflow_handler (); + + return r; +} + +/* { dg-final { scan-assembler "subs" } } */ +/* { dg-final { scan-assembler "sbcs" } } */ diff --git a/gcc/testsuite/gcc.target/arm/data-rel-1.c b/gcc/testsuite/gcc.target/arm/data-rel-1.c new file mode 100644 index 00000000000..d9d88f2e8db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/data-rel-1.c @@ -0,0 +1,12 @@ +/* { dg-options "-fPIC -mno-pic-data-is-text-relative" } */ +/* { dg-final { scan-assembler-not "j-\\(.LPIC" } } */ +/* { dg-final { scan-assembler-not "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */ +/* { dg-final { scan-assembler "j\\(GOT\\)" } } */ +/* { dg-final { scan-assembler "(ldr|mov)\tr\[0-9\]+, \\\[?r9" } } */ + +static int j; + +int *Foo () +{ + return &j; +} diff --git a/gcc/testsuite/gcc.target/arm/data-rel-2.c b/gcc/testsuite/gcc.target/arm/data-rel-2.c new file mode 100644 index 00000000000..6ba47d677a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/data-rel-2.c @@ -0,0 +1,11 @@ +/* { dg-options "-fPIC -mno-pic-data-is-text-relative -mno-single-pic-base" } */ +/* { dg-final { scan-assembler-not "j-\\(.LPIC" } } */ +/* { dg-final { scan-assembler "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */ +/* { dg-final { scan-assembler "j\\(GOT\\)" } } */ + +static int j; + +int *Foo () +{ + return &j; +} diff --git a/gcc/testsuite/gcc.target/arm/data-rel-3.c b/gcc/testsuite/gcc.target/arm/data-rel-3.c new file mode 100644 index 00000000000..2ce1e6607c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/data-rel-3.c @@ -0,0 +1,11 @@ +/* { dg-options "-fPIC -mpic-data-is-text-relative" } */ +/* { dg-final { scan-assembler "j-\\(.LPIC" } } */ +/* { dg-final { scan-assembler-not "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */ +/* { dg-final { scan-assembler-not "j\\(GOT\\)" } } */ + +static int j; + +int *Foo () +{ + return &j; +} diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c new file mode 100644 index 00000000000..9bf3fc07e7f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-require-effective-target arm_fp16_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_fp16_ieee } */ + +/* Test __fp16 arguments and return value in registers (hard-float). */ + +void +swap (__fp16, __fp16); + +__fp16 +F (__fp16 a, __fp16 b, __fp16 c) +{ + swap (b, a); + return c; +} + +/* { dg-final { scan-assembler-times {vmov\tr[0-9]+, s[0-2]} 2 } } */ +/* { dg-final { scan-assembler-times {vmov.f32\ts1, s0} 1 } } */ +/* { dg-final { scan-assembler-times {vmov\ts0, r[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c new file mode 100644 index 00000000000..4753e364a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_fp16_ok } */ +/* { dg-options "-mfloat-abi=softfp -O2" } */ +/* { dg-add-options arm_fp16_ieee } */ +/* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */ + +/* Test __fp16 arguments and return value in registers (softfp). */ + +void +swap (__fp16, __fp16); + +__fp16 +F (__fp16 a, __fp16 b, __fp16 c) +{ + swap (b, a); + return c; +} + +/* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } } */ +/* { dg-final { scan-assembler-times {mov\tr1, r0} 1 } } */ +/* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vaddws16.c b/gcc/testsuite/gcc.target/arm/neon-vaddws16.c new file mode 100644 index 00000000000..82811343e49 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vaddws16.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O3" } */ +/* { dg-add-options arm_neon } */ + + + +int +t6 (int len, void * dummy, short * __restrict x) +{ + len = len & ~31; + int result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "vaddw\.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vaddws32.c b/gcc/testsuite/gcc.target/arm/neon-vaddws32.c new file mode 100644 index 00000000000..8c186918012 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vaddws32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O3" } */ +/* { dg-add-options arm_neon } */ + + +int +t6 (int len, void * dummy, int * __restrict x) +{ + len = len & ~31; + long long result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "vaddw\.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vaddwu16.c b/gcc/testsuite/gcc.target/arm/neon-vaddwu16.c new file mode 100644 index 00000000000..580bb061006 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vaddwu16.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O3" } */ +/* { dg-add-options arm_neon } */ + + +int +t6 (int len, void * dummy, unsigned short * __restrict x) +{ + len = len & ~31; + unsigned int result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "vaddw.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vaddwu32.c b/gcc/testsuite/gcc.target/arm/neon-vaddwu32.c new file mode 100644 index 00000000000..21b063342dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vaddwu32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O3" } */ +/* { dg-add-options arm_neon } */ + + +int +t6 (int len, void * dummy, unsigned int * __restrict x) +{ + len = len & ~31; + unsigned long long result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "vaddw\.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vaddwu8.c b/gcc/testsuite/gcc.target/arm/neon-vaddwu8.c new file mode 100644 index 00000000000..d350ed537e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vaddwu8.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O3" } */ +/* { dg-add-options arm_neon } */ + + + +int +t6 (int len, void * dummy, char * __restrict x) +{ + len = len & ~31; + unsigned short result = 0; + __asm volatile (""); + for (int i = 0; i < len; i++) + result += x[i]; + return result; +} + +/* { dg-final { scan-assembler "vaddw\.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr37780_1.c b/gcc/testsuite/gcc.target/arm/pr37780_1.c new file mode 100644 index 00000000000..8e069200e9f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr37780_1.c @@ -0,0 +1,48 @@ +/* Test that we can remove the conditional move due to CLZ + being defined at zero. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v6t2_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v6t2 } */ + +int +fooctz (int i) +{ + return (i == 0) ? 32 : __builtin_ctz (i); +} + +int +fooctz2 (int i) +{ + return (i != 0) ? __builtin_ctz (i) : 32; +} + +unsigned int +fooctz3 (unsigned int i) +{ + return (i > 0) ? __builtin_ctz (i) : 32; +} + +/* { dg-final { scan-assembler-times "rbit\t*" 3 } } */ + +int +fooclz (int i) +{ + return (i == 0) ? 32 : __builtin_clz (i); +} + +int +fooclz2 (int i) +{ + return (i != 0) ? __builtin_clz (i) : 32; +} + +unsigned int +fooclz3 (unsigned int i) +{ + return (i > 0) ? __builtin_clz (i) : 32; +} + +/* { dg-final { scan-assembler-times "clz\t" 6 } } */ +/* { dg-final { scan-assembler-not "cmp\t.*0" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr70830.c b/gcc/testsuite/gcc.target/arm/pr70830.c new file mode 100644 index 00000000000..cad903b0cf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr70830.c @@ -0,0 +1,14 @@ +/* PR target/70830. */ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_arm_ok } */ +/* { dg-options "-Os -marm -save-temps" } */ + +/* This test is not valid when -mthumb. */ + +extern void prints (char *); + +void __attribute__ ((interrupt ("IRQ"))) dm3730_IRQHandler(void) +{ + prints("IRQ" ); +} +/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, ip, pc}\\^" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr71056.c b/gcc/testsuite/gcc.target/arm/pr71056.c new file mode 100644 index 00000000000..136754eb13c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr71056.c @@ -0,0 +1,32 @@ +/* PR target/71056. */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_vfp3_ok } */ +/* { dg-options "-O3 -mfpu=vfpv3" } */ + +/* Check that compiling for a non-NEON target doesn't try to introduce + a NEON vectorized builtin. */ + +extern char *buff; +int f2 (); +struct T1 +{ + int reserved[2]; + unsigned int ip; + unsigned short cs; + unsigned short rsrv2; +}; +void +f3 (const char *p) +{ + struct T1 x; + __builtin_memcpy (&x, p, sizeof (struct T1)); + x.reserved[0] = __builtin_bswap32 (x.reserved[0]); + x.reserved[1] = __builtin_bswap32 (x.reserved[1]); + x.ip = __builtin_bswap32 (x.ip); + x.cs = x.cs << 8 | x.cs >> 8; + x.rsrv2 = x.rsrv2 << 8 | x.rsrv2 >> 8; + if (f2 ()) + { + __builtin_memcpy (buff, "\n", 1); + } +} diff --git a/gcc/testsuite/gcc.target/avr/pr50739.c b/gcc/testsuite/gcc.target/avr/pr50739.c new file mode 100644 index 00000000000..a6850b73c3e --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr50739.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-fmerge-all-constants" } */ + +char *ca = "123"; + +const char a[] __attribute__((__progmem__))= "a"; +const char b[] __attribute__((__progmem__))= "b"; diff --git a/gcc/testsuite/gcc.target/avr/pr71103.c b/gcc/testsuite/gcc.target/avr/pr71103.c new file mode 100644 index 00000000000..43244d15e97 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71103.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +struct ResponseStruct{ + unsigned char responseLength; + char *response; +}; + +static char response[5]; +struct ResponseStruct something(){ + struct ResponseStruct returnValue; + returnValue.responseLength = 5; + returnValue.response = response; + return returnValue; +} + diff --git a/gcc/testsuite/gcc.target/avr/pr71151-1.c b/gcc/testsuite/gcc.target/avr/pr71151-1.c new file mode 100644 index 00000000000..615dce86026 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71151-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -ffunction-sections -fdata-sections" } */ + +/* { dg-final { scan-assembler-not ".section .progmem.gcc_sw_table.foo.str1.1" } } */ +/* { dg-final { scan-assembler ".section .rodata.foo.str1.1,\"aMS\"" } } */ + + +extern void bar(const char*); +void foo(void) +{ + bar("BBBBBBBBBB"); +} diff --git a/gcc/testsuite/gcc.target/avr/pr71151-2.c b/gcc/testsuite/gcc.target/avr/pr71151-2.c new file mode 100644 index 00000000000..f745841df8a --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71151-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fno-tree-switch-conversion -ffunction-sections -fdata-sections" } */ + +/* Make sure jumptables work properly if placed below 64 KB i.e. 2 byte + flash address for loading jump table entry, 2 byte entry, after + removing the special section placement hook. */ + +#define SECTION_NAME ".foo" + +#include "exit-abort.h" +#include "pr71151-common.h" + +int main() +{ + foo(5); + if (y != 37) + abort(); + + foo(0); + if (y != 67) + abort(); + + foo(7); + if (y != 98) + abort(); +} diff --git a/gcc/testsuite/gcc.target/avr/pr71151-3.c b/gcc/testsuite/gcc.target/avr/pr71151-3.c new file mode 100644 index 00000000000..a8fa6b63e0b --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71151-3.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fno-tree-switch-conversion -ffunction-sections -mno-relax -fdata-sections -Wl,--section-start=.foo=0x10000" } */ + +#ifdef __AVR_HAVE_ELPM__ +/* Make sure jumptables work properly if placed above 64 KB and below 128 KB, + i.e. 3 byte flash address for loading jump table entry and 2 byte jump table + entry, with relaxation disabled, after removing the special section + placement hook. */ +#define SECTION_NAME ".foo" +#else +/* No special jump table placement so that avrtest won't abort + for, e.g. ATmega64. */ +#define SECTION_NAME ".text.foo" +#endif + +#include "exit-abort.h" +#include "pr71151-common.h" + +int main() +{ + foo(5); + if (y != 37) + abort(); + + foo(0); + if (y != 67) + abort(); + + foo(7); + if (y != 98) + abort(); +} diff --git a/gcc/testsuite/gcc.target/avr/pr71151-4.c b/gcc/testsuite/gcc.target/avr/pr71151-4.c new file mode 100644 index 00000000000..659aff07510 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71151-4.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fno-tree-switch-conversion -ffunction-sections -fdata-sections -mrelax -Wl,--section-start=.foo=0x10000" } */ + +#ifdef __AVR_HAVE_ELPM__ +/* Make sure jumptables work properly if placed above 64 KB and below 128 KB, + i.e. 3 byte flash address for loading jump table entry and 2 byte jump + table entry, with relaxation enabled, after removing the special section + placement hook. */ +#define SECTION_NAME ".foo" +#else +/* No special jump table placement so that avrtest won't abort + for, e.g. ATmega64. */ +#define SECTION_NAME ".text.foo" +#endif + +#include "exit-abort.h" +#include "pr71151-common.h" + +int main() +{ + foo(5); + if (y != 37) + abort(); + + foo(0); + if (y != 67) + abort(); + + foo(7); + if (y != 98) + abort(); +} diff --git a/gcc/testsuite/gcc.target/avr/pr71151-5.c b/gcc/testsuite/gcc.target/avr/pr71151-5.c new file mode 100644 index 00000000000..f9b09e82083 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71151-5.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fno-tree-switch-conversion -ffunction-sections -fdata-sections -mno-relax -Wl,--section-start=.foo=0x20000" } */ + +#ifdef __AVR_3_BYTE_PC__ +/* Make sure jumptables work properly if placed above 128 KB, i.e. 3 byte + flash address for loading jump table entry and a jump table entry + that is a stub, with relaxation disabled, after removing the special + section placement hook. */ +#define SECTION_NAME ".foo" +#else +/* No special jump table placement so that avrtest won't abort + for, e.g. ATmega128. */ +#define SECTION_NAME ".text.foo" +#endif + +#include "exit-abort.h" +#include "pr71151-common.h" + +int main() +{ + foo(5); + if (y != 37) + abort(); + + foo(0); + if (y != 67) + abort(); + + foo(7); + if (y != 98) + abort(); +} diff --git a/gcc/testsuite/gcc.target/avr/pr71151-6.c b/gcc/testsuite/gcc.target/avr/pr71151-6.c new file mode 100644 index 00000000000..dedeffaa425 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71151-6.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fno-tree-switch-conversion -ffunction-sections -fdata-sections -mrelax -Wl,--section-start=.foo=0x20000" } */ + +#ifdef __AVR_3_BYTE_PC__ +/* Make sure jumptables work properly if placed above 128 KB, i.e. 3 byte + flash address for loading jump table entry and a jump table entry + that is a stub, with relaxation enabled, after removing the special + section placement hook. */ +#define SECTION_NAME ".foo" +#else +/* No special jump table placement so that avrtest won't abort + for, e.g. ATmega128. */ +#define SECTION_NAME ".text.foo" +#endif + +#include "exit-abort.h" +#include "pr71151-common.h" + +int main() +{ + foo(5); + if (y != 37) + abort(); + + foo(0); + if (y != 67) + abort(); + + foo(7); + if (y != 98) + abort(); +} diff --git a/gcc/testsuite/gcc.target/avr/pr71151-7.c b/gcc/testsuite/gcc.target/avr/pr71151-7.c new file mode 100644 index 00000000000..2a440960301 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71151-7.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fno-tree-switch-conversion -ffunction-sections -fdata-sections -mno-relax -Wl,--section-start=.foo=0x1fffa" } */ + +#ifdef __AVR_3_BYTE_PC__ +/* Make sure jumptables work properly if placed straddling 128 KB i.e + some entries below 128 KB and some above it, with relaxation disabled. */ +#define SECTION_NAME ".foo" +#else +/* No special jump table placement so that avrtest won't abort + for, e.g. ATmega128. */ +#define SECTION_NAME ".text.foo" +#endif + +#include "exit-abort.h" +#include "pr71151-common.h" + +int main() +{ + foo(5); + if (y != 37) + abort(); + + foo(0); + if (y != 67) + abort(); + + foo(7); + if (y != 98) + abort(); +} diff --git a/gcc/testsuite/gcc.target/avr/pr71151-8.c b/gcc/testsuite/gcc.target/avr/pr71151-8.c new file mode 100644 index 00000000000..aa3015b0455 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71151-8.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fno-tree-switch-conversion -ffunction-sections -fdata-sections -mrelax -Wl,--section-start=.foo=0x1fffa" } */ + +#ifdef __AVR_3_BYTE_PC__ +/* Make sure jumptables work properly if placed straddling 128 KB i.e + some entries below 128 KB and some above it, with relaxation disabled. */ +#define SECTION_NAME ".foo" +#else +/* No special jump table placement so that avrtest won't abort. */ +#define SECTION_NAME ".text.foo" +#endif + +#include "exit-abort.h" +#include "pr71151-common.h" + +int main() +{ + foo(5); + if (y != 37) + abort(); + + foo(0); + if (y != 67) + abort(); + + foo(7); + if (y != 98) + abort(); +} diff --git a/gcc/testsuite/gcc.target/avr/pr71151-common.h b/gcc/testsuite/gcc.target/avr/pr71151-common.h new file mode 100644 index 00000000000..43379be5d2c --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71151-common.h @@ -0,0 +1,27 @@ +volatile char y; +volatile char g; + +__attribute__((section(SECTION_NAME))) +void foo(char x) +{ + switch (x) + { + case 0: + y = 67; break; + case 1: + y = 20; break; + case 2: + y = 109; break; + case 3: + y = 33; break; + case 4: + y = 44; break; + case 5: + y = 37; break; + case 6: + y = 10; break; + case 7: + y = 98; break; + } + y = y + g; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/pr71103-2.c b/gcc/testsuite/gcc.target/avr/torture/pr71103-2.c new file mode 100644 index 00000000000..480ad05acab --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr71103-2.c @@ -0,0 +1,118 @@ +/* Use -g0 so that this test case doesn't just fail because + of PR52472. */ + +/* { dg-do compile } */ +/* { dg-options "-std=gnu99 -g0" } */ + +struct S12 +{ + char c; + const char *p; +}; + +struct S12f +{ + char c; + struct S12f (*f)(void); +}; + +struct S12labl +{ + char c; + void **labl; +}; + +struct S121 +{ + char c; + const char *p; + char d; +}; + +const char str[5] = "abcd"; + +struct S12 test_S12_0 (void) +{ + struct S12 s; + s.c = 'A'; + s.p = str; + return s; +} + +struct S12 test_S12_4 (void) +{ + struct S12 s; + s.c = 'A'; + s.p = str + 4; + return s; +} + +struct S12f test_S12f (void) +{ + struct S12f s; + s.c = 'A'; + s.f = test_S12f; + return s; +} + +struct S121 test_S121 (void) +{ + struct S121 s; + s.c = 'c'; + s.p = str + 4; + s.d = 'd'; + return s; +} + +extern void use_S12lab (struct S12labl*); + +struct S12labl test_S12lab (void) +{ + struct S12labl s; +labl:; + s.c = 'A'; + s.labl = &&labl; + return s; +} + +#ifdef __MEMX + +struct S13 +{ + char c; + const __memx char *p; +}; + +const __memx char str_x[] = "abcd"; + +struct S13 test_S13_0 (void) +{ + struct S13 s; + s.c = 'A'; + s.p = str_x; + return s; +} + +struct S13 test_S13_4a (void) +{ + struct S13 s; + s.c = 'A'; + s.p = str_x + 4; + return s; +} + +#ifdef __FLASH1 + +const __flash1 char str_1[] = "abcd"; + +struct S13 test_13_4b (void) +{ + struct S13 s; + s.c = 'A'; + s.p = str_1 + 4; + return s; +} + +#endif /* have __flash1 */ +#endif /* have __memx */ + diff --git a/gcc/testsuite/gcc.target/i386/avx-pr71559.c b/gcc/testsuite/gcc.target/i386/avx-pr71559.c new file mode 100644 index 00000000000..af16d56d785 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-pr71559.c @@ -0,0 +1,8 @@ +/* PR target/71559 */ +/* { dg-do run { target avx } } */ +/* { dg-options "-O2 -ftree-vectorize -mavx" } */ + +#include "avx-check.h" +#define PR71559_TEST avx_test + +#include "sse2-pr71559.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-1.c new file mode 100644 index 00000000000..fc48b1572b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = ceil (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != ceil (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-2.c new file mode 100644 index 00000000000..bf8af064cfe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-ceil-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscalepd\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-1.c new file mode 100644 index 00000000000..c6d53d89fc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) ceilf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) ceilf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-2.c new file mode 100644 index 00000000000..80e594dbfa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-ceilf-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dq\[^\n\]+zmm\[0-9\].{7}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-1.c new file mode 100644 index 00000000000..4788825fc3d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = ceilf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != ceilf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-2.c new file mode 100644 index 00000000000..95a79e29d12 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-ceilf-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-1.c new file mode 100644 index 00000000000..b7cbed005dd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = floor (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != floor (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-2.c new file mode 100644 index 00000000000..0d401f78d63 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-floor-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscalepd\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-1.c new file mode 100644 index 00000000000..6a25f438a8e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) floorf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) floorf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-2.c new file mode 100644 index 00000000000..f4bfec5385e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-floorf-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dq\[^\n\]+zmm\[0-9\].{7}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-1.c new file mode 100644 index 00000000000..69fc73d78ef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = floorf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != floorf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-2.c new file mode 100644 index 00000000000..90c6c0fade5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-floorf-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr71559.c b/gcc/testsuite/gcc.target/i386/avx512f-pr71559.c new file mode 100644 index 00000000000..d78d86ac2f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr71559.c @@ -0,0 +1,8 @@ +/* PR target/71559 */ +/* { dg-do run { target avx512f } } */ +/* { dg-options "-O2 -ftree-vectorize -mavx512f" } */ + +#include "avx512f-check.h" +#define PR71559_TEST avx512f_test + +#include "sse2-pr71559.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-1.c new file mode 100644 index 00000000000..8e1745aa13a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) rint (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) rint (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-2.c new file mode 100644 index 00000000000..c3f78ac3f25 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-rint-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vcvtpd2dq\[^\n\]+ymm\[0-9\](?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vinserti64x4\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-1.c new file mode 100644 index 00000000000..ac3e9a25973 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) rintf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) rintf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-2.c new file mode 100644 index 00000000000..c172e61f84a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-rintf-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vcvtps2dq\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-1.c new file mode 100644 index 00000000000..61bea578e18 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) round (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) round (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-2.c new file mode 100644 index 00000000000..5982c65d1e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-round-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscalepd\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dq\[^\n\]+zmm\[0-9\].{7}(?:\n|\[ \\t\]+#)" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-1.c new file mode 100644 index 00000000000..c5ec9e7ec00 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) roundf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) roundf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-2.c new file mode 100644 index 00000000000..0d8abb892d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-roundf-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dq\[^\n\]+zmm\[0-9\].{7}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-1.c new file mode 100644 index 00000000000..dfb93d72324 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = trunc (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != trunc (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-2.c new file mode 100644 index 00000000000..e8ec0227653 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-trunc-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscalepd\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-1.c new file mode 100644 index 00000000000..db13e712829 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = truncf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != truncf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-2.c new file mode 100644 index 00000000000..ae542d8276b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-truncf-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/fabsneg-1.c b/gcc/testsuite/gcc.target/i386/fabsneg-1.c new file mode 100644 index 00000000000..3cdf4566864 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fabsneg-1.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mtune=nocona" } */ + +double x; + +void +__attribute__ ((noinline, noclone)) +test_fabs (double a) +{ + asm volatile ("" : "+r" (a)); + x = __builtin_fabs (a); +} + +void +__attribute__ ((noinline, noclone)) +test_neg (double a) +{ + asm volatile ("" : "+r" (a)); + x = -a; +} + +int main () +{ + test_fabs (-1.0); + + if (x != 1.0) + __builtin_abort (); + + test_neg (-1.0); + + if (x != 1.0) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr68657.c b/gcc/testsuite/gcc.target/i386/pr68657.c new file mode 100644 index 00000000000..6f0d4987d39 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr68657.c @@ -0,0 +1,15 @@ +/* PR c/68657 */ +/* { dg-options "-mno-avx512f -Werror=psabi" } */ + +typedef int V __attribute__((vector_size (64))); + +void foo (V x, V *y) { /* { dg-error "AVX512F vector argument without AVX512F enabled" } */ + *y = x; +} + +V bar (V *x) { /* { dg-error "AVX512F vector return without AVX512F enabled" } */ + return *x; +} + +/* { dg-message "The ABI for passing parameters with 64-byte alignment has changed" "" { target *-*-* } 6 } */ +/* { dg-message "some warnings being treated as errors" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr70876.c b/gcc/testsuite/gcc.target/i386/pr70876.c new file mode 100644 index 00000000000..c9bab690b33 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70876.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! x32 } } } */ +/* { dg-options "-fcheck-pointer-bounds -mmpx -Wno-implicit-function-declaration" } */ + +void f (char *s1, char *s2) +{ + int z = 5; + + struct { char a[z]; } x; + + s1[0] = s2[0]; + + foo (x, x); +} diff --git a/gcc/testsuite/gcc.target/i386/pr70877.c b/gcc/testsuite/gcc.target/i386/pr70877.c new file mode 100644 index 00000000000..4269e84daff --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70877.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! x32 } } } */ +/* { dg-options "-fcheck-pointer-bounds -mmpx" } */ + +int foo(int); + +typedef struct { + double d; + int a; +} str_t; + +void bar(double d, int i, str_t s) +{ + d = ((double (*) (int)) foo) (i); /* { dg-warning "function called through a non-compatible type" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/pr71529.C b/gcc/testsuite/gcc.target/i386/pr71529.C new file mode 100644 index 00000000000..3169101e1a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr71529.C @@ -0,0 +1,22 @@ +/* PR71529 */ +/* { dg-do compile { target { ! x32 } } } */ +/* { dg-options "-fcheck-pointer-bounds -mmpx -O2" } */ + +class c1 +{ + public: + virtual ~c1 (); +}; + +class c2 +{ + public: + virtual ~c2 (); +}; + +class c3 : c1, c2 { }; + +int main (int, char **) +{ + c3 obj; +} diff --git a/gcc/testsuite/gcc.target/i386/pr71647.c b/gcc/testsuite/gcc.target/i386/pr71647.c new file mode 100644 index 00000000000..ab091bd93dd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr71647.c @@ -0,0 +1,32 @@ +/* PR tree-optimization/71647 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -fopenmp-simd -mavx -mno-avx512f -fdump-tree-vect-details" } */ + +void +foo (double *a, double *b) +{ + int i; +#pragma omp simd aligned(a,b:4*sizeof(double)) + for (i = 0; i < 32768; i++) + a[i] += b[i]; +} + +void +bar (double *a, double *b) +{ + int i; +#pragma omp simd aligned(a,b:32) + for (i = 0; i < 32768; i++) + a[i] += b[i]; +} + +void +baz (double *a, double *b) +{ + int i; +#pragma omp simd aligned(a,b:32L) + for (i = 0; i < 32768; i++) + a[i] += b[i]; +} + +/* { dg-final { scan-tree-dump-not "Alignment of access forced using peeling" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr76342.c b/gcc/testsuite/gcc.target/i386/pr76342.c new file mode 100644 index 00000000000..d492b00c1aa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr76342.c @@ -0,0 +1,11 @@ +/* PR target/76342 */ +/* { dg-do compile } */ +/* { dg-options "-mavx512f" } */ + +#include <immintrin.h> + +__m512i +test() +{ + return _mm512_undefined_epi32 (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-pr71559.c b/gcc/testsuite/gcc.target/i386/sse2-pr71559.c new file mode 100644 index 00000000000..59ecc7fb37f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-pr71559.c @@ -0,0 +1,73 @@ +/* PR target/71559 */ +/* { dg-do run { target sse2 } } */ +/* { dg-options "-O2 -ftree-vectorize -msse2" } */ + +#ifndef PR71559_TEST +#include "sse2-check.h" +#define PR71559_TEST sse2_test +#endif + +#define N 16 +float a[N] = { 5.0f, -3.0f, 1.0f, __builtin_nanf (""), 9.0f, 7.0f, -3.0f, -9.0f, + -3.0f, -5.0f, -9.0f, __builtin_nanf (""), 0.5f, -0.5f, 0.0f, 0.0f }; +float b[N] = { -5.0f, 3.0f, 1.0f, 7.0f, 8.0f, 8.0f, -3.0f, __builtin_nanf (""), + -4.0f, -4.0f, -9.0f, __builtin_nanf (""), 0.0f, 0.0f, 0.0f, __builtin_nanf ("") }; +int c[N], d[N]; + +#define FN(name, op) \ +void \ +name (void) \ +{ \ + int i; \ + for (i = 0; i < N; i++) \ + c[i] = (op || d[i] > 37) ? 5 : 32; \ +} +FN (eq, a[i] == b[i]) +FN (ne, a[i] != b[i]) +FN (gt, a[i] > b[i]) +FN (ge, a[i] >= b[i]) +FN (lt, a[i] < b[i]) +FN (le, a[i] <= b[i]) +FN (unle, !__builtin_isgreater (a[i], b[i])) +FN (unlt, !__builtin_isgreaterequal (a[i], b[i])) +FN (unge, !__builtin_isless (a[i], b[i])) +FN (ungt, !__builtin_islessequal (a[i], b[i])) +FN (uneq, !__builtin_islessgreater (a[i], b[i])) +FN (ordered, !__builtin_isunordered (a[i], b[i])) +FN (unordered, __builtin_isunordered (a[i], b[i])) + +#define TEST(name, GT, LT, EQ, UO) \ + name (); \ + for (i = 0; i < N; i++) \ + { \ + int v; \ + switch (i % 4) \ + { \ + case 0: v = GT ? 5 : 32; break; \ + case 1: v = LT ? 5 : 32; break; \ + case 2: v = EQ ? 5 : 32; break; \ + case 3: v = UO ? 5 : 32; break; \ + } \ + if (c[i] != v) \ + __builtin_abort (); \ + } + +void +PR71559_TEST (void) +{ + int i; + asm volatile ("" : : "g" (a), "g" (b), "g" (c), "g" (d) : "memory"); + TEST (eq, 0, 0, 1, 0) + TEST (ne, 1, 1, 0, 1) + TEST (gt, 1, 0, 0, 0) + TEST (ge, 1, 0, 1, 0) + TEST (lt, 0, 1, 0, 0) + TEST (le, 0, 1, 1, 0) + TEST (unle, 0, 1, 1, 1) + TEST (unlt, 0, 1, 0, 1) + TEST (unge, 1, 0, 1, 1) + TEST (ungt, 1, 0, 0, 1) + TEST (uneq, 0, 0, 1, 1) + TEST (ordered, 1, 1, 1, 0) + TEST (unordered, 0, 0, 0, 1) +} diff --git a/gcc/testsuite/gcc.target/powerpc/abs128-1.c b/gcc/testsuite/gcc.target/powerpc/abs128-1.c new file mode 100644 index 00000000000..49635df2b90 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/abs128-1.c @@ -0,0 +1,61 @@ +/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +void abort (); + +typedef unsigned long long int uint64_t; + +typedef union +{ + __float128 value; + + struct + { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + unsigned negative:1; + unsigned exponent:15; + unsigned quiet_nan:1; + uint64_t mant_high:47; + uint64_t mant_low:64; +#else + uint64_t mant_low:64; + uint64_t mant_high:47; + unsigned quiet_nan:1; + unsigned exponent:15; + unsigned negative:1; +#endif + } nan; + +} ieee854_float128; + +int +main (int argc, int *argv[]) +{ + ieee854_float128 x, z; + + x.nan.negative = 1; + x.nan.exponent = 0x22; + x.nan.quiet_nan = 0; + x.nan.mant_high = 0x1234; + x.nan.mant_low = 0xabcdef; + + z.value = __builtin_fabsq (x.value); + + if (z.nan.negative != 0 + || z.nan.exponent != 0x22 + || z.nan.quiet_nan != 0 + || z.nan.mant_high != 0x1234 + || z.nan.mant_low != 0xabcdef) + abort (); + + z.value = __builtin_fabsq (z.value); + + if (z.nan.negative != 0 + || z.nan.exponent != 0x22 + || z.nan.quiet_nan != 0 + || z.nan.mant_high != 0x1234 + || z.nan.mant_low != 0xabcdef) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/copysign128-1.c b/gcc/testsuite/gcc.target/powerpc/copysign128-1.c new file mode 100644 index 00000000000..429dfc072e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/copysign128-1.c @@ -0,0 +1,58 @@ +/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +void abort (); + +typedef unsigned long long int uint64_t; + +typedef union +{ + __float128 value; + + struct + { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + unsigned negative:1; + unsigned exponent:15; + unsigned quiet_nan:1; + uint64_t mant_high:47; + uint64_t mant_low:64; +#else + uint64_t mant_low:64; + uint64_t mant_high:47; + unsigned quiet_nan:1; + unsigned exponent:15; + unsigned negative:1; +#endif + } nan; + +} ieee854_float128; + +int +main (int argc, int *argv[]) +{ + ieee854_float128 x, y, z; + + x.nan.negative = 0; + x.nan.exponent = 0x22; + x.nan.quiet_nan = 0; + x.nan.mant_high = 0x1234; + x.nan.mant_low = 0xabcdef; + + y.nan.negative = 1; + y.nan.exponent = 0; + y.nan.quiet_nan = 0; + y.nan.mant_high = 0; + y.nan.mant_low = 0; + + z.value = __builtin_copysignq (x.value, y.value); + + if (z.nan.negative != 1 + || z.nan.exponent != 0x22 + || z.nan.quiet_nan != 0 + || z.nan.mant_high != 0x1234 + || z.nan.mant_low != 0xabcdef) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ctz-3.c b/gcc/testsuite/gcc.target/powerpc/ctz-3.c new file mode 100644 index 00000000000..468a1f93540 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ctz-3.c @@ -0,0 +1,62 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +#ifndef ALIGN +#define ALIGN 32 +#endif + +#define ALIGN_ATTR __attribute__((__aligned__(ALIGN))) + +#define DO_BUILTIN(PREFIX, TYPE, CTZ) \ +TYPE PREFIX ## _a[SIZE] ALIGN_ATTR; \ +TYPE PREFIX ## _b[SIZE] ALIGN_ATTR; \ + \ +void \ +PREFIX ## _ctz (void) \ +{ \ + unsigned long i; \ + \ + for (i = 0; i < SIZE; i++) \ + PREFIX ## _a[i] = CTZ (PREFIX ## _b[i]); \ +} + +#if !defined(DO_LONG_LONG) && !defined(DO_LONG) && !defined(DO_INT) && !defined(DO_SHORT) && !defined(DO_CHAR) +#define DO_INT 1 +#endif + +#if DO_LONG_LONG +/* At the moment, only int is auto vectorized. */ +DO_BUILTIN (sll, long long, __builtin_ctzll) +DO_BUILTIN (ull, unsigned long long, __builtin_ctzll) +#endif + +#if defined(_ARCH_PPC64) && DO_LONG +DO_BUILTIN (sl, long, __builtin_ctzl) +DO_BUILTIN (ul, unsigned long, __builtin_ctzl) +#endif + +#if DO_INT +DO_BUILTIN (si, int, __builtin_ctz) +DO_BUILTIN (ui, unsigned int, __builtin_ctz) +#endif + +#if DO_SHORT +DO_BUILTIN (ss, short, __builtin_ctz) +DO_BUILTIN (us, unsigned short, __builtin_ctz) +#endif + +#if DO_CHAR +DO_BUILTIN (sc, signed char, __builtin_ctz) +DO_BUILTIN (uc, unsigned char, __builtin_ctz) +#endif + +/* { dg-final { scan-assembler-times "vctzw" 2 } } */ +/* { dg-final { scan-assembler-not "cnttzd" } } */ +/* { dg-final { scan-assembler-not "cnttzw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ctz-4.c b/gcc/testsuite/gcc.target/powerpc/ctz-4.c new file mode 100644 index 00000000000..2d04a9b6579 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ctz-4.c @@ -0,0 +1,110 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +#include <altivec.h> + +vector signed char +count_trailing_zeros_v16qi_1s (vector signed char a) +{ + return vec_vctz (a); +} + +vector signed char +count_trailing_zeros_v16qi_2s (vector signed char a) +{ + return vec_vctzb (a); +} + +vector unsigned char +count_trailing_zeros_v16qi_1u (vector unsigned char a) +{ + return vec_vctz (a); +} + +vector unsigned char +count_trailing_zeros_v16qi_2u (vector unsigned char a) +{ + return vec_vctzb (a); +} + +vector short +count_trailing_zeros_v8hi_1s (vector short a) +{ + return vec_vctz (a); +} + +vector short +count_trailing_zeros_v8hi_2s (vector short a) +{ + return vec_vctzh (a); +} + +vector unsigned short +count_trailing_zeros_v8hi_1u (vector unsigned short a) +{ + return vec_vctz (a); +} + +vector unsigned short +count_trailing_zeros_v8hi_2u (vector unsigned short a) +{ + return vec_vctzh (a); +} + +vector int +count_trailing_zeros_v4si_1s (vector int a) +{ + return vec_vctz (a); +} + +vector int +count_trailing_zeros_v4si_2s (vector int a) +{ + return vec_vctzw (a); +} + +vector unsigned int +count_trailing_zeros_v4si_1u (vector unsigned int a) +{ + return vec_vctz (a); +} + +vector unsigned int +count_trailing_zeros_v4si_2u (vector unsigned int a) +{ + return vec_vctzw (a); +} + +vector long long +count_trailing_zeros_v2di_1s (vector long long a) +{ + return vec_vctz (a); +} + +vector long long +count_trailing_zeros_v2di_2s (vector long long a) +{ + return vec_vctzd (a); +} + +vector unsigned long long +count_trailing_zeros_v2di_1u (vector unsigned long long a) +{ + return vec_vctz (a); +} + +vector unsigned long long +count_trailing_zeros_v2di_2u (vector unsigned long long a) +{ + return vec_vctzd (a); +} + +/* { dg-final { scan-assembler "vctzb" } } */ +/* { dg-final { scan-assembler "vctzd" } } */ +/* { dg-final { scan-assembler "vctzh" } } */ +/* { dg-final { scan-assembler "vctzw" } } */ +/* { dg-final { scan-assembler-not "cnttzd" } } */ +/* { dg-final { scan-assembler-not "cnttzw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/darn-0.c b/gcc/testsuite/gcc.target/powerpc/darn-0.c new file mode 100644 index 00000000000..fc150766108 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darn-0.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int get_random () +{ + return __builtin_darn_32 (); +} + +/* { dg-final { scan-assembler "darn" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/darn-1.c b/gcc/testsuite/gcc.target/powerpc/darn-1.c new file mode 100644 index 00000000000..9b7482d6551 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darn-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +long long get_conditioned_random () +{ + return __builtin_darn (); +} + +/* { dg-final { scan-assembler "darn" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/darn-2.c b/gcc/testsuite/gcc.target/powerpc/darn-2.c new file mode 100644 index 00000000000..84493602cfc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darn-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +long long get_raw_random () +{ + return __builtin_darn_raw (); +} + +/* { dg-final { scan-assembler "darn" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dform-3.c b/gcc/testsuite/gcc.target/powerpc/dform-3.c new file mode 100644 index 00000000000..b1c481fbf6d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dform-3.c @@ -0,0 +1,39 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ + +#ifndef TYPE +#define TYPE vector double +#endif + +struct foo { + TYPE a, b, c, d; +}; + +/* Test whether ISA 3.0 vector d-form instructions are implemented. */ +void +add (struct foo *p) +{ + p->b = p->c + p->d; +} + +/* Make sure we don't use direct moves to get stuff into GPR registers. */ +void +gpr (struct foo *p) +{ + TYPE x = p->c; + + __asm__ (" # reg = %0" : "+r" (x)); + + p->b = x; +} + +/* { dg-final { scan-assembler "lxv " } } */ +/* { dg-final { scan-assembler "stxv " } } */ +/* { dg-final { scan-assembler-not "lxvx " } } */ +/* { dg-final { scan-assembler-not "stxvx " } } */ +/* { dg-final { scan-assembler-not "mfvsrd " } } */ +/* { dg-final { scan-assembler-not "mfvsrld " } } */ +/* { dg-final { scan-assembler "l\[dq\] " } } */ +/* { dg-final { scan-assembler "st\[dq\] " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dfp.exp b/gcc/testsuite/gcc.target/powerpc/dfp/dfp.exp new file mode 100644 index 00000000000..081946f7fbf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dfp.exp @@ -0,0 +1,39 @@ +# Copyright (C) 2014-2016 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# Exit immediately if this isn't a PowerPC target. +if { ![istarget powerpc*-*-*] && ![istarget rs6000-*-*] } then { + return +} + +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Load support procs. +load_lib gcc-dg.exp +load_lib torture-options.exp + +# Initialize. +dg-init + +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c*]] "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c new file mode 100644 index 00000000000..29859c55986 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c new file mode 100644 index 00000000000..d634a2acd04 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c new file mode 100644 index 00000000000..a56f19ba391 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt_dd (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c new file mode 100644 index 00000000000..523facea156 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c new file mode 100644 index 00000000000..e62e4bc7bbe --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c new file mode 100644 index 00000000000..38bff163c02 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_lt_dd (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c new file mode 100644 index 00000000000..57fc81ad742 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c new file mode 100644 index 00000000000..990461f9c53 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt_td (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c new file mode 100644 index 00000000000..dcd4a16635f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c new file mode 100644 index 00000000000..5fbf5b5cc0c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c new file mode 100644 index 00000000000..675109552b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_lt_td (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c new file mode 100644 index 00000000000..d24eb10f7a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c new file mode 100644 index 00000000000..d66ba886a92 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c new file mode 100644 index 00000000000..e42f0debc82 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c new file mode 100644 index 00000000000..975843c6a02 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c new file mode 100644 index 00000000000..d6eced78f6a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c new file mode 100644 index 00000000000..eccca7e5d85 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_gt (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c new file mode 100644 index 00000000000..54f1cd3d134 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c new file mode 100644 index 00000000000..0c6594ecf46 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c new file mode 100644 index 00000000000..e30c2f4ac79 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c new file mode 100644 index 00000000000..aaa0a854370 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c new file mode 100644 index 00000000000..efec051639a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_gt (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c new file mode 100644 index 00000000000..2f84bbfd36a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c new file mode 100644 index 00000000000..ac0380973f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_lt (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c new file mode 100644 index 00000000000..cfa8d0d2817 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt_dd (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c new file mode 100644 index 00000000000..a95dcb8dbb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c new file mode 100644 index 00000000000..512e1574555 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c new file mode 100644 index 00000000000..f21399e9d62 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_gt_dd (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c new file mode 100644 index 00000000000..86422831975 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c new file mode 100644 index 00000000000..5987b438970 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt_td (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c new file mode 100644 index 00000000000..00be5389310 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c new file mode 100644 index 00000000000..dcbde72a7f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c new file mode 100644 index 00000000000..c892c100aa8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_gt_td (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c new file mode 100644 index 00000000000..d54138d8c5c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c new file mode 100644 index 00000000000..f00756aa23c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c new file mode 100644 index 00000000000..6b2ecf775d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c new file mode 100644 index 00000000000..c84387dc38b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c new file mode 100644 index 00000000000..f193b415007 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c new file mode 100644 index 00000000000..0de23f4f225 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_eq (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c new file mode 100644 index 00000000000..41652c99f6f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c new file mode 100644 index 00000000000..4ef2d555d43 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c new file mode 100644 index 00000000000..f1d6e2de80f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c new file mode 100644 index 00000000000..c85b709f228 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c new file mode 100644 index 00000000000..94962fcff2f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_eq (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c new file mode 100644 index 00000000000..79190d0dde0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c new file mode 100644 index 00000000000..2aadb7e7dc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c new file mode 100644 index 00000000000..3d9869d39f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq_dd (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c new file mode 100644 index 00000000000..58f542673de --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c new file mode 100644 index 00000000000..382fdc21060 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c new file mode 100644 index 00000000000..067c2071b4b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_eq_dd (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c new file mode 100644 index 00000000000..ac2c692b51f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c new file mode 100644 index 00000000000..cd732fbc885 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq_td (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c new file mode 100644 index 00000000000..7efb1a3d0f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c new file mode 100644 index 00000000000..74ff7ec0d50 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c new file mode 100644 index 00000000000..d6ee4f72a75 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_eq_td (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c new file mode 100644 index 00000000000..acd2a208379 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c new file mode 100644 index 00000000000..1bddb651b0e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c new file mode 100644 index 00000000000..71eab2609b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c new file mode 100644 index 00000000000..247c1448a70 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c new file mode 100644 index 00000000000..fbe137de7f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c new file mode 100644 index 00000000000..18d17f36ee3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_ov (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c new file mode 100644 index 00000000000..6e601160ef7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c new file mode 100644 index 00000000000..2ad93313760 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c new file mode 100644 index 00000000000..69272acb47a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c new file mode 100644 index 00000000000..a9ba111b82f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c new file mode 100644 index 00000000000..bd8040a175a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_ov (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c new file mode 100644 index 00000000000..078f232cb4a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c new file mode 100644 index 00000000000..1875741f5c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c new file mode 100644 index 00000000000..f84faf8022b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov_dd (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c new file mode 100644 index 00000000000..3e512038cf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c new file mode 100644 index 00000000000..044d039b464 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c new file mode 100644 index 00000000000..52a5d9a5664 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_ov_dd (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c new file mode 100644 index 00000000000..2dd72ee1253 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c new file mode 100644 index 00000000000..6bbe73b7511 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov_td (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c new file mode 100644 index 00000000000..572897fee55 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c new file mode 100644 index 00000000000..4b725377e09 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c new file mode 100644 index 00000000000..c302027e3be --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_ov_td (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c new file mode 100644 index 00000000000..789b3ada11a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c new file mode 100644 index 00000000000..d3aa64efa97 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_lt (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c new file mode 100644 index 00000000000..9180e3e9a01 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/divkc3-1.c b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c new file mode 100644 index 00000000000..89bf04f12a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c @@ -0,0 +1,22 @@ +/* { dg-do run { target { powerpc64*-*-* && p8vector_hw } } } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +void abort (); + +typedef __complex float __cfloat128 __attribute__((mode(KC))); + +__cfloat128 divide (__cfloat128 x, __cfloat128 y) +{ + return x / y; +} + +__cfloat128 z, a; + +int main () +{ + z = divide (5.0q + 5.0jq, 2.0q + 1.0jq); + a = 3.0q + 1.0jq; + if (z != a) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmp.c b/gcc/testsuite/gcc.target/powerpc/float128-cmp.c new file mode 100644 index 00000000000..247abc0f7d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmp.c @@ -0,0 +1,106 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target ppc_float128_sw } */ +/* { dg-options "-mvsx -O2 -mfloat128" } */ + +#include <stddef.h> +#include <stdlib.h> + +#ifndef TYPE +#define TYPE __float128 +#define NAN __builtin_nanq ("") +#define SNAN __builtin_nansq ("") +#else +#define NAN __builtin_nan ("") +#define SNAN __builtin_nans ("") +#endif + +extern void check (TYPE a, + TYPE b, + int eq, + int ne, + int lt, + int le, + int gt, + int ge, + int i_lt, + int i_le, + int i_gt, + int i_ge, + int i_lg, + int i_un) __attribute__((__noinline__)); + +void +check (TYPE a, + TYPE b, + int eq, + int ne, + int lt, + int le, + int gt, + int ge, + int i_lt, + int i_le, + int i_gt, + int i_ge, + int i_lg, + int i_un) +{ + if (eq != (a == b)) + abort (); + + if (ne != (a != b)) + abort (); + + if (lt != (a < b)) + abort (); + + if (le != (a <= b)) + abort (); + + if (gt != (a > b)) + abort (); + + if (ge != (a >= b)) + abort (); + + if (i_lt != __builtin_isless (a, b)) + abort (); + + if (i_le != __builtin_islessequal (a, b)) + abort (); + + if (i_gt != __builtin_isgreater (a, b)) + abort (); + + if (i_ge != __builtin_isgreaterequal (a, b)) + abort (); + + if (i_lg != __builtin_islessgreater (a, b)) + abort (); + + if (i_un != __builtin_isunordered (a, b)) + abort (); +} + +int main (void) +{ + TYPE one = (TYPE) +1.0; + TYPE two = (TYPE) +2.0; + TYPE pzero = (TYPE) +0.0; + TYPE mzero = (TYPE) -0.0; + TYPE nan = (TYPE) NAN; + TYPE snan = (TYPE) SNAN; + + check (one, two, 0, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0); + check (one, one, 1, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0); + check (one, pzero, 0, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 0); + check (mzero, pzero, 1, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0); + check (nan, one, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1); + check (one, nan, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1); + check (nan, nan, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1); + check (snan, one, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1); + check (one, snan, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1); + check (snan, nan, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1); + check (nan, snan, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/float128-complex-1.c b/gcc/testsuite/gcc.target/powerpc/float128-complex-1.c new file mode 100644 index 00000000000..4e3b3253caf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-complex-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target powerpc_float128_sw_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-options "-O2 -mcpu=power7 -mfloat128" } */ + +#ifndef NO_FLOAT +typedef _Complex float float_complex; +extern float_complex cfloat1 (void); +extern float_complex cfloat2 (void); + +#define FLOAT_ARG(NAME, OP) ARG_OP(float, float_complex, NAME, OP) +#define FLOAT_PTR(NAME, OP) PTR_OP(float, float_complex, NAME, OP) +#define FLOAT_CALL() CALL_OP(float, float_complex, cfloat1, cfloat2) + +#else +#define FLOAT_ARG(NAME, OP) +#define FLOAT_PTR(NAME, OP) +#define FLOAT_CALL() +#endif + +#ifndef NO_DOUBLE +typedef _Complex double double_complex; +extern double_complex cdouble1 (void); +extern double_complex cdouble2 (void); + +#define DOUBLE_ARG(NAME, OP) ARG_OP(double, double_complex, NAME, OP) +#define DOUBLE_PTR(NAME, OP) PTR_OP(double, double_complex, NAME, OP) +#define DOUBLE_CALL() CALL_OP(double, double_complex, cdouble1, cdouble2) + +#else +#define DOUBLE_ARG(NAME, OP) +#define DOUBLE_PTR(NAME, OP) +#define DOUBLE_CALL() +#endif + +#ifndef NO_FLOAT128 +#ifdef __VSX__ +typedef _Complex float __attribute__((mode(KC))) float128_complex; +#else +typedef _Complex float __attribute__((mode(TC))) float128_complex; +#endif + +extern float128_complex cfloat128_1 (void); +extern float128_complex cfloat128_2 (void); + +#define FLOAT128_ARG(NAME, OP) ARG_OP(float128, float128_complex, NAME, OP) +#define FLOAT128_PTR(NAME, OP) PTR_OP(float128, float128_complex, NAME, OP) +#define FLOAT128_CALL() CALL_OP(float128, float128_complex, cfloat128_1, cfloat128_2) + +#else +#define FLOAT128_ARG(NAME, OP) +#define FLOAT128_PTR(NAME, OP) +#define FLOAT128_CALL() +#endif + +#ifndef NO_LDOUBLE +typedef _Complex long double ldouble_complex; +extern ldouble_complex cldouble1 (void); +extern ldouble_complex cldouble2 (void); + +#define LDOUBLE_ARG(NAME, OP) ARG_OP(ldouble, ldouble_complex, NAME, OP) +#define LDOUBLE_PTR(NAME, OP) PTR_OP(ldouble, ldouble_complex, NAME, OP) +#define LDOUBLE_CALL() CALL_OP(ldouble, ldouble_complex, cldouble1, cldouble2) + +#else +#define LDOUBLE_ARG(NAME, OP) +#define LDOUBLE_PTR(NAME, OP) +#define LDOUBLE_CALL() +#endif + + +#define ARG_OP(SUFFIX, TYPE, NAME, OP) \ +TYPE arg_ ## NAME ## _ ## SUFFIX (TYPE a, TYPE b) \ +{ \ + return a OP b; \ +} + +#define PTR_OP(SUFFIX, TYPE, NAME, OP) \ +void ptr_ ## NAME ## _ ## SUFFIX (TYPE *p, TYPE *a, TYPE *b) \ +{ \ + *p = *a OP *b; \ +} + +#define CALL_OP(SUFFIX, TYPE, FUNC1, FUNC2) \ +TYPE call_ ## SUFFIX (void) \ +{ \ + TYPE value1 = FUNC1 (); \ + TYPE value2 = FUNC2 (); \ + return value1 + value2; \ +} + +#ifndef NO_ARG +#ifndef NO_ADD +FLOAT_ARG (add, +) +DOUBLE_ARG (add, +) +FLOAT128_ARG (add, +) +LDOUBLE_ARG (add, +) +#endif + +#ifndef NO_SUB +FLOAT_ARG (sub, -) +DOUBLE_ARG (sub, -) +FLOAT128_ARG (sub, -) +LDOUBLE_ARG (sub, -) +#endif + +#ifndef NO_MUL +FLOAT_ARG (mul, *) +DOUBLE_ARG (mul, *) +FLOAT128_ARG (mul, *) +LDOUBLE_ARG (mul, *) +#endif + +#ifndef NO_DIV +FLOAT_ARG (div, /) +DOUBLE_ARG (div, /) +FLOAT128_ARG (div, /) +LDOUBLE_ARG (div, /) +#endif +#endif + +#ifndef NO_PTR +#ifndef NO_ADD +FLOAT_PTR (add, +) +DOUBLE_PTR (add, +) +FLOAT128_PTR (add, +) +LDOUBLE_PTR (add, +) +#endif + +#ifndef NO_SUB +FLOAT_PTR (sub, -) +DOUBLE_PTR (sub, -) +FLOAT128_PTR (sub, -) +LDOUBLE_PTR (sub, -) +#endif + +#ifndef NO_MUL +FLOAT_PTR (mul, *) +DOUBLE_PTR (mul, *) +FLOAT128_PTR (mul, *) +LDOUBLE_PTR (mul, *) +#endif + +#ifndef NO_DIV +FLOAT_PTR (div, /) +DOUBLE_PTR (div, /) +FLOAT128_PTR (div, /) +LDOUBLE_PTR (div, /) +#endif +#endif + +#ifndef NO_CALL +FLOAT_CALL () +DOUBLE_CALL () +FLOAT128_CALL () +LDOUBLE_CALL () +#endif diff --git a/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c b/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c new file mode 100644 index 00000000000..06dd8e2f01b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target powerpc_float128_hw_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-O2 -mcpu=power9 -mfloat128 -mfloat128-hardware" } */ + +#ifndef NO_FLOAT +typedef _Complex float float_complex; +extern float_complex cfloat1 (void); +extern float_complex cfloat2 (void); + +#define FLOAT_ARG(NAME, OP) ARG_OP(float, float_complex, NAME, OP) +#define FLOAT_PTR(NAME, OP) PTR_OP(float, float_complex, NAME, OP) +#define FLOAT_CALL() CALL_OP(float, float_complex, cfloat1, cfloat2) + +#else +#define FLOAT_ARG(NAME, OP) +#define FLOAT_PTR(NAME, OP) +#define FLOAT_CALL() +#endif + +#ifndef NO_DOUBLE +typedef _Complex double double_complex; +extern double_complex cdouble1 (void); +extern double_complex cdouble2 (void); + +#define DOUBLE_ARG(NAME, OP) ARG_OP(double, double_complex, NAME, OP) +#define DOUBLE_PTR(NAME, OP) PTR_OP(double, double_complex, NAME, OP) +#define DOUBLE_CALL() CALL_OP(double, double_complex, cdouble1, cdouble2) + +#else +#define DOUBLE_ARG(NAME, OP) +#define DOUBLE_PTR(NAME, OP) +#define DOUBLE_CALL() +#endif + +#ifndef NO_FLOAT128 +#ifdef __VSX__ +typedef _Complex float __attribute__((mode(KC))) float128_complex; +#else +typedef _Complex float __attribute__((mode(TC))) float128_complex; +#endif + +extern float128_complex cfloat128_1 (void); +extern float128_complex cfloat128_2 (void); + +#define FLOAT128_ARG(NAME, OP) ARG_OP(float128, float128_complex, NAME, OP) +#define FLOAT128_PTR(NAME, OP) PTR_OP(float128, float128_complex, NAME, OP) +#define FLOAT128_CALL() CALL_OP(float128, float128_complex, cfloat128_1, cfloat128_2) + +#else +#define FLOAT128_ARG(NAME, OP) +#define FLOAT128_PTR(NAME, OP) +#define FLOAT128_CALL() +#endif + +#ifndef NO_LDOUBLE +typedef _Complex long double ldouble_complex; +extern ldouble_complex cldouble1 (void); +extern ldouble_complex cldouble2 (void); + +#define LDOUBLE_ARG(NAME, OP) ARG_OP(ldouble, ldouble_complex, NAME, OP) +#define LDOUBLE_PTR(NAME, OP) PTR_OP(ldouble, ldouble_complex, NAME, OP) +#define LDOUBLE_CALL() CALL_OP(ldouble, ldouble_complex, cldouble1, cldouble2) + +#else +#define LDOUBLE_ARG(NAME, OP) +#define LDOUBLE_PTR(NAME, OP) +#define LDOUBLE_CALL() +#endif + + +#define ARG_OP(SUFFIX, TYPE, NAME, OP) \ +TYPE arg_ ## NAME ## _ ## SUFFIX (TYPE a, TYPE b) \ +{ \ + return a OP b; \ +} + +#define PTR_OP(SUFFIX, TYPE, NAME, OP) \ +void ptr_ ## NAME ## _ ## SUFFIX (TYPE *p, TYPE *a, TYPE *b) \ +{ \ + *p = *a OP *b; \ +} + +#define CALL_OP(SUFFIX, TYPE, FUNC1, FUNC2) \ +TYPE call_ ## SUFFIX (void) \ +{ \ + TYPE value1 = FUNC1 (); \ + TYPE value2 = FUNC2 (); \ + return value1 + value2; \ +} + +#ifndef NO_ARG +#ifndef NO_ADD +FLOAT_ARG (add, +) +DOUBLE_ARG (add, +) +FLOAT128_ARG (add, +) +LDOUBLE_ARG (add, +) +#endif + +#ifndef NO_SUB +FLOAT_ARG (sub, -) +DOUBLE_ARG (sub, -) +FLOAT128_ARG (sub, -) +LDOUBLE_ARG (sub, -) +#endif + +#ifndef NO_MUL +FLOAT_ARG (mul, *) +DOUBLE_ARG (mul, *) +FLOAT128_ARG (mul, *) +LDOUBLE_ARG (mul, *) +#endif + +#ifndef NO_DIV +FLOAT_ARG (div, /) +DOUBLE_ARG (div, /) +FLOAT128_ARG (div, /) +LDOUBLE_ARG (div, /) +#endif +#endif + +#ifndef NO_PTR +#ifndef NO_ADD +FLOAT_PTR (add, +) +DOUBLE_PTR (add, +) +FLOAT128_PTR (add, +) +LDOUBLE_PTR (add, +) +#endif + +#ifndef NO_SUB +FLOAT_PTR (sub, -) +DOUBLE_PTR (sub, -) +FLOAT128_PTR (sub, -) +LDOUBLE_PTR (sub, -) +#endif + +#ifndef NO_MUL +FLOAT_PTR (mul, *) +DOUBLE_PTR (mul, *) +FLOAT128_PTR (mul, *) +LDOUBLE_PTR (mul, *) +#endif + +#ifndef NO_DIV +FLOAT_PTR (div, /) +DOUBLE_PTR (div, /) +FLOAT128_PTR (div, /) +LDOUBLE_PTR (div, /) +#endif +#endif + +#ifndef NO_CALL +FLOAT_CALL () +DOUBLE_CALL () +FLOAT128_CALL () +LDOUBLE_CALL () +#endif + +/* { dg-final { scan-assembler "xsaddqp" } } */ +/* { dg-final { scan-assembler "xssubqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/inf128-1.c b/gcc/testsuite/gcc.target/powerpc/inf128-1.c new file mode 100644 index 00000000000..df797e33220 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/inf128-1.c @@ -0,0 +1,55 @@ +/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +void abort (); + +typedef unsigned long long int uint64_t; + +typedef union +{ + __float128 value; + + struct + { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + unsigned negative:1; + unsigned exponent:15; + unsigned quiet_nan:1; + uint64_t mant_high:47; + uint64_t mant_low:64; +#else + uint64_t mant_low:64; + uint64_t mant_high:47; + unsigned quiet_nan:1; + unsigned exponent:15; + unsigned negative:1; +#endif + } nan; + +} ieee854_float128; + +int +main (int argc, int *argv[]) +{ + ieee854_float128 y; + + y.value = __builtin_infq (); + + if (y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 0 + || y.nan.mant_high != 0 + || y.nan.mant_low != 0) + abort (); + + y.value = __builtin_huge_valq (); + + if (y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 0 + || y.nan.mant_high != 0 + || y.nan.mant_low != 0) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/mulkc3-1.c b/gcc/testsuite/gcc.target/powerpc/mulkc3-1.c new file mode 100644 index 00000000000..b975a91dbd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mulkc3-1.c @@ -0,0 +1,22 @@ +/* { dg-do run { target { powerpc64*-*-* && p8vector_hw } } } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +void abort (); + +typedef __complex float __cfloat128 __attribute__((mode(KC))); + +__cfloat128 multiply (__cfloat128 x, __cfloat128 y) +{ + return x * y; +} + +__cfloat128 z, a; + +int main () +{ + z = multiply (2.0q + 1.0jq, 3.0q + 1.0jq); + a = 5.0q + 5.0jq; + if (z != a) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/nan128-1.c b/gcc/testsuite/gcc.target/powerpc/nan128-1.c new file mode 100644 index 00000000000..e327f40f837 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/nan128-1.c @@ -0,0 +1,77 @@ +/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +#include <stdio.h> + +void abort (); + +typedef unsigned long long int uint64_t; + +typedef union +{ + __float128 value; + + struct + { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + unsigned negative:1; + unsigned exponent:15; + unsigned quiet_nan:1; + uint64_t mant_high:47; + uint64_t mant_low:64; +#else + uint64_t mant_low:64; + uint64_t mant_high:47; + unsigned quiet_nan:1; + unsigned exponent:15; + unsigned negative:1; +#endif + } nan; + +} ieee854_float128; + +int +main (int argc, int *argv[]) +{ + ieee854_float128 y; + + y.value = __builtin_nanq ("1"); + + if (y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 1 + || y.nan.mant_high != 0 + || y.nan.mant_low != 1) + abort (); + + y.value = __builtin_nanq ("0x2ab3c"); + + if (y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 1 + || y.nan.mant_high != 0 + || y.nan.mant_low != 0x2ab3c) + abort (); + + y.value = __builtin_nansq ("1"); + + if ( + y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 0 + || y.nan.mant_high != 0 + || y.nan.mant_low != 1 + ) + abort (); + + y.value = __builtin_nansq ("0x2ab3c"); + + if (y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 0 + || y.nan.mant_high != 0 + || y.nan.mant_low != 0x2ab3c) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c b/gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c new file mode 100644 index 00000000000..c182da9470e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c @@ -0,0 +1,171 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2 -mpower9-minmax -ffast-math" } */ +/* { dg-final { scan-assembler-not "fsel" } } */ +/* { dg-final { scan-assembler "xscmpeqdp" } } */ +/* { dg-final { scan-assembler "xscmpgtdp" } } */ +/* { dg-final { scan-assembler "xscmpgedp" } } */ +/* { dg-final { scan-assembler-not "xscmpodp" } } */ +/* { dg-final { scan-assembler-not "xscmpudp" } } */ +/* { dg-final { scan-assembler "xsmaxcdp" } } */ +/* { dg-final { scan-assembler-not "xsmaxdp" } } */ +/* { dg-final { scan-assembler "xsmincdp" } } */ +/* { dg-final { scan-assembler-not "xsmindp" } } */ +/* { dg-final { scan-assembler "xxsel" } } */ + +double +dbl_max1 (double a, double b) +{ + return (a >= b) ? a : b; +} + +double +dbl_max2 (double a, double b) +{ + return (a > b) ? a : b; +} + +double +dbl_min1 (double a, double b) +{ + return (a < b) ? a : b; +} + +double +dbl_min2 (double a, double b) +{ + return (a <= b) ? a : b; +} + +double +dbl_cmp_eq (double a, double b, double c, double d) +{ + return (a == b) ? c : d; +} + +double +dbl_cmp_ne (double a, double b, double c, double d) +{ + return (a != b) ? c : d; +} + +double +dbl_cmp_gt (double a, double b, double c, double d) +{ + return (a > b) ? c : d; +} + +double +dbl_cmp_ge (double a, double b, double c, double d) +{ + return (a >= b) ? c : d; +} + +double +dbl_cmp_lt (double a, double b, double c, double d) +{ + return (a < b) ? c : d; +} + +double +dbl_cmp_le (double a, double b, double c, double d) +{ + return (a <= b) ? c : d; +} + +float +flt_max1 (float a, float b) +{ + return (a >= b) ? a : b; +} + +float +flt_max2 (float a, float b) +{ + return (a > b) ? a : b; +} + +float +flt_min1 (float a, float b) +{ + return (a < b) ? a : b; +} + +float +flt_min2 (float a, float b) +{ + return (a <= b) ? a : b; +} + +float +flt_cmp_eq (float a, float b, float c, float d) +{ + return (a == b) ? c : d; +} + +float +flt_cmp_ne (float a, float b, float c, float d) +{ + return (a != b) ? c : d; +} + +float +flt_cmp_gt (float a, float b, float c, float d) +{ + return (a > b) ? c : d; +} + +float +flt_cmp_ge (float a, float b, float c, float d) +{ + return (a >= b) ? c : d; +} + +float +flt_cmp_lt (float a, float b, float c, float d) +{ + return (a < b) ? c : d; +} + +float +flt_cmp_le (float a, float b, float c, float d) +{ + return (a <= b) ? c : d; +} + +double +dbl_flt_max1 (float a, float b) +{ + return (a > b) ? a : b; +} + +double +dbl_flt_max2 (double a, float b) +{ + return (a > b) ? a : b; +} + +double +dbl_flt_max3 (float a, double b) +{ + return (a > b) ? a : b; +} + +double +dbl_flt_min1 (float a, float b) +{ + return (a < b) ? a : b; +} + +double +dbl_flt_min2 (double a, float b) +{ + return (a < b) ? a : b; +} + +double +dbl_flt_min3 (float a, double b) +{ + return (a < b) ? a : b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c new file mode 100644 index 00000000000..f6742142966 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c @@ -0,0 +1,191 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2 -mpower9-minmax" } */ +/* { dg-final { scan-assembler-not "fsel" } } */ +/* { dg-final { scan-assembler "xscmpeqdp" } } */ +/* { dg-final { scan-assembler "xscmpgtdp" } } */ +/* { dg-final { scan-assembler-not "xscmpodp" } } */ +/* { dg-final { scan-assembler-not "xscmpudp" } } */ +/* { dg-final { scan-assembler "xsmaxcdp" } } */ +/* { dg-final { scan-assembler-not "xsmaxdp" } } */ +/* { dg-final { scan-assembler "xsmincdp" } } */ +/* { dg-final { scan-assembler-not "xsmindp" } } */ +/* { dg-final { scan-assembler "xxsel" } } */ + +/* Due to NaN support, <= and >= are not handled presently unless -ffast-math + is used. At some point this will be fixed and the xscmpgedp instruction can + be generated normally. The <= and >= tests are bracketed with + #ifdef DO_GE_LE. */ + +#ifdef DO_GE_LE +double +dbl_max1 (double a, double b) +{ + return (a >= b) ? a : b; +} +#endif + +double +dbl_max2 (double a, double b) +{ + return (a > b) ? a : b; +} + +double +dbl_min1 (double a, double b) +{ + return (a < b) ? a : b; +} + +#ifdef DO_GE_LE +double +dbl_min2 (double a, double b) +{ + return (a <= b) ? a : b; +} +#endif + +double +dbl_cmp_eq (double a, double b, double c, double d) +{ + return (a == b) ? c : d; +} + +double +dbl_cmp_ne (double a, double b, double c, double d) +{ + return (a != b) ? c : d; +} + +double +dbl_cmp_gt (double a, double b, double c, double d) +{ + return (a > b) ? c : d; +} + +#ifdef DO_GE_LE +double +dbl_cmp_ge (double a, double b, double c, double d) +{ + return (a >= b) ? c : d; +} +#endif + +double +dbl_cmp_lt (double a, double b, double c, double d) +{ + return (a < b) ? c : d; +} + +#ifdef DO_GE_LE +double +dbl_cmp_le (double a, double b, double c, double d) +{ + return (a <= b) ? c : d; +} +#endif + +#ifdef DO_GE_LE +float +flt_max1 (float a, float b) +{ + return (a >= b) ? a : b; +} +#endif + +float +flt_max2 (float a, float b) +{ + return (a > b) ? a : b; +} + +float +flt_min1 (float a, float b) +{ + return (a < b) ? a : b; +} + +#ifdef DO_GE_LE +float +flt_min2 (float a, float b) +{ + return (a <= b) ? a : b; +} +#endif + +float +flt_cmp_eq (float a, float b, float c, float d) +{ + return (a == b) ? c : d; +} + +float +flt_cmp_ne (float a, float b, float c, float d) +{ + return (a != b) ? c : d; +} + +float +flt_cmp_gt (float a, float b, float c, float d) +{ + return (a > b) ? c : d; +} + +#ifdef DO_GE_LE +float +flt_cmp_ge (float a, float b, float c, float d) +{ + return (a >= b) ? c : d; +} +#endif + +float +flt_cmp_lt (float a, float b, float c, float d) +{ + return (a < b) ? c : d; +} + +#ifdef DO_GE_LE +float +flt_cmp_le (float a, float b, float c, float d) +{ + return (a <= b) ? c : d; +} +#endif + +double +dbl_flt_max1 (float a, float b) +{ + return (a > b) ? a : b; +} + +double +dbl_flt_max2 (double a, float b) +{ + return (a > b) ? a : b; +} + +double +dbl_flt_max3 (float a, double b) +{ + return (a > b) ? a : b; +} + +double +dbl_flt_min1 (float a, float b) +{ + return (a < b) ? a : b; +} + +double +dbl_flt_min2 (double a, float b) +{ + return (a < b) ? a : b; +} + +double +dbl_flt_min3 (float a, double b) +{ + return (a < b) ? a : b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-1.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-1.c new file mode 100644 index 00000000000..13b72872d74 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ + +#include <altivec.h> + +vector int +foo_r (int a) +{ + return (vector int) { a, a, a, a }; /* mtvsrws */ +} + +vector int +foo_r2 (int a) +{ + return vec_splats (a); /* mtvsrws */ +} + +vector int +foo_p (int *a) +{ + return (vector int) { *a, *a, *a, *a }; /* lxvwsx */ +} + +/* { dg-final { scan-assembler-times "mtvsrws" 2 } } */ +/* { dg-final { scan-assembler-times "lxvwsx" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c new file mode 100644 index 00000000000..2468e92dddb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c @@ -0,0 +1,38 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ + +#include <altivec.h> + +vector float +foo_r (float a) +{ + return (vector float) { a, a, a, a }; /* xscvdpspn/xxspltw */ +} + +vector float +foo_r2 (float a) +{ + return vec_splats (a); /* xscvdpspn/xxspltw */ +} + +vector float +foo_g (float *a) +{ + float f = *a; + + __asm__ (" # %0" : "+r" (f)); + return (vector float) { f, f, f, f }; /* mtvsrws */ +} + +vector float +foo_p (float *a) +{ + return (vector float) { *a, *a, *a, *a }; /* lxvwsx */ +} + +/* { dg-final { scan-assembler-times "xscvdpspn" 2 } } */ +/* { dg-final { scan-assembler-times "xxspltw" 2 } } */ +/* { dg-final { scan-assembler-times "mtvsrws" 1 } } */ +/* { dg-final { scan-assembler-times "lxvwsx" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-3.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-3.c new file mode 100644 index 00000000000..8a121da2572 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-3.c @@ -0,0 +1,61 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ + +#include <altivec.h> + +typedef vector signed char v16qi_t; +typedef vector short v8hi_t; +typedef vector int v4si_t; +typedef vector long long v2di_t; + +void v16qi_0a (v16qi_t *p) { *p = (v16qi_t) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; } +void v8hi_0a (v8hi_t *p) { *p = (v8hi_t) { 0, 0, 0, 0, 0, 0, 0, 0 }; } +void v4si_0a (v4si_t *p) { *p = (v4si_t) { 0, 0, 0, 0 }; } +void v2di_0a (v2di_t *p) { *p = (v2di_t) { 0, 0 }; } + +void v16qi_0b (v16qi_t *p) { *p = (v16qi_t) vec_splats ((signed char)0); } +void v8hi_0b (v8hi_t *p) { *p = (v8hi_t) vec_splats ((short)0); } +void v4si_0b (v4si_t *p) { *p = (v4si_t) vec_splats ((int)0); } +void v2di_0b (v2di_t *p) { *p = (v2di_t) vec_splats ((long long)0); } + +void v16qi_m1a (v16qi_t *p) { *p = (v16qi_t) { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 }; } +void v8hi_m1a (v8hi_t *p) { *p = (v8hi_t) { -1, -1, -1, -1, -1, -1, -1, -1 }; } +void v4si_m1a (v4si_t *p) { *p = (v4si_t) { -1, -1, -1, -1 }; } +void v2di_m1a (v2di_t *p) { *p = (v2di_t) { -1, -1 }; } + +void v16qi_m1b (v16qi_t *p) { *p = (v16qi_t) vec_splats ((signed char)-1); } +void v8hi_m1b (v8hi_t *p) { *p = (v8hi_t) vec_splats ((short)-1); } +void v4si_m1b (v4si_t *p) { *p = (v4si_t) vec_splats ((int)-1); } +void v2di_m1b (v2di_t *p) { *p = (v2di_t) vec_splats ((long long)-1); } + +void v16qi_5a (v16qi_t *p) { *p = (v16qi_t) { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; } +void v8hi_5a (v8hi_t *p) { *p = (v8hi_t) { 5, 5, 5, 5, 5, 5, 5, 5 }; } +void v4si_5a (v4si_t *p) { *p = (v4si_t) { 5, 5, 5, 5 }; } +void v2di_5a (v2di_t *p) { *p = (v2di_t) { 5, 5 }; } + +void v16qi_5b (v16qi_t *p) { *p = (v16qi_t) vec_splats ((signed char)5); } +void v8hi_5b (v8hi_t *p) { *p = (v8hi_t) vec_splats ((short)5); } +void v4si_5b (v4si_t *p) { *p = (v4si_t) vec_splats ((int)5); } +void v2di_5b (v2di_t *p) { *p = (v2di_t) vec_splats ((long long)5); } + +void v16qi_33a (v16qi_t *p) { *p = (v16qi_t) { 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33 }; } +void v8hi_33a (v8hi_t *p) { *p = (v8hi_t) { 33, 33, 33, 33, 33, 33, 33, 33 }; } +void v4si_33a (v4si_t *p) { *p = (v4si_t) { 33, 33, 33, 33 }; } +void v2di_33a (v2di_t *p) { *p = (v2di_t) { 33, 33 }; } + +void v16qi_33b (v16qi_t *p) { *p = (v16qi_t) vec_splats ((signed char)33); } +void v8hi_33b (v8hi_t *p) { *p = (v8hi_t) vec_splats ((short)33); } +void v4si_33b (v4si_t *p) { *p = (v4si_t) vec_splats ((int)33); } +void v2di_33b (v2di_t *p) { *p = (v2di_t) vec_splats ((long long)33); } + +/* { dg-final { scan-assembler "xxspltib" } } */ +/* { dg-final { scan-assembler "vextsb2d" } } */ +/* { dg-final { scan-assembler "vextsb2w" } } */ +/* { dg-final { scan-assembler "vupk\[hl\]sb" } } */ +/* { dg-final { scan-assembler-not "lxvd2x" } } */ +/* { dg-final { scan-assembler-not "lxvw4x" } } */ +/* { dg-final { scan-assembler-not "lxv " } } */ +/* { dg-final { scan-assembler-not "lxvx" } } */ +/* { dg-final { scan-assembler-not "lvx" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c new file mode 100644 index 00000000000..d643324afe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ + +#include <altivec.h> + +vector long long foo (long long a) { return (vector long long) { a, a }; } + +/* { dg-final { scan-assembler "mtvsrdd" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vneg.c b/gcc/testsuite/gcc.target/powerpc/p9-vneg.c new file mode 100644 index 00000000000..10041c94fae --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-vneg.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { powerpc64*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +/* Verify P9 vector negate instructions. */ + +vector long long v2di_neg (vector long long a) { return -a; } +vector int v4si_neg (vector int a) { return -a; } + +/* { dg-final { scan-assembler "vnegd" } } */ +/* { dg-final { scan-assembler "vnegw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c new file mode 100644 index 00000000000..e4c20870717 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c @@ -0,0 +1,107 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2 -mlra -mvsx-timode" } */ + +#include <altivec.h> + +vector int +parity_v4si_1s (vector int a) +{ + return vec_vprtyb (a); +} + +vector int +parity_v4si_2s (vector int a) +{ + return vec_vprtybw (a); +} + +vector unsigned int +parity_v4si_1u (vector unsigned int a) +{ + return vec_vprtyb (a); +} + +vector unsigned int +parity_v4si_2u (vector unsigned int a) +{ + return vec_vprtybw (a); +} + +vector long long +parity_v2di_1s (vector long long a) +{ + return vec_vprtyb (a); +} + +vector long long +parity_v2di_2s (vector long long a) +{ + return vec_vprtybd (a); +} + +vector unsigned long long +parity_v2di_1u (vector unsigned long long a) +{ + return vec_vprtyb (a); +} + +vector unsigned long long +parity_v2di_2u (vector unsigned long long a) +{ + return vec_vprtybd (a); +} + +vector __int128_t +parity_v1ti_1s (vector __int128_t a) +{ + return vec_vprtyb (a); +} + +vector __int128_t +parity_v1ti_2s (vector __int128_t a) +{ + return vec_vprtybq (a); +} + +__int128_t +parity_ti_3s (__int128_t a) +{ + return vec_vprtyb (a); +} + +__int128_t +parity_ti_4s (__int128_t a) +{ + return vec_vprtybq (a); +} + +vector __uint128_t +parity_v1ti_1u (vector __uint128_t a) +{ + return vec_vprtyb (a); +} + +vector __uint128_t +parity_v1ti_2u (vector __uint128_t a) +{ + return vec_vprtybq (a); +} + +__uint128_t +parity_ti_3u (__uint128_t a) +{ + return vec_vprtyb (a); +} + +__uint128_t +parity_ti_4u (__uint128_t a) +{ + return vec_vprtybq (a); +} + +/* { dg-final { scan-assembler "vprtybd" } } */ +/* { dg-final { scan-assembler "vprtybq" } } */ +/* { dg-final { scan-assembler "vprtybw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vpermr.c b/gcc/testsuite/gcc.target/powerpc/p9-vpermr.c new file mode 100644 index 00000000000..7e7a266e1ec --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-vpermr.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +/* Test generation of VPERMR/XXPERMR on ISA 3.0 in little endian. */ + +#include <altivec.h> + +vector long long +permute (vector long long *p, vector long long *q, vector unsigned char mask) +{ + vector long long a = *p; + vector long long b = *q; + + /* Force a, b to be in altivec registers to select vpermr insn. */ + __asm__ (" # a: %x0, b: %x1" : "+v" (a), "+v" (b)); + + return vec_perm (a, b, mask); +} + +/* { dg-final { scan-assembler "vpermr\|xxpermr" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr70963.c b/gcc/testsuite/gcc.target/powerpc/pr70963.c new file mode 100644 index 00000000000..128ebd9f09f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr70963.c @@ -0,0 +1,44 @@ +/* { dg-do run { target powerpc64*-*-* } } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <stdlib.h> +#include <stdio.h> +#include <altivec.h> + +static int failed; +static void test (void); + +static void check (int result, const char *name) +{ + if (!result) + { + failed++; + printf ("fail %s\n", name); + } +} + +int main (void) +{ + test (); + if (failed) + abort (); + return 0; +} + +vector double x = { 81.0, 76.0 }; +vector long long y = { 81, 76 }; + +static void test() +{ + vector long long a = vec_cts (x, 0); + vector double b = vec_ctf (a, 0); + vector long long c = __builtin_vsx_xvcvdpuxds_scale (x, 0); + vector double d = vec_ctf (c, 0); + check (vec_all_eq (a, y), "vec_cts"); + check (vec_all_eq (b, x), "vec_ctf"); + check (vec_all_eq (c, y), "xvcvdpuxds"); + check (vec_all_eq (d, x), "vec_ctf unsigned"); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr71186.c b/gcc/testsuite/gcc.target/powerpc/pr71186.c new file mode 100644 index 00000000000..22762ccafb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71186.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ + +static unsigned short x[(16384/sizeof(unsigned short))] __attribute__ ((aligned (16))); +static unsigned short y[(16384/sizeof(unsigned short))] __attribute__ ((aligned (16))); +static unsigned short a; + +void obfuscate(void *a, ...); + +static void __attribute__((noinline)) do_one(void) +{ + unsigned long i; + + obfuscate(x, y, &a); + + for (i = 0; i < (16384/sizeof(unsigned short)); i++) + y[i] = a * x[i]; + + obfuscate(x, y, &a); +} + +int main(void) +{ + unsigned long i; + + for (i = 0; i < 1000000; i++) + do_one(); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr71493-1.c b/gcc/testsuite/gcc.target/powerpc/pr71493-1.c new file mode 100644 index 00000000000..9ec9da0fbed --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71493-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { powerpc*-*-linux* && ilp32 } } } */ +/* { dg-options "-O2 -msvr4-struct-return" } */ + +struct S1 { float f; }; + +struct S1 foo1 (void) +{ + struct S1 s = { 1.0f }; + return s; +} + +/* { dg-final { scan-assembler "lwz" } } */ +/* { dg-final { scan-assembler-not "lfs" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr71493-2.c b/gcc/testsuite/gcc.target/powerpc/pr71493-2.c new file mode 100644 index 00000000000..e9184a605be --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71493-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { powerpc*-*-linux* && ilp32 } } } */ +/* { dg-options "-O2 -msvr4-struct-return" } */ + +struct S2 { double d; }; + +struct S2 foo2 (void) +{ + struct S2 s = { 1.0 }; + return s; +} + +/* { dg-final { scan-assembler "lwz" } } */ +/* { dg-final { scan-assembler-not "lfd" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c new file mode 100644 index 00000000000..fa6b4ffb816 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c @@ -0,0 +1,20 @@ +/* Test for reload ICE arising from POWER9 Vector Dform code generation. */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector -mno-lra" } */ + +typedef __attribute__((altivec(vector__))) int type_t; +type_t +func (type_t *src) +{ + asm volatile ("# force the base reg on the load below to be spilled" + : /* no outputs */ + : /* no inputs */ + : "r0", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"); + return src[1]; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c new file mode 100644 index 00000000000..99855fa1667 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c @@ -0,0 +1,47 @@ +/* Test for reload ICE arising from POWER9 Vector Dform code generation. */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -mno-lra -funroll-loops -fno-aggressive-loop-optimizations" } */ + +typedef double vec[3]; +struct vec_t +{ + vec x; + vec y; +}; +int a, j, k, l, m, n, o, p, q; +double b, i; +vec c; +double h[6]; +void func1 (vec); + +void +func2 (double *b) +{ + for (; k; k--) + for (; j <= k;) + for (; m <= q; m++) + for (; n <= k; n++) + for (; o <= l; o++) + { + j = p + m + n + o; + h[j] = i; + } +} + +void +func3 (void) +{ + struct vec_t d; + func1 (d.y); + func2 (&b); + for (; a;) + { + double *e = d.y, *g; + double f; + c[0] = g[0] + f * e[0]; + c[1] = g[1] + f * e[1]; + func1 (c); + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr71670.c b/gcc/testsuite/gcc.target/powerpc/pr71670.c new file mode 100644 index 00000000000..18fb62759d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71670.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O1" } */ + +volatile int a; +int b; +void fn1(void) { b + (long)b || a; } diff --git a/gcc/testsuite/gcc.target/powerpc/pr71698.c b/gcc/testsuite/gcc.target/powerpc/pr71698.c new file mode 100644 index 00000000000..c752f64e1c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71698.c @@ -0,0 +1,13 @@ +/* Test for a reload ICE arising from trying to direct move a TDmode value. */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target dfp } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-O1 -mcpu=power9 -mno-lra" } */ + +extern void testvad128 (int n, ...); +void +testitd128 (_Decimal128 g01d128) +{ + testvad128 (1, g01d128); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr71720.c b/gcc/testsuite/gcc.target/powerpc/pr71720.c new file mode 100644 index 00000000000..732daf97595 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71720.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +/* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat. */ + +vector float +splat_v4sf (float f) +{ + return (vector float) { f, f, f, f }; +} + +/* { dg-final { scan-assembler "xscvdpspn " } } */ +/* { dg-final { scan-assembler "xxspltw .*,.*,0" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr71763.c b/gcc/testsuite/gcc.target/powerpc/pr71763.c new file mode 100644 index 00000000000..b36ddfa26b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71763.c @@ -0,0 +1,25 @@ +// PR target/71763 +// { dg-do compile } +// { dg-options "-O1 -mvsx" } + +int a, b; +float c; + +void fn2(void); + +void fn1(void) +{ + long d; + + for (d = 3; d; d--) { + for (a = 0; a <= 1; a++) { + b &= 1; + if (b) { + for (;;) { + fn2(); + c = d; + } + } + } + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr71805.c b/gcc/testsuite/gcc.target/powerpc/pr71805.c new file mode 100644 index 00000000000..02db059dff9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71805.c @@ -0,0 +1,113 @@ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O3 --param tree-reassoc-width=1" } */ + +/* Originally from gcc.dg/vect/pr45752.c. */ +#include <stdarg.h> + +#ifdef __cplusplus +extern "C" { +#endif +extern void abort (void); +extern void exit (int); +#ifdef __cplusplus +} +#endif + +#define M00 100 +#define M10 216 +#define M20 23 +#define M30 237 +#define M40 437 + +#define M01 1322 +#define M11 13 +#define M21 27271 +#define M31 2280 +#define M41 284 + +#define M02 74 +#define M12 191 +#define M22 500 +#define M32 111 +#define M42 1114 + +#define M03 134 +#define M13 117 +#define M23 11 +#define M33 771 +#define M43 71 + +#define M04 334 +#define M14 147 +#define M24 115 +#define M34 7716 +#define M44 16 + +#define N 20 + +void foo (unsigned int *__restrict__ pInput, + unsigned int *__restrict__ pOutput, + unsigned int *__restrict__ pInput2, + unsigned int *__restrict__ pOutput2) +{ + unsigned int i, a, b, c, d, e; + + for (i = 0; i < N / 5; i++) + { + a = *pInput++; + b = *pInput++; + c = *pInput++; + d = *pInput++; + e = *pInput++; + + *pOutput++ = M00 * a + M01 * b + M02 * c + M03 * d + M04 * e; + *pOutput++ = M10 * a + M11 * b + M12 * c + M13 * d + M14 * e; + *pOutput++ = M20 * a + M21 * b + M22 * c + M23 * d + M24 * e; + *pOutput++ = M30 * a + M31 * b + M32 * c + M33 * d + M34 * e; + *pOutput++ = M40 * a + M41 * b + M42 * c + M43 * d + M44 * e; + + + a = *pInput2++; + b = *pInput2++; + c = *pInput2++; + d = *pInput2++; + e = *pInput2++; + + *pOutput2++ = M00 * a + M01 * b + M02 * c + M03 * d + M04 * e; + *pOutput2++ = M10 * a + M11 * b + M12 * c + M13 * d + M14 * e; + *pOutput2++ = M20 * a + M21 * b + M22 * c + M23 * d + M24 * e; + *pOutput2++ = M30 * a + M31 * b + M32 * c + M33 * d + M34 * e; + *pOutput2++ = M40 * a + M41 * b + M42 * c + M43 * d + M44 * e; + + } +} + +int main (int argc, const char* argv[]) +{ + unsigned int input[N], output[N], i, input2[N], output2[N]; + unsigned int check_results[N] + = {3208, 1334, 28764, 35679, 2789, 13028, 4754, 168364, 91254, 12399, + 22848, 8174, 307964, 146829, 22009, 32668, 11594, 447564, 202404, 31619 }; + unsigned int check_results2[N] + = {7136, 2702, 84604, 57909, 6633, 16956, 6122, 224204, 113484, 16243, + 26776, 9542, 363804, 169059, 25853, 36596, 12962, 503404, 224634, 35463 }; + + for (i = 0; i < N; i++) + { + input[i] = i%256; + input2[i] = i + 2; + output[i] = 0; + output2[i] = 0; + __asm__ volatile (""); + } + + foo (input, output, input2, output2); + + for (i = 0; i < N; i++) + if (output[i] != check_results[i] + || output2[i] != check_results2[i]) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr72853.c b/gcc/testsuite/gcc.target/powerpc/pr72853.c new file mode 100644 index 00000000000..8eae7d4a41d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr72853.c @@ -0,0 +1,108 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O3 -mupper-regs-df -mupper-regs-sf -funroll-loops" } */ + +/* derived from 20021120-1.c, compiled for -mcpu=power9. */ + +extern void abort (void); +extern void exit (int); + +volatile double gd[32]; +volatile float gf[32]; + +void +foo (int n) +{ + double d00, d10, d20, d30, d01, d11, d21, d31, d02, d12, d22, d32, d03, d13, + d23, d33, d04, d14, d24, d34, d05, d15, d25, d35, d06, d16, d26, d36, d07, + d17, d27, d37; + float f00, f10, f20, f30, f01, f11, f21, f31, f02, f12, f22, f32, f03, f13, + f23, f33, f04, f14, f24, f34, f05, f15, f25, f35, f06, f16, f26, f36, f07, + f17, f27, f37; + volatile double *pd; + volatile float *pf; + int i; + + pd = gd; + d00 = *(pd++), d10 = *(pd++), d20 = *(pd++), d30 = *(pd++), d01 = + *(pd++), d11 = *(pd++), d21 = *(pd++), d31 = *(pd++), d02 = *(pd++), d12 = + *(pd++), d22 = *(pd++), d32 = *(pd++), d03 = *(pd++), d13 = *(pd++), d23 = + *(pd++), d33 = *(pd++), d04 = *(pd++), d14 = *(pd++), d24 = *(pd++), d34 = + *(pd++), d05 = *(pd++), d15 = *(pd++), d25 = *(pd++), d35 = *(pd++), d06 = + *(pd++), d16 = *(pd++), d26 = *(pd++), d36 = *(pd++), d07 = *(pd++), d17 = + *(pd++), d27 = *(pd++), d37 = *(pd++); + for (i = 0; i < n; i++) + { + pf = gf; + f00 = *(pf++), f10 = *(pf++), f20 = *(pf++), f30 = *(pf++), f01 = + *(pf++), f11 = *(pf++), f21 = *(pf++), f31 = *(pf++), f02 = + *(pf++), f12 = *(pf++), f22 = *(pf++), f32 = *(pf++), f03 = + *(pf++), f13 = *(pf++), f23 = *(pf++), f33 = *(pf++), f04 = + *(pf++), f14 = *(pf++), f24 = *(pf++), f34 = *(pf++), f05 = + *(pf++), f15 = *(pf++), f25 = *(pf++), f35 = *(pf++), f06 = + *(pf++), f16 = *(pf++), f26 = *(pf++), f36 = *(pf++), f07 = + *(pf++), f17 = *(pf++), f27 = *(pf++), f37 = *(pf++); + pd = gd; + d00 += *(pd++), d10 += *(pd++), d20 += *(pd++), d30 += *(pd++), d01 += + *(pd++), d11 += *(pd++), d21 += *(pd++), d31 += *(pd++), d02 += + *(pd++), d12 += *(pd++), d22 += *(pd++), d32 += *(pd++), d03 += + *(pd++), d13 += *(pd++), d23 += *(pd++), d33 += *(pd++), d04 += + *(pd++), d14 += *(pd++), d24 += *(pd++), d34 += *(pd++), d05 += + *(pd++), d15 += *(pd++), d25 += *(pd++), d35 += *(pd++), d06 += + *(pd++), d16 += *(pd++), d26 += *(pd++), d36 += *(pd++), d07 += + *(pd++), d17 += *(pd++), d27 += *(pd++), d37 += *(pd++); + pd = gd; + d00 += *(pd++), d10 += *(pd++), d20 += *(pd++), d30 += *(pd++), d01 += + *(pd++), d11 += *(pd++), d21 += *(pd++), d31 += *(pd++), d02 += + *(pd++), d12 += *(pd++), d22 += *(pd++), d32 += *(pd++), d03 += + *(pd++), d13 += *(pd++), d23 += *(pd++), d33 += *(pd++), d04 += + *(pd++), d14 += *(pd++), d24 += *(pd++), d34 += *(pd++), d05 += + *(pd++), d15 += *(pd++), d25 += *(pd++), d35 += *(pd++), d06 += + *(pd++), d16 += *(pd++), d26 += *(pd++), d36 += *(pd++), d07 += + *(pd++), d17 += *(pd++), d27 += *(pd++), d37 += *(pd++); + pd = gd; + d00 += *(pd++), d10 += *(pd++), d20 += *(pd++), d30 += *(pd++), d01 += + *(pd++), d11 += *(pd++), d21 += *(pd++), d31 += *(pd++), d02 += + *(pd++), d12 += *(pd++), d22 += *(pd++), d32 += *(pd++), d03 += + *(pd++), d13 += *(pd++), d23 += *(pd++), d33 += *(pd++), d04 += + *(pd++), d14 += *(pd++), d24 += *(pd++), d34 += *(pd++), d05 += + *(pd++), d15 += *(pd++), d25 += *(pd++), d35 += *(pd++), d06 += + *(pd++), d16 += *(pd++), d26 += *(pd++), d36 += *(pd++), d07 += + *(pd++), d17 += *(pd++), d27 += *(pd++), d37 += *(pd++); + pf = gf; + *(pf++) = f00, *(pf++) = f10, *(pf++) = f20, *(pf++) = f30, *(pf++) = + f01, *(pf++) = f11, *(pf++) = f21, *(pf++) = f31, *(pf++) = + f02, *(pf++) = f12, *(pf++) = f22, *(pf++) = f32, *(pf++) = + f03, *(pf++) = f13, *(pf++) = f23, *(pf++) = f33, *(pf++) = + f04, *(pf++) = f14, *(pf++) = f24, *(pf++) = f34, *(pf++) = + f05, *(pf++) = f15, *(pf++) = f25, *(pf++) = f35, *(pf++) = + f06, *(pf++) = f16, *(pf++) = f26, *(pf++) = f36, *(pf++) = + f07, *(pf++) = f17, *(pf++) = f27, *(pf++) = f37; + } + pd = gd; + *(pd++) = d00, *(pd++) = d10, *(pd++) = d20, *(pd++) = d30, *(pd++) = + d01, *(pd++) = d11, *(pd++) = d21, *(pd++) = d31, *(pd++) = d02, *(pd++) = + d12, *(pd++) = d22, *(pd++) = d32, *(pd++) = d03, *(pd++) = d13, *(pd++) = + d23, *(pd++) = d33, *(pd++) = d04, *(pd++) = d14, *(pd++) = d24, *(pd++) = + d34, *(pd++) = d05, *(pd++) = d15, *(pd++) = d25, *(pd++) = d35, *(pd++) = + d06, *(pd++) = d16, *(pd++) = d26, *(pd++) = d36, *(pd++) = d07, *(pd++) = + d17, *(pd++) = d27, *(pd++) = d37; +} + +int +main () +{ + int i; + + for (i = 0; i < 32; i++) + gd[i] = i, gf[i] = i; + foo (1); + for (i = 0; i < 32; i++) + if (gd[i] != i * 4 || gf[i] != i) + abort (); + exit (0); +} + +/* { dg-final { scan-assembler-not "stxsd \[0-9\]+,\[0-9\]+,\[0-9\]" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/signbit-1.c b/gcc/testsuite/gcc.target/powerpc/signbit-1.c new file mode 100644 index 00000000000..bdfeb702663 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/signbit-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O2 -mfloat128" } */ + +int do_signbit_kf (__float128 a) { return __builtin_signbit (a); } +int do_signbit_if (__ibm128 a) { return __builtin_signbit (a); } +int do_signbit_tf (long double a) { return __builtin_signbit (a); } + +/* { dg-final { scan-assembler-not "stxvd2x" } } */ +/* { dg-final { scan-assembler-not "stxvw4x" } } */ +/* { dg-final { scan-assembler-not "stxsd" } } */ +/* { dg-final { scan-assembler-not "stxsdx" } } */ +/* { dg-final { scan-assembler-times "mfvsrd" 3 } } */ +/* { dg-final { scan-assembler-times "srdi" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/signbit-2.c b/gcc/testsuite/gcc.target/powerpc/signbit-2.c new file mode 100644 index 00000000000..b5bd856d909 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/signbit-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2 -mfloat128" } */ + +int do_signbit_kf (__float128 *a) { return __builtin_signbit (*a); } + +/* { dg-final { scan-assembler-not "stxvd2x" } } */ +/* { dg-final { scan-assembler-not "stxvw4x" } } */ +/* { dg-final { scan-assembler-not "stxsd" } } */ +/* { dg-final { scan-assembler-not "stxsdx" } } */ +/* { dg-final { scan-assembler-not "lxvd2x" } } */ +/* { dg-final { scan-assembler-not "lxvw4x" } } */ +/* { dg-final { scan-assembler-not "lxsd" } } */ +/* { dg-final { scan-assembler-not "lxsdx" } } */ +/* { dg-final { scan-assembler-times "ld" 1 } } */ +/* { dg-final { scan-assembler-times "srdi" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/signbit-3.c b/gcc/testsuite/gcc.target/powerpc/signbit-3.c new file mode 100644 index 00000000000..cd64143fc2f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/signbit-3.c @@ -0,0 +1,172 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target ppc_float128_sw } */ +/* { dg-options "-mcpu=power7 -O2 -mfloat128 -lm" } */ + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <stddef.h> +#include <stdint.h> +#include <inttypes.h> +#include <stdlib.h> +#include <math.h> + +#if defined(__BIG_ENDIAN__) +struct ieee128 { + uint64_t upper; + uint64_t lower; +}; + +#elif defined(__LITTLE_ENDIAN__) +struct ieee128 { + uint64_t lower; + uint64_t upper; +}; + +#else +#error "Unknown system" +#endif + +union ieee_union { + __float128 f128; + struct ieee128 st128; +}; + +#ifdef DEBUG +static int num_errors = 0; + +__attribute__((__noinline__)) +static void +failure (int expected, int got, __float128 x) +{ + unsigned sign; + unsigned exponent; + uint64_t mantissa1; + uint64_t mantissa2; + uint64_t upper; + uint64_t lower; + + union ieee_union u; + + u.f128 = x; + upper = u.st128.upper; + lower = u.st128.lower; + + sign = (unsigned)((upper >> 63) & 1); + exponent = (unsigned)((upper >> 48) & ((((uint64_t)1) << 16) - 1)); + mantissa1 = (upper & ((((uint64_t)1) << 48) - 1)); + mantissa2 = lower; + + printf ("Expected %d, got %d, %c 0x%.4x 0x%.12" PRIx64 " 0x%.16" PRIx64, + expected, got, + sign ? '-' : '+', + exponent, + mantissa1, + mantissa2); + + num_errors++; +} + +#else + +#define failure(E, G, F) abort () +#endif + +__attribute__((__noinline__)) +static void +test_signbit_arg (__float128 f128, int expected) +{ + int sign = __builtin_signbit (f128); + + if ((expected != 0 && sign == 0) + || (expected == 0 && sign != 0)) + failure (f128, expected, sign); +} + +__attribute__((__noinline__)) +static void +test_signbit_mem (__float128 *ptr, int expected) +{ + int sign = __builtin_signbit (*ptr); + + if ((expected != 0 && sign == 0) + || (expected == 0 && sign != 0)) + failure (*ptr, expected, sign); +} + +__attribute__((__noinline__)) +static void +test_signbit_gpr (__float128 *ptr, int expected) +{ + __float128 f128 = *ptr; + int sign; + + __asm__ (" # %0" : "+r" (f128)); + + sign = __builtin_signbit (f128); + if ((expected != 0 && sign == 0) + || (expected == 0 && sign != 0)) + failure (f128, expected, sign); +} + +__attribute__((__noinline__)) +static void +test_signbit (__float128 f128, int expected) +{ +#ifdef DEBUG + union ieee_union u; + u.f128 = f128; + printf ("Expecting %d, trying %-5g " + "(0x%.16" PRIx64 " 0x%.16" PRIx64 ")\n", + expected, (double)f128, + u.st128.upper, u.st128.lower); +#endif + + test_signbit_arg (f128, expected); + test_signbit_mem (&f128, expected); + test_signbit_gpr (&f128, expected); +} + +int +main (void) +{ + union ieee_union u; + + test_signbit (+0.0q, 0); + test_signbit (+1.0q, 0); + + test_signbit (-0.0q, 1); + test_signbit (-1.0q, 1); + + test_signbit (__builtin_copysign (__builtin_infq (), +1.0q), 0); + test_signbit (__builtin_copysign (__builtin_infq (), -1.0q), 1); + + test_signbit (__builtin_copysign (__builtin_nanq (""), +1.0q), 0); + test_signbit (__builtin_copysign (__builtin_nanq (""), -1.0q), 1); + + /* force the bottom double word to have specific bits in the 'sign' bit to + make sure we are picking the right word. */ + u.f128 = 1.0q; + u.st128.lower = 0ULL; + test_signbit (u.f128, 0); + + u.st128.lower = ~0ULL; + test_signbit (u.f128, 0); + + u.f128 = -1.0q; + u.st128.lower = 0ULL; + test_signbit (u.f128, 1); + + u.st128.lower = ~0ULL; + test_signbit (u.f128, 1); + +#ifdef DEBUG + printf ("%d error(s) were found\n", num_errors); + if (num_errors) + return num_errors; +#endif + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c new file mode 100644 index 00000000000..4d66df8ffdf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned int +doAbsoluteDifferenceUnsignedInt (__vector unsigned int *p, + __vector unsigned int *q) +{ + __vector unsigned int source_1, source_2; + __vector unsigned int result; + + source_1 = *p; + source_2 = *q; + + result = __builtin_vec_vadu (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c new file mode 100644 index 00000000000..28c85655066 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned int +doAbsoluteDifferenceUnsignedIntMacro (__vector unsigned int *p, + __vector unsigned int *q) +{ + __vector unsigned int result, source_1, source_2; + + source_1 = *p; + source_2 = *q; + + result = vec_absd (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c new file mode 100644 index 00000000000..726c90478c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned short +doAbsoluteDifferenceUnsignedShort (__vector unsigned short *p, + __vector unsigned short *q) +{ + __vector unsigned short source_1, source_2; + __vector unsigned short result; + + source_1 = *p; + source_2 = *q; + + result = __builtin_vec_vadu (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c new file mode 100644 index 00000000000..d3618db7184 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned short +doAbsoluteDifferenceUnsignedShortMacro (__vector unsigned short *p, + __vector unsigned short *q) +{ + __vector unsigned short result, source_1, source_2; + + source_1 = *p; + source_2 = *q; + + result = vec_absd (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c new file mode 100644 index 00000000000..e5744d13994 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned char +doAbsoluteDifferenceUnsignedChar (__vector unsigned char *p, + __vector unsigned char *q) +{ + __vector unsigned char source_1, source_2; + __vector unsigned char result; + + source_1 = *p; + source_2 = *q; + + result = __builtin_vec_vadu (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsdub" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c new file mode 100644 index 00000000000..5dc14a956f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned char +doAbsoluteDifferenceUnsignedCharMacro (__vector unsigned char *p, + __vector unsigned char *q) +{ + __vector unsigned char result, source_1, source_2; + + source_1 = *p; + source_2 = *q; + + result = vec_absd (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsdub" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c b/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c new file mode 100644 index 00000000000..649811ae0ce --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned char +doAbsoluteDifferenceUnsigned (__vector unsigned char *p, + __vector unsigned char *q) +{ + __vector unsigned char source_1, source_2; + __vector unsigned char uc_result; + + source_1 = *p; + source_2 = *q; + + uc_result = __builtin_vec_vadub (source_1, source_2); + return uc_result; +} + +/* { dg-final { scan-assembler "vabsdub" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c b/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c new file mode 100644 index 00000000000..142c3d39af5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned char +doAbsoluteDifferenceUnsigned (__vector unsigned char *p, + __vector unsigned char *q) +{ + __vector unsigned char source_1, source_2; + __vector unsigned char uc_result; + + source_1 = *p; + source_2 = *q; + + uc_result = vec_absdb (source_1, source_2); + return uc_result; +} + +/* { dg-final { scan-assembler "vabsdub" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c b/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c new file mode 100644 index 00000000000..6d933b9aa78 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned short +doAbsoluteDifferenceUnsigned (__vector unsigned short *p, + __vector unsigned short *q) +{ + __vector unsigned short source_1, source_2; + __vector unsigned short us_result; + + source_1 = *p; + source_2 = *q; + + us_result = __builtin_vec_vaduh (source_1, source_2); + return us_result; +} + +/* { dg-final { scan-assembler "vabsduh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c b/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c new file mode 100644 index 00000000000..bf28b713b2c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned short +doAbsoluteDifferenceUnsignedMacro (__vector unsigned short *p, + __vector unsigned short *q) +{ + __vector unsigned short result, source_1, source_2; + + source_1 = *p; + source_2 = *q; + + result = vec_absdh (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c b/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c new file mode 100644 index 00000000000..5188d68e143 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned int +doAbsoluteDifferenceUnsigned (__vector unsigned int *p, + __vector unsigned int *q) +{ + __vector unsigned int source_1, source_2; + __vector unsigned int ui_result; + + source_1 = *p; + source_2 = *q; + + ui_result = __builtin_vec_vaduw (source_1, source_2); + return ui_result; +} + +/* { dg-final { scan-assembler "vabsduw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c b/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c new file mode 100644 index 00000000000..bf93d96d967 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned int +doAbsoluteDifferenceUnsignedMacro (__vector unsigned int *p, + __vector unsigned int *q) +{ + __vector unsigned int result, source_1, source_2; + + source_1 = *p; + source_2 = *q; + + result = vec_absdw (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vslv-0.c b/gcc/testsuite/gcc.target/powerpc/vslv-0.c new file mode 100644 index 00000000000..9ad04dd92e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vslv-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned char +doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q) +{ + __vector unsigned char result, input, shift_distance; + result = __builtin_vec_vslv (input, shift_distance); + return result; +} + +/* { dg-final { scan-assembler "vslv" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vslv-1.c b/gcc/testsuite/gcc.target/powerpc/vslv-1.c new file mode 100644 index 00000000000..2d09543c814 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vslv-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned char +doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q) +{ + __vector unsigned char result, input, shift_distance; + result = vec_slv (input, shift_distance); + return result; +} + +/* { dg-final { scan-assembler "vslv" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsrv-0.c b/gcc/testsuite/gcc.target/powerpc/vsrv-0.c new file mode 100644 index 00000000000..29c7e3fde20 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsrv-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned char +doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q) +{ + __vector unsigned char result, input, shift_distance; + result = __builtin_vec_vsrv (input, shift_distance); + return result; +} + +/* { dg-final { scan-assembler "vsrv" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsrv-1.c b/gcc/testsuite/gcc.target/powerpc/vsrv-1.c new file mode 100644 index 00000000000..cd3f714bd64 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsrv-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned char +doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q) +{ + __vector unsigned char result, input, shift_distance; + result = vec_srv (input, shift_distance); + return result; +} + +/* { dg-final { scan-assembler "vsrv" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-1.c new file mode 100644 index 00000000000..7ab6d446a23 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-1.c @@ -0,0 +1,143 @@ +/* { dg-do compile { target { powerpc64le*-*-* } } } */ +/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O0" } */ +/* { dg-final { scan-assembler-times "lxvd2x" 18 } } */ +/* { dg-final { scan-assembler-times "lxvw4x" 6 } } */ +/* { dg-final { scan-assembler-times "stxvd2x" 18 } } */ +/* { dg-final { scan-assembler-times "stxvw4x" 6 } } */ +/* { dg-final { scan-assembler-times "xxpermdi" 24 } } */ + +#include <altivec.h> + +extern vector double vd, *vdp; +extern vector signed long long vsll, *vsllp; +extern vector unsigned long long vull, *vullp; +extern vector float vf, *vfp; +extern vector signed int vsi, *vsip; +extern vector unsigned int vui, *vuip; +extern double *dp; +extern signed long long *sllp; +extern unsigned long long *ullp; +extern float *fp; +extern signed int *sip; +extern unsigned int *uip; + +void foo0 (void) +{ + vd = vec_xl (0, vdp); +} + +void foo1 (void) +{ + vsll = vec_xl (0, vsllp); +} + +void foo2 (void) +{ + vull = vec_xl (0, vullp); +} + +void foo3 (void) +{ + vf = vec_xl (0, vfp); +} + +void foo4 (void) +{ + vsi = vec_xl (0, vsip); +} + +void foo5 (void) +{ + vui = vec_xl (0, vuip); +} + +void foo6 (void) +{ + vec_xst (vd, 0, vdp); +} + +void foo7 (void) +{ + vec_xst (vsll, 0, vsllp); +} + +void foo8 (void) +{ + vec_xst (vull, 0, vullp); +} + +void foo9 (void) +{ + vec_xst (vf, 0, vfp); +} + +void foo10 (void) +{ + vec_xst (vsi, 0, vsip); +} + +void foo11 (void) +{ + vec_xst (vui, 0, vuip); +} + +void foo20 (void) +{ + vd = vec_xl (0, dp); +} + +void foo21 (void) +{ + vsll = vec_xl (0, sllp); +} + +void foo22 (void) +{ + vull = vec_xl (0, ullp); +} + +void foo23 (void) +{ + vf = vec_xl (0, fp); +} + +void foo24 (void) +{ + vsi = vec_xl (0, sip); +} + +void foo25 (void) +{ + vui = vec_xl (0, uip); +} + +void foo26 (void) +{ + vec_xst (vd, 0, dp); +} + +void foo27 (void) +{ + vec_xst (vsll, 0, sllp); +} + +void foo28 (void) +{ + vec_xst (vull, 0, ullp); +} + +void foo29 (void) +{ + vec_xst (vf, 0, fp); +} + +void foo30 (void) +{ + vec_xst (vsi, 0, sip); +} + +void foo31 (void) +{ + vec_xst (vui, 0, uip); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c new file mode 100644 index 00000000000..eb4a13081a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c @@ -0,0 +1,236 @@ +/* { dg-do compile { target { powerpc64le*-*-* } } } */ +/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O0" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-final { scan-assembler-times "lxvd2x" 6 } } */ +/* { dg-final { scan-assembler-times "lxvw4x" 6 } } */ +/* { dg-final { scan-assembler-times "lxvh8x" 4 } } */ +/* { dg-final { scan-assembler-times "lxvb16x" 4 } } */ +/* { dg-final { scan-assembler-times "stxvd2x" 6 } } */ +/* { dg-final { scan-assembler-times "stxvw4x" 6 } } */ +/* { dg-final { scan-assembler-times "stxvh8x" 4 } } */ +/* { dg-final { scan-assembler-times "stxvb16x" 4 } } */ + +#include <altivec.h> + +extern vector double vd, *vdp; +extern vector signed long long vsll, *vsllp; +extern vector unsigned long long vull, *vullp; +extern vector float vf, *vfp; +extern vector signed int vsi, *vsip; +extern vector unsigned int vui, *vuip; +extern vector signed short vss, *vssp; +extern vector unsigned short vus, *vusp; +extern vector signed char vsc, *vscp; +extern vector unsigned char vuc, *vucp; +extern double *dp; +extern signed long long *sllp; +extern unsigned long long *ullp; +extern float *fp; +extern signed int *sip; +extern unsigned int *uip; +extern signed short *ssp; +extern unsigned short *usp; +extern signed char *scp; +extern unsigned char *ucp; + +void foo0 (void) +{ + vd = vec_xl (0, vdp); +} + +void foo1 (void) +{ + vsll = vec_xl (0, vsllp); +} + +void foo2 (void) +{ + vull = vec_xl (0, vullp); +} + +void foo3 (void) +{ + vf = vec_xl (0, vfp); +} + +void foo4 (void) +{ + vsi = vec_xl (0, vsip); +} + +void foo5 (void) +{ + vui = vec_xl (0, vuip); +} + +void foo6 (void) +{ + vss = vec_xl (0, vssp); +} + +void foo7 (void) +{ + vus = vec_xl (0, vusp); +} + +void foo8 (void) +{ + vsc = vec_xl (0, vscp); +} + +void foo9 (void) +{ + vuc = vec_xl (0, vucp); +} + +void foo10 (void) +{ + vec_xst (vd, 0, vdp); +} + +void foo11 (void) +{ + vec_xst (vsll, 0, vsllp); +} + +void foo12 (void) +{ + vec_xst (vull, 0, vullp); +} + +void foo13 (void) +{ + vec_xst (vf, 0, vfp); +} + +void foo14 (void) +{ + vec_xst (vsi, 0, vsip); +} + +void foo15 (void) +{ + vec_xst (vui, 0, vuip); +} + +void foo16 (void) +{ + vec_xst (vss, 0, vssp); +} + +void foo17 (void) +{ + vec_xst (vus, 0, vusp); +} + +void foo18 (void) +{ + vec_xst (vsc, 0, vscp); +} + +void foo19 (void) +{ + vec_xst (vuc, 0, vucp); +} + +void foo20 (void) +{ + vd = vec_xl (0, dp); +} + +void foo21 (void) +{ + vsll = vec_xl (0, sllp); +} + +void foo22 (void) +{ + vull = vec_xl (0, ullp); +} + +void foo23 (void) +{ + vf = vec_xl (0, fp); +} + +void foo24 (void) +{ + vsi = vec_xl (0, sip); +} + +void foo25 (void) +{ + vui = vec_xl (0, uip); +} + +void foo26 (void) +{ + vss = vec_xl (0, ssp); +} + +void foo27 (void) +{ + vus = vec_xl (0, usp); +} + +void foo28 (void) +{ + vsc = vec_xl (0, scp); +} + +void foo29 (void) +{ + vuc = vec_xl (0, ucp); +} + +void foo30 (void) +{ + vec_xst (vd, 0, dp); +} + +void foo31 (void) +{ + vec_xst (vsll, 0, sllp); +} + +void foo32 (void) +{ + vec_xst (vull, 0, ullp); +} + +void foo33 (void) +{ + vec_xst (vf, 0, fp); +} + +void foo34 (void) +{ + vec_xst (vsi, 0, sip); +} + +void foo35 (void) +{ + vec_xst (vui, 0, uip); +} + +void foo36 (void) +{ + vec_xst (vss, 0, ssp); +} + +void foo37 (void) +{ + vec_xst (vus, 0, usp); +} + +void foo38 (void) +{ + vec_xst (vsc, 0, scp); +} + +void foo39 (void) +{ + vec_xst (vuc, 0, ucp); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-3.c new file mode 100644 index 00000000000..2888c171c4f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-3.c @@ -0,0 +1,142 @@ +/* { dg-do compile { target { powerpc64-*-* } } } */ +/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O0" } */ +/* { dg-final { scan-assembler-times "lxvd2x" 16 } } */ +/* { dg-final { scan-assembler-times "lxvw4x" 8 } } */ +/* { dg-final { scan-assembler-times "stxvd2x" 16 } } */ +/* { dg-final { scan-assembler-times "stxvw4x" 8 } } */ + +#include <altivec.h> + +extern vector double vd, *vdp; +extern vector signed long long vsll, *vsllp; +extern vector unsigned long long vull, *vullp; +extern vector float vf, *vfp; +extern vector signed int vsi, *vsip; +extern vector unsigned int vui, *vuip; +extern double *dp; +extern signed long long *sllp; +extern unsigned long long *ullp; +extern float *fp; +extern signed int *sip; +extern unsigned int *uip; + +void foo0 (void) +{ + vd = vec_xl (0, vdp); +} + +void foo1 (void) +{ + vsll = vec_xl (0, vsllp); +} + +void foo2 (void) +{ + vull = vec_xl (0, vullp); +} + +void foo3 (void) +{ + vf = vec_xl (0, vfp); +} + +void foo4 (void) +{ + vsi = vec_xl (0, vsip); +} + +void foo5 (void) +{ + vui = vec_xl (0, vuip); +} + +void foo6 (void) +{ + vec_xst (vd, 0, vdp); +} + +void foo7 (void) +{ + vec_xst (vsll, 0, vsllp); +} + +void foo8 (void) +{ + vec_xst (vull, 0, vullp); +} + +void foo9 (void) +{ + vec_xst (vf, 0, vfp); +} + +void foo10 (void) +{ + vec_xst (vsi, 0, vsip); +} + +void foo11 (void) +{ + vec_xst (vui, 0, vuip); +} + +void foo20 (void) +{ + vd = vec_xl (0, dp); +} + +void foo21 (void) +{ + vsll = vec_xl (0, sllp); +} + +void foo22 (void) +{ + vull = vec_xl (0, ullp); +} + +void foo23 (void) +{ + vf = vec_xl (0, fp); +} + +void foo24 (void) +{ + vsi = vec_xl (0, sip); +} + +void foo25 (void) +{ + vui = vec_xl (0, uip); +} + +void foo26 (void) +{ + vec_xst (vd, 0, dp); +} + +void foo27 (void) +{ + vec_xst (vsll, 0, sllp); +} + +void foo28 (void) +{ + vec_xst (vull, 0, ullp); +} + +void foo29 (void) +{ + vec_xst (vf, 0, fp); +} + +void foo30 (void) +{ + vec_xst (vsi, 0, sip); +} + +void foo31 (void) +{ + vec_xst (vui, 0, uip); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c new file mode 100644 index 00000000000..a116316c174 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c @@ -0,0 +1,230 @@ +/* { dg-do compile { target { powerpc64-*-* } } } */ +/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O0" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-final { scan-assembler-times "lxvx" 40 } } */ +/* { dg-final { scan-assembler-times "stxvx" 40 } } */ + +#include <altivec.h> + +extern vector double vd, *vdp; +extern vector signed long long vsll, *vsllp; +extern vector unsigned long long vull, *vullp; +extern vector float vf, *vfp; +extern vector signed int vsi, *vsip; +extern vector unsigned int vui, *vuip; +extern vector signed short vss, *vssp; +extern vector unsigned short vus, *vusp; +extern vector signed char vsc, *vscp; +extern vector unsigned char vuc, *vucp; +extern double *dp; +extern signed long long *sllp; +extern unsigned long long *ullp; +extern float *fp; +extern signed int *sip; +extern unsigned int *uip; +extern signed short *ssp; +extern unsigned short *usp; +extern signed char *scp; +extern unsigned char *ucp; + +void foo0 (void) +{ + vd = vec_xl (0, vdp); +} + +void foo1 (void) +{ + vsll = vec_xl (0, vsllp); +} + +void foo2 (void) +{ + vull = vec_xl (0, vullp); +} + +void foo3 (void) +{ + vf = vec_xl (0, vfp); +} + +void foo4 (void) +{ + vsi = vec_xl (0, vsip); +} + +void foo5 (void) +{ + vui = vec_xl (0, vuip); +} + +void foo6 (void) +{ + vss = vec_xl (0, vssp); +} + +void foo7 (void) +{ + vus = vec_xl (0, vusp); +} + +void foo8 (void) +{ + vsc = vec_xl (0, vscp); +} + +void foo9 (void) +{ + vuc = vec_xl (0, vucp); +} + +void foo10 (void) +{ + vec_xst (vd, 0, vdp); +} + +void foo11 (void) +{ + vec_xst (vsll, 0, vsllp); +} + +void foo12 (void) +{ + vec_xst (vull, 0, vullp); +} + +void foo13 (void) +{ + vec_xst (vf, 0, vfp); +} + +void foo14 (void) +{ + vec_xst (vsi, 0, vsip); +} + +void foo15 (void) +{ + vec_xst (vui, 0, vuip); +} + +void foo16 (void) +{ + vec_xst (vss, 0, vssp); +} + +void foo17 (void) +{ + vec_xst (vus, 0, vusp); +} + +void foo18 (void) +{ + vec_xst (vsc, 0, vscp); +} + +void foo19 (void) +{ + vec_xst (vuc, 0, vucp); +} + +void foo20 (void) +{ + vd = vec_xl (0, dp); +} + +void foo21 (void) +{ + vsll = vec_xl (0, sllp); +} + +void foo22 (void) +{ + vull = vec_xl (0, ullp); +} + +void foo23 (void) +{ + vf = vec_xl (0, fp); +} + +void foo24 (void) +{ + vsi = vec_xl (0, sip); +} + +void foo25 (void) +{ + vui = vec_xl (0, uip); +} + +void foo26 (void) +{ + vss = vec_xl (0, ssp); +} + +void foo27 (void) +{ + vus = vec_xl (0, usp); +} + +void foo28 (void) +{ + vsc = vec_xl (0, scp); +} + +void foo29 (void) +{ + vuc = vec_xl (0, ucp); +} + +void foo30 (void) +{ + vec_xst (vd, 0, dp); +} + +void foo31 (void) +{ + vec_xst (vsll, 0, sllp); +} + +void foo32 (void) +{ + vec_xst (vull, 0, ullp); +} + +void foo33 (void) +{ + vec_xst (vf, 0, fp); +} + +void foo34 (void) +{ + vec_xst (vsi, 0, sip); +} + +void foo35 (void) +{ + vec_xst (vui, 0, uip); +} + +void foo36 (void) +{ + vec_xst (vss, 0, ssp); +} + +void foo37 (void) +{ + vec_xst (vus, 0, usp); +} + +void foo38 (void) +{ + vec_xst (vsc, 0, scp); +} + +void foo39 (void) +{ + vec_xst (vuc, 0, ucp); +} diff --git a/gcc/testsuite/gcc.target/s390/nolrl-1.c b/gcc/testsuite/gcc.target/s390/nolrl-1.c new file mode 100644 index 00000000000..e0d1213f78f --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/nolrl-1.c @@ -0,0 +1,19 @@ +/* Make sure the compiler does not try to use a relative long + instruction to load the string since it might not meet the + alignment requirements of the instruction. */ + +/* { dg-do compile } */ +/* { dg-options "-march=z10 -O3 -mzarch" } */ + +extern void foo (char*); + +void +bar () +{ + unsigned char z[32]; + + __builtin_memcpy (z, "\001\000\000\000", 4); + foo (z); +} + +/* { dg-final { scan-assembler-not "lrl" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fpcmp.c b/gcc/testsuite/gcc.target/sparc/fpcmp.c new file mode 100644 index 00000000000..1255d67442f --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fpcmp.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4" } */ + +typedef unsigned char vec8 __attribute__((vector_size(8))); + +long test_fpcmple8 (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmple8 (a, b); +} + +long test_fpcmpgt8 (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmpgt8 (a, b); +} + +/* { dg-final { scan-assembler "fpcmple8\t%" } } */ +/* { dg-final { scan-assembler "fpcmpgt8\t%" } } */ + diff --git a/gcc/testsuite/gcc.target/sparc/fpcmpu.c b/gcc/testsuite/gcc.target/sparc/fpcmpu.c new file mode 100644 index 00000000000..816a22d7078 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fpcmpu.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4" } */ + + +typedef short vec16 __attribute__((vector_size(8))); +typedef int vec32 __attribute__((vector_size(8))); + +long test_fpcmpule16 (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpule16 (a, b); +} + +long test_fpcmpugt16 (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpugt16 (a, b); +} + +long test_fpcmpule32 (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpule32 (a, b); +} + +long test_fpcmpugt32 (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpugt32 (a, b); +} + +/* { dg-final { scan-assembler "fpcmpule16\t%" } } */ +/* { dg-final { scan-assembler "fpcmpugt16\t%" } } */ +/* { dg-final { scan-assembler "fpcmpule32\t%" } } */ +/* { dg-final { scan-assembler "fpcmpugt32\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/vis4misc.c b/gcc/testsuite/gcc.target/sparc/vis4misc.c new file mode 100644 index 00000000000..b520b12b381 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vis4misc.c @@ -0,0 +1,126 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4" } */ +typedef int __v2si __attribute__((vector_size(8))); +typedef short __v4hi __attribute__((vector_size(8))); +typedef unsigned char __v8qi __attribute__((vector_size(8))); + +__v8qi test_fpadd8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpadd8 (x, y); +} + +__v8qi test_fpadds8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpadds8 (x, y); +} + +__v8qi test_fpaddus8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpaddus8 (x, y); +} + +__v4hi test_fpaddus16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpaddus16 (x, y); +} + +__v8qi test_fpsub8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpsub8 (x, y); +} + +__v8qi test_fpsubs8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpsubs8 (x, y); +} + +__v8qi test_fpsubus8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpsubus8 (x, y); +} + +__v4hi test_fpsubus16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpsubus16 (x, y); +} + +__v8qi test_fpmax8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpmax8 (x, y); +} + +__v4hi test_fpmax16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpmax16 (x, y); +} + +__v2si test_fpmax32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpmax32 (x, y); +} + +__v8qi test_fpmaxu8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpmaxu8 (x, y); +} + +__v4hi test_fpmaxu16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpmaxu16 (x, y); +} + +__v2si test_fpmaxu32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpmaxu32 (x, y); +} + +__v8qi test_fpmin8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpmin8 (x, y); +} + +__v4hi test_fpmin16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpmin16 (x, y); +} + +__v2si test_fpmin32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpmin32 (x, y); +} + +__v8qi test_fpminu8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpminu8 (x, y); +} + +__v4hi test_fpminu16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpminu16 (x, y); +} + +__v2si test_fpminu32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpminu32 (x, y); +} + +/* { dg-final { scan-assembler "fpadd8\t%" } } */ +/* { dg-final { scan-assembler "fpadds8\t%" } } */ +/* { dg-final { scan-assembler "fpaddus8\t%" } } */ +/* { dg-final { scan-assembler "fpaddus16\t%" } } */ +/* { dg-final { scan-assembler "fpsub8\t%" } } */ +/* { dg-final { scan-assembler "fpsubs8\t%" } } */ +/* { dg-final { scan-assembler "fpsubus8\t%" } } */ +/* { dg-final { scan-assembler "fpsubus16\t%" } } */ +/* { dg-final { scan-assembler "fpmax8\t%" } } */ +/* { dg-final { scan-assembler "fpmax16\t%" } } */ +/* { dg-final { scan-assembler "fpmax32\t%" } } */ +/* { dg-final { scan-assembler "fpmaxu8\t%" } } */ +/* { dg-final { scan-assembler "fpmaxu16\t%" } } */ +/* { dg-final { scan-assembler "fpmaxu32\t%" } } */ +/* { dg-final { scan-assembler "fpmin8\t%" } } */ +/* { dg-final { scan-assembler "fpmin16\t%" } } */ +/* { dg-final { scan-assembler "fpmin32\t%" } } */ +/* { dg-final { scan-assembler "fpminu8\t%" } } */ +/* { dg-final { scan-assembler "fpminu16\t%" } } */ +/* { dg-final { scan-assembler "fpminu32\t%" } } */ |